/* cr16-opc.c -- Table of opcodes for the CR16 processor.
- Copyright 2007 Free Software Foundation, Inc.
+ Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc.
Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com)
This file is part of the GNU opcodes library.
/* opc8 r r */ \
{NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
-/* for Logincal operations, allow unsinged imm16 also */
+/* For Logical operations, allow unsigned imm16 also. */
#define ARITH1_BYTE_INST(NAME, OPC, OP1) \
/* opc8 imm16 r */ \
{NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
/* Create a conditional branch instruction. */
#define BRANCH_INST(NAME, OPC) \
/* opc4 c4 dispe9 */ \
- {NAME, 1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}}, \
+ {NAME, 1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\
/* opc4 c4 disps17 */ \
- {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \
+ {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\
/* opc4 c4 disps25 */ \
- {NAME, 3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}}
+ {NAME, 3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}}
BRANCH_INST ("b", 0x1),
For example :
REG(u4, 0x84, CR16_U_REGTYPE)
is interpreted as :
- {"u4", u4, 0x84, CR16_U_REGTYPE} */
-#define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE}
+ {"u4", u4, 0x84, CR16_U_REGTYPE}
+ The union initializer (second member) always refers to the first
+ member of the union, so cast NAME to that type to avoid possible
+ compiler warnings when used for CR16_P_REGTYPE cases. */
+#define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE}
#define REGP(NAME, BNAME, N, TYPE) {STRINGX(NAME), {BNAME}, N, TYPE}
{4, arg_cc, OP_UNSIGNED} /* cc - code */
};
+const unsigned int cr16_num_optab = ARRAY_SIZE (cr16_optab);
/* CR16 traps/interrupts. */
const trap_entry cr16_traps[] =