/* d10v-opc.c -- D10V opcode list
- Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Written by Martin Hunt, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
{ "r13", NULL, OPERAND_GPR+13 },
{ "r14", NULL, OPERAND_GPR+14 },
{ "r14-r15", NULL, OPERAND_GPR+14 },
- { "r15", "sp", OPERAND_SP|OPERAND_GPR+15 },
+ { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) },
{ "r2", NULL, OPERAND_GPR+2 },
{ "r2-r3", NULL, OPERAND_GPR+2 },
{ "r3", NULL, OPERAND_GPR+3 },
{ "rpt_c", NULL, OPERAND_CONTROL+7 },
{ "rpt_e", NULL, OPERAND_CONTROL+9 },
{ "rpt_s", NULL, OPERAND_CONTROL+8 },
- { "sp", NULL, OPERAND_SP|OPERAND_GPR+15 },
+ { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
};
int
{ 4, 1, OPERAND_GPR|OPERAND_REG },
#define RSRC_SP (RSRC + 1)
{ 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG },
-#define RDST (RSRC_SP + 1)
+#define RSRC_NOSP (RSRC_SP + 1)
+ { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG },
+#define RDST (RSRC_NOSP + 1)
{ 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
#define ASRC (RDST + 1)
{ 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
{ "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } },
{ "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } },
{ "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } },
- { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RDST, UNUM4 } },
+ { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RSRC2, UNUM4 } },
{ "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } },
{ "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } },
{ "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
- { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } },
+ { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } },
{ "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
{ "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
- { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } },
+ { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } },
{ "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
{ "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
{ "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },