RISC-V: Add compressed instruction hints, and a few misc cleanups.

[deliverable/binutils-gdb.git] / opcodes / epiphany-asm.c

diff --git a/opcodes/epiphany-asm.c b/opcodes/epiphany-asm.c
index df347bdcccf611708b0440a6f678bea9babcb25f..cfb94dbfc538504d106dadda87a3635965d803b5 100644 (file)
--- a/opcodes/epiphany-asm.c
+++ b/opcodes/epiphany-asm.c
@@ -1,10 +1,11 @@
+/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-asm.in isn't
 
-   Copyright (C) 1996-2015 Free Software Foundation, Inc.
+   Copyright (C) 1996-2017 Free Software Foundation, Inc.
 
    This file is part of libopcodes.