[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED

[deliverable/binutils-gdb.git] / opcodes / fr30-ibld.c

diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c
index 12b17335ba86096ee67b69c3591772109bb95267..3ebecf92f941eeb71e6b828221c74ea38dfcfa1a 100644 (file)
--- a/opcodes/fr30-ibld.c
+++ b/opcodes/fr30-ibld.c
@@ -207,12 +207,19 @@ insert_normal (CGEN_CPU_DESC cd,
 #if CGEN_INT_INSN_P
 
   {
-    int shift;
+    int shift_within_word, shift_to_word, shift;
 
+    /* How to shift the value to BIT0 of the word.  */
+    shift_to_word = total_length - (word_offset + word_length);
+
+    /* How to shift the value to the field within the word.  */
     if (CGEN_INSN_LSB0_P)
-      shift = (word_offset + start + 1) - length;
+      shift_within_word = start + 1 - length;
     else
-      shift = total_length - (word_offset + start + length);
+      shift_within_word = word_length - start - length;
+
+    /* The total SHIFT, then mask in the value.  */
+    shift = shift_to_word + shift_within_word;
     *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
   }
 
@@ -874,7 +881,7 @@ fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
-        value = ((value) | (((-1UL) << (4))));
+        value = ((value) | (-16));
         fields->f_m4 = value;
       }
       break;