arc: Don't generate dynamic relocation for non SEC_ALLOC sections

[deliverable/binutils-gdb.git] / opcodes / frv-ibld.c

diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c
index 6dabd4fa005b6b4eba98adfca4bf6f98928d3fb1..0421884908714461a69f9136baa1b11c7881667e 100644 (file)
--- a/opcodes/frv-ibld.c
+++ b/opcodes/frv-ibld.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
    - the resultant file is machine generated, cgen-ibld.in isn't
 
-   Copyright (C) 1996-2019 Free Software Foundation, Inc.
+   Copyright (C) 1996-2020 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
 
@@ -480,7 +480,10 @@ extract_normal (CGEN_CPU_DESC cd,
        abort ();
 
       if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
-       return 0;
+       {
+         *valuep = 0;
+         return 0;
+       }
 
       value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
     }
@@ -1090,7 +1093,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (pc));
+        value = ((((value) * (4))) + (pc));
         fields->f_label16 = value;
       }
       break;
@@ -1101,7 +1104,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
         length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18);
         if (length <= 0) break;
 {
-  FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc));
+  FLD (f_label24) = ((((((((FLD (f_labelH6)) * (((1) << (18))))) | (FLD (f_labelL18)))) * (4))) + (pc));
 }
       }
       break;
@@ -1156,7 +1159,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
         length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l);
         if (length <= 0) break;
 {
-  FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l)));
+  FLD (f_u12) = ((((FLD (f_u12_h)) * (64))) | (FLD (f_u12_l)));
 }
       }
       break;