/* Print i386 instructions for GDB, the GNU debugger.
- Copyright (C) 1988-2018 Free Software Foundation, Inc.
+ Copyright (C) 1988-2020 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
#include "opintl.h"
#include "opcode/i386.h"
#include "libiberty.h"
+#include "safe-ctype.h"
#include <setjmp.h>
static void OP_XS (int, int);
static void OP_M (int, int);
static void OP_VEX (int, int);
-static void OP_EX_Vex (int, int);
-static void OP_EX_VexW (int, int);
-static void OP_EX_VexImmW (int, int);
-static void OP_XMM_Vex (int, int);
-static void OP_XMM_VexW (int, int);
+static void OP_VexR (int, int);
+static void OP_VexW (int, int);
static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
+static void OP_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
-static void VZERO_Fixup (int, int);
-static void VCMP_Fixup (int, int);
static void VPCMP_Fixup (int, int);
static void VPCOM_Fixup (int, int);
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
-static void OP_Mwaitx (int, int);
static void NOP_Fixup1 (int, int);
static void NOP_Fixup2 (int, int);
static void OP_3DNowSuffix (int, int);
static void CMP_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
+static void SEP_Fixup (int, int);
static void BND_Fixup (int, int);
static void NOTRACK_Fixup (int, int);
static void HLE_Fixup1 (int, int);
static void HLE_Fixup3 (int, int);
static void CMPXCHG8B_Fixup (int, int);
static void XMM_Fixup (int, int);
-static void CRC32_Fixup (int, int);
static void FXSAVE_Fixup (int, int);
-static void PCMPESTR_Fixup (int, int);
-static void OP_LWPCB_E (int, int);
-static void OP_LWP_E (int, int);
-static void OP_Vex_2src_1 (int, int);
-static void OP_Vex_2src_2 (int, int);
-static void MOVBE_Fixup (int, int);
+static void MOVSXD_Fixup (int, int);
static void OP_Mask (int, int);
static int rex;
/* Bits of REX we've already used. */
static int rex_used;
-/* REX bits in original REX prefix ignored. */
-static int rex_ignored;
/* Mark parts used in the REX prefix. When we are testing for
empty prefix (for 8bit register REX extension), just mask it
out. Otherwise test for REX bit is excuse for existence of REX
#define Edb { OP_E, db_mode }
#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
-#define Edqa { OP_E, dqa_mode }
#define Eq { OP_E, q_mode }
#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
+#define Mv { OP_M, v_mode }
#define Mv_bnd { OP_M, v_bndmk_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
#define Iv { OP_I, v_mode }
#define sIv { OP_sI, v_mode }
-#define Iq { OP_I, q_mode }
#define Iv64 { OP_I64, v_mode }
+#define Id { OP_I, d_mode }
#define Iw { OP_I, w_mode }
#define I1 { OP_I, const_1_mode }
#define Jb { OP_J, b_mode }
#define Jv { OP_J, v_mode }
+#define Jdqw { OP_J, dqw_mode }
#define Cm { OP_C, m_mode }
#define Dm { OP_D, m_mode }
#define Td { OP_T, d_mode }
#define RMDX { OP_REG, dx_reg }
#define eAX { OP_IMREG, eAX_reg }
-#define eBX { OP_IMREG, eBX_reg }
-#define eCX { OP_IMREG, eCX_reg }
-#define eDX { OP_IMREG, eDX_reg }
-#define eSP { OP_IMREG, eSP_reg }
-#define eBP { OP_IMREG, eBP_reg }
-#define eSI { OP_IMREG, eSI_reg }
-#define eDI { OP_IMREG, eDI_reg }
#define AL { OP_IMREG, al_reg }
#define CL { OP_IMREG, cl_reg }
-#define DL { OP_IMREG, dl_reg }
-#define BL { OP_IMREG, bl_reg }
-#define AH { OP_IMREG, ah_reg }
-#define CH { OP_IMREG, ch_reg }
-#define DH { OP_IMREG, dh_reg }
-#define BH { OP_IMREG, bh_reg }
-#define AX { OP_IMREG, ax_reg }
-#define DX { OP_IMREG, dx_reg }
#define zAX { OP_IMREG, z_mode_ax_reg }
#define indirDX { OP_IMREG, indir_dx_reg }
#define XMScalar { OP_XMM, scalar_mode }
#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
#define XMM { OP_XMM, xmm_mode }
+#define TMM { OP_XMM, tmm_mode }
#define XMxmmq { OP_XMM, xmmq_mode }
#define EM { OP_EM, v_mode }
#define EMS { OP_EM, v_swap_mode }
#define EMd { OP_EM, d_mode }
#define EMx { OP_EM, x_mode }
-#define EXbScalar { OP_EX, b_scalar_mode }
+#define EXbwUnit { OP_EX, bw_unit_mode }
#define EXw { OP_EX, w_mode }
-#define EXwScalar { OP_EX, w_scalar_mode }
#define EXd { OP_EX, d_mode }
-#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
-#define EXdScalarS { OP_EX, d_scalar_swap_mode }
#define EXq { OP_EX, q_mode }
-#define EXqScalar { OP_EX, q_scalar_mode }
-#define EXqScalarS { OP_EX, q_scalar_swap_mode }
#define EXqS { OP_EX, q_swap_mode }
#define EXx { OP_EX, x_mode }
#define EXxS { OP_EX, x_swap_mode }
#define EXxmm { OP_EX, xmm_mode }
#define EXymm { OP_EX, ymm_mode }
+#define EXtmm { OP_EX, tmm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
#define EXxmm_mb { OP_EX, xmm_mb_mode }
#define EXxmm_mw { OP_EX, xmm_mw_mode }
#define EXxmm_md { OP_EX, xmm_md_mode }
#define EXxmm_mq { OP_EX, xmm_mq_mode }
-#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define EMCq { OP_EMC, q_mode }
#define MXC { OP_MXC, 0 }
#define OPSUF { OP_3DNowSuffix, 0 }
+#define SEP { SEP_Fixup, 0 }
#define CMP { CMP_Fixup, 0 }
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
-#define Vex_2src_1 { OP_Vex_2src_1, 0 }
-#define Vex_2src_2 { OP_Vex_2src_2, 0 }
#define Vex { OP_VEX, vex_mode }
+#define VexW { OP_VexW, vex_mode }
#define VexScalar { OP_VEX, vex_scalar_mode }
+#define VexScalarR { OP_VexR, vex_scalar_mode }
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
-#define Vex128 { OP_VEX, vex128_mode }
-#define Vex256 { OP_VEX, vex256_mode }
#define VexGdq { OP_VEX, dq_mode }
-#define EXdVex { OP_EX_Vex, d_mode }
-#define EXdVexS { OP_EX_Vex, d_swap_mode }
-#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
-#define EXqVex { OP_EX_Vex, q_mode }
-#define EXqVexS { OP_EX_Vex, q_swap_mode }
-#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
-#define EXVexW { OP_EX_VexW, x_mode }
-#define EXdVexW { OP_EX_VexW, d_mode }
-#define EXqVexW { OP_EX_VexW, q_mode }
-#define EXVexImmW { OP_EX_VexImmW, x_mode }
-#define XMVex { OP_XMM_Vex, 0 }
-#define XMVexScalar { OP_XMM_Vex, scalar_mode }
-#define XMVexW { OP_XMM_VexW, 0 }
+#define VexTmm { OP_VEX, tmm_mode }
#define XMVexI4 { OP_REG_VexI4, x_mode }
+#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
+#define VexI4 { OP_VexI4, 0 }
#define PCLMUL { PCLMUL_Fixup, 0 }
-#define VZERO { VZERO_Fixup, 0 }
-#define VCMP { VCMP_Fixup, 0 }
#define VPCMP { VPCMP_Fixup, 0 }
#define VPCOM { VPCOM_Fixup, 0 }
#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
+#define MVexSIBMEM { OP_M, vex_sibmem_mode }
+
/* Used handle "rep" prefix for string instructions. */
#define Xbr { REP_Fixup, eSI_reg }
#define Xvr { REP_Fixup, eSI_reg }
x_mode,
/* Similar to x_mode, but with different EVEX mem shifts. */
evex_x_gscat_mode,
+ /* Similar to x_mode, but with yet different EVEX mem shifts. */
+ bw_unit_mode,
/* Similar to x_mode, but with disabled broadcast. */
evex_x_nobcst_mode,
/* Similar to x_mode, but with operands swapped and disabled broadcast
xmm_md_mode,
/* XMM register or quad word memory operand */
xmm_mq_mode,
- /* XMM register or double/quad word memory operand, depending on
- VEX.W. */
- xmm_mdq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
ymmq_mode,
/* 32-byte YMM or 16-byte word operand */
ymmxmm_mode,
+ /* TMM operand */
+ tmm_mode,
/* d_mode in 32bit, q_mode in 64bit mode. */
m_mode,
/* pair of v_mode operands */
a_mode,
cond_jump_mode,
loop_jcxz_mode,
+ movsxd_mode,
v_bnd_mode,
/* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
v_bndmk_mode,
/* operand size depends on REX prefixes. */
dq_mode,
- /* registers like dq_mode, memory like w_mode. */
+ /* registers like dq_mode, memory like w_mode, displacements like
+ v_mode without considering Intel64 ISA. */
dqw_mode,
/* bounds operand */
bnd_mode,
dw_mode,
/* registers like dq_mode, memory like d_mode. */
dqd_mode,
- /* operand size depends on the W bit as well as address mode. */
- dqa_mode,
/* normal vex mode */
vex_mode,
- /* 128bit vex mode */
- vex128_mode,
- /* 256bit vex mode */
- vex256_mode,
- /* operand size depends on the VEX.W bit. */
- vex_w_dq_mode,
-
- /* Similar to vex_w_dq_mode, with VSIB dword indices. */
+
+ /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
/* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
vex_vsib_d_w_d_mode,
- /* Similar to vex_w_dq_mode, with VSIB qword indices. */
+ /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
vex_vsib_q_w_dq_mode,
/* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
vex_vsib_q_w_d_mode,
+ /* mandatory non-vector SIB. */
+ vex_sibmem_mode,
/* scalar, ignore vector length. */
scalar_mode,
- /* like b_mode, ignore vector length. */
- b_scalar_mode,
- /* like w_mode, ignore vector length. */
- w_scalar_mode,
- /* like d_mode, ignore vector length. */
- d_scalar_mode,
- /* like d_swap_mode, ignore vector length. */
- d_scalar_swap_mode,
- /* like q_mode, ignore vector length. */
- q_scalar_mode,
- /* like q_swap_mode, ignore vector length. */
- q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
vex_scalar_mode,
- /* like vex_w_dq_mode, ignore vector length. */
+ /* Operand size depends on the VEX.W bit, ignore vector length. */
vex_scalar_w_dq_mode,
/* Static rounding. */
USE_VEX_C5_TABLE,
USE_VEX_LEN_TABLE,
USE_VEX_W_TABLE,
- USE_EVEX_TABLE
+ USE_EVEX_TABLE,
+ USE_EVEX_LEN_TABLE
};
#define FLOAT NULL, { { NULL, FLOATCODE } }, 0
#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
#define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
+#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
enum
{
REG_0F01,
REG_0F0D,
REG_0F18,
- REG_0F1C_MOD_0,
- REG_0F1E_MOD_3,
+ REG_0F1C_P_0_MOD_0,
+ REG_0F1E_P_1_MOD_3,
REG_0F71,
REG_0F72,
REG_0F73,
REG_VEX_0F72,
REG_VEX_0F73,
REG_VEX_0FAE,
+ REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
REG_VEX_0F38F3,
- REG_XOP_LWPCB,
- REG_XOP_LWP,
- REG_XOP_TBM_01,
- REG_XOP_TBM_02,
+
+ REG_0FXOP_09_01_L_0,
+ REG_0FXOP_09_02_L_0,
+ REG_0FXOP_09_12_M_1_L_0,
+ REG_0FXOP_0A_12_L_0,
REG_EVEX_0F71,
REG_EVEX_0F72,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
+ MOD_0F12_PREFIX_2,
MOD_0F13,
MOD_0F16_PREFIX_0,
+ MOD_0F16_PREFIX_2,
MOD_0F17,
MOD_0F18_REG_0,
MOD_0F18_REG_1,
MOD_0F2B_PREFIX_1,
MOD_0F2B_PREFIX_2,
MOD_0F2B_PREFIX_3,
- MOD_0F51,
+ MOD_0F50,
MOD_0F71_REG_2,
MOD_0F71_REG_4,
MOD_0F71_REG_6,
MOD_0FE7_PREFIX_2,
MOD_0FF0_PREFIX_3,
MOD_0F382A_PREFIX_2,
+ MOD_VEX_0F3849_X86_64_P_0_W_0,
+ MOD_VEX_0F3849_X86_64_P_2_W_0,
+ MOD_VEX_0F3849_X86_64_P_3_W_0,
+ MOD_VEX_0F384B_X86_64_P_1_W_0,
+ MOD_VEX_0F384B_X86_64_P_2_W_0,
+ MOD_VEX_0F384B_X86_64_P_3_W_0,
+ MOD_VEX_0F385C_X86_64_P_1_W_0,
+ MOD_VEX_0F385E_X86_64_P_0_W_0,
+ MOD_VEX_0F385E_X86_64_P_1_W_0,
+ MOD_VEX_0F385E_X86_64_P_2_W_0,
+ MOD_VEX_0F385E_X86_64_P_3_W_0,
MOD_0F38F5_PREFIX_2,
MOD_0F38F6_PREFIX_0,
+ MOD_0F38F8_PREFIX_1,
MOD_0F38F8_PREFIX_2,
+ MOD_0F38F8_PREFIX_3,
MOD_0F38F9_PREFIX_0,
MOD_62_32BIT,
MOD_C4_32BIT,
MOD_C5_32BIT,
MOD_VEX_0F12_PREFIX_0,
+ MOD_VEX_0F12_PREFIX_2,
MOD_VEX_0F13,
MOD_VEX_0F16_PREFIX_0,
+ MOD_VEX_0F16_PREFIX_2,
MOD_VEX_0F17,
MOD_VEX_0F2B,
MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F91_P_2_LEN_0,
MOD_VEX_W_0_0F92_P_0_LEN_0,
MOD_VEX_W_0_0F92_P_2_LEN_0,
- MOD_VEX_W_0_0F92_P_3_LEN_0,
- MOD_VEX_W_1_0F92_P_3_LEN_0,
+ MOD_VEX_0F92_P_3_LEN_0,
MOD_VEX_W_0_0F93_P_0_LEN_0,
MOD_VEX_W_0_0F93_P_2_LEN_0,
- MOD_VEX_W_0_0F93_P_3_LEN_0,
- MOD_VEX_W_1_0F93_P_3_LEN_0,
+ MOD_VEX_0F93_P_3_LEN_0,
MOD_VEX_W_0_0F98_P_0_LEN_0,
MOD_VEX_W_1_0F98_P_0_LEN_0,
MOD_VEX_W_0_0F98_P_2_LEN_0,
MOD_VEX_W_0_0F3A33_P_2_LEN_0,
MOD_VEX_W_1_0F3A33_P_2_LEN_0,
- MOD_EVEX_0F10_PREFIX_1,
- MOD_EVEX_0F10_PREFIX_3,
- MOD_EVEX_0F11_PREFIX_1,
- MOD_EVEX_0F11_PREFIX_3,
+ MOD_VEX_0FXOP_09_12,
+
MOD_EVEX_0F12_PREFIX_0,
+ MOD_EVEX_0F12_PREFIX_2,
+ MOD_EVEX_0F13,
MOD_EVEX_0F16_PREFIX_0,
+ MOD_EVEX_0F16_PREFIX_2,
+ MOD_EVEX_0F17,
+ MOD_EVEX_0F2B,
+ MOD_EVEX_0F381A_P_2_W_0,
+ MOD_EVEX_0F381A_P_2_W_1,
+ MOD_EVEX_0F381B_P_2_W_0,
+ MOD_EVEX_0F381B_P_2_W_1,
+ MOD_EVEX_0F385A_P_2_W_0,
+ MOD_EVEX_0F385A_P_2_W_1,
+ MOD_EVEX_0F385B_P_2_W_0,
+ MOD_EVEX_0F385B_P_2_W_1,
MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5,
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
- RM_0F01_REG_5,
- RM_0F01_REG_7,
- RM_0F1E_MOD_3_REG_7,
- RM_0FAE_REG_6,
- RM_0FAE_REG_7
+ RM_0F01_REG_5_MOD_3,
+ RM_0F01_REG_7_MOD_3,
+ RM_0F1E_P_1_MOD_3_REG_7,
+ RM_0FAE_REG_6_MOD_3_P_0,
+ RM_0FAE_REG_7_MOD_3,
+ RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
};
enum
{
PREFIX_90 = 0,
- PREFIX_MOD_0_0F01_REG_5,
- PREFIX_MOD_3_0F01_REG_5_RM_0,
- PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F01_REG_3_RM_1,
+ PREFIX_0F01_REG_5_MOD_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_1,
+ PREFIX_0F01_REG_5_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_3,
PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F7D,
PREFIX_0F7E,
PREFIX_0F7F,
- PREFIX_0FAE_REG_0,
- PREFIX_0FAE_REG_1,
- PREFIX_0FAE_REG_2,
- PREFIX_0FAE_REG_3,
- PREFIX_MOD_0_0FAE_REG_4,
- PREFIX_MOD_3_0FAE_REG_4,
- PREFIX_MOD_0_0FAE_REG_5,
- PREFIX_MOD_3_0FAE_REG_5,
- PREFIX_MOD_0_0FAE_REG_6,
- PREFIX_MOD_1_0FAE_REG_6,
- PREFIX_0FAE_REG_7,
+ PREFIX_0FAE_REG_0_MOD_3,
+ PREFIX_0FAE_REG_1_MOD_3,
+ PREFIX_0FAE_REG_2_MOD_3,
+ PREFIX_0FAE_REG_3_MOD_3,
+ PREFIX_0FAE_REG_4_MOD_0,
+ PREFIX_0FAE_REG_4_MOD_3,
+ PREFIX_0FAE_REG_5_MOD_0,
+ PREFIX_0FAE_REG_5_MOD_3,
+ PREFIX_0FAE_REG_6_MOD_0,
+ PREFIX_0FAE_REG_6_MOD_3,
+ PREFIX_0FAE_REG_7_MOD_0,
PREFIX_0FB8,
PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0FC2,
- PREFIX_MOD_0_0FC3,
- PREFIX_MOD_0_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_7,
+ PREFIX_0FC3_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_3,
+ PREFIX_0FC7_REG_7_MOD_3,
PREFIX_0FD0,
PREFIX_0FD6,
PREFIX_0FE6,
PREFIX_VEX_0F3845,
PREFIX_VEX_0F3846,
PREFIX_VEX_0F3847,
+ PREFIX_VEX_0F3849_X86_64,
+ PREFIX_VEX_0F384B_X86_64,
PREFIX_VEX_0F3858,
PREFIX_VEX_0F3859,
PREFIX_VEX_0F385A,
+ PREFIX_VEX_0F385C_X86_64,
+ PREFIX_VEX_0F385E_X86_64,
PREFIX_VEX_0F3878,
PREFIX_VEX_0F3879,
PREFIX_VEX_0F388C,
PREFIX_EVEX_0F10,
PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12,
- PREFIX_EVEX_0F13,
- PREFIX_EVEX_0F14,
- PREFIX_EVEX_0F15,
PREFIX_EVEX_0F16,
- PREFIX_EVEX_0F17,
- PREFIX_EVEX_0F28,
- PREFIX_EVEX_0F29,
PREFIX_EVEX_0F2A,
- PREFIX_EVEX_0F2B,
PREFIX_EVEX_0F2C,
PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E,
PREFIX_EVEX_0F2F,
PREFIX_EVEX_0F51,
- PREFIX_EVEX_0F54,
- PREFIX_EVEX_0F55,
- PREFIX_EVEX_0F56,
- PREFIX_EVEX_0F57,
PREFIX_EVEX_0F58,
PREFIX_EVEX_0F59,
PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E,
PREFIX_EVEX_0F5F,
- PREFIX_EVEX_0F60,
- PREFIX_EVEX_0F61,
- PREFIX_EVEX_0F62,
- PREFIX_EVEX_0F63,
PREFIX_EVEX_0F64,
PREFIX_EVEX_0F65,
PREFIX_EVEX_0F66,
- PREFIX_EVEX_0F67,
- PREFIX_EVEX_0F68,
- PREFIX_EVEX_0F69,
- PREFIX_EVEX_0F6A,
- PREFIX_EVEX_0F6B,
- PREFIX_EVEX_0F6C,
- PREFIX_EVEX_0F6D,
PREFIX_EVEX_0F6E,
PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70,
PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC4,
PREFIX_EVEX_0FC5,
- PREFIX_EVEX_0FC6,
- PREFIX_EVEX_0FD1,
- PREFIX_EVEX_0FD2,
- PREFIX_EVEX_0FD3,
- PREFIX_EVEX_0FD4,
- PREFIX_EVEX_0FD5,
PREFIX_EVEX_0FD6,
- PREFIX_EVEX_0FD8,
- PREFIX_EVEX_0FD9,
- PREFIX_EVEX_0FDA,
PREFIX_EVEX_0FDB,
- PREFIX_EVEX_0FDC,
- PREFIX_EVEX_0FDD,
- PREFIX_EVEX_0FDE,
PREFIX_EVEX_0FDF,
- PREFIX_EVEX_0FE0,
- PREFIX_EVEX_0FE1,
PREFIX_EVEX_0FE2,
- PREFIX_EVEX_0FE3,
- PREFIX_EVEX_0FE4,
- PREFIX_EVEX_0FE5,
PREFIX_EVEX_0FE6,
PREFIX_EVEX_0FE7,
- PREFIX_EVEX_0FE8,
- PREFIX_EVEX_0FE9,
- PREFIX_EVEX_0FEA,
PREFIX_EVEX_0FEB,
- PREFIX_EVEX_0FEC,
- PREFIX_EVEX_0FED,
- PREFIX_EVEX_0FEE,
PREFIX_EVEX_0FEF,
- PREFIX_EVEX_0FF1,
- PREFIX_EVEX_0FF2,
- PREFIX_EVEX_0FF3,
- PREFIX_EVEX_0FF4,
- PREFIX_EVEX_0FF5,
- PREFIX_EVEX_0FF6,
- PREFIX_EVEX_0FF8,
- PREFIX_EVEX_0FF9,
- PREFIX_EVEX_0FFA,
- PREFIX_EVEX_0FFB,
- PREFIX_EVEX_0FFC,
- PREFIX_EVEX_0FFD,
- PREFIX_EVEX_0FFE,
- PREFIX_EVEX_0F3800,
- PREFIX_EVEX_0F3804,
- PREFIX_EVEX_0F380B,
- PREFIX_EVEX_0F380C,
PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3810,
PREFIX_EVEX_0F3811,
PREFIX_EVEX_0F3814,
PREFIX_EVEX_0F3815,
PREFIX_EVEX_0F3816,
- PREFIX_EVEX_0F3818,
PREFIX_EVEX_0F3819,
PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B,
- PREFIX_EVEX_0F381C,
- PREFIX_EVEX_0F381D,
PREFIX_EVEX_0F381E,
PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3820,
PREFIX_EVEX_0F3828,
PREFIX_EVEX_0F3829,
PREFIX_EVEX_0F382A,
- PREFIX_EVEX_0F382B,
PREFIX_EVEX_0F382C,
PREFIX_EVEX_0F382D,
PREFIX_EVEX_0F3830,
PREFIX_EVEX_0F3839,
PREFIX_EVEX_0F383A,
PREFIX_EVEX_0F383B,
- PREFIX_EVEX_0F383C,
PREFIX_EVEX_0F383D,
- PREFIX_EVEX_0F383E,
PREFIX_EVEX_0F383F,
PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842,
PREFIX_EVEX_0F3853,
PREFIX_EVEX_0F3854,
PREFIX_EVEX_0F3855,
- PREFIX_EVEX_0F3858,
PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A,
PREFIX_EVEX_0F385B,
PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865,
PREFIX_EVEX_0F3866,
+ PREFIX_EVEX_0F3868,
PREFIX_EVEX_0F3870,
PREFIX_EVEX_0F3871,
PREFIX_EVEX_0F3872,
PREFIX_EVEX_0F3875,
PREFIX_EVEX_0F3876,
PREFIX_EVEX_0F3877,
- PREFIX_EVEX_0F3878,
- PREFIX_EVEX_0F3879,
PREFIX_EVEX_0F387A,
PREFIX_EVEX_0F387B,
PREFIX_EVEX_0F387C,
PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892,
PREFIX_EVEX_0F3893,
- PREFIX_EVEX_0F3896,
- PREFIX_EVEX_0F3897,
- PREFIX_EVEX_0F3898,
- PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A,
PREFIX_EVEX_0F389B,
- PREFIX_EVEX_0F389C,
- PREFIX_EVEX_0F389D,
- PREFIX_EVEX_0F389E,
- PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0,
PREFIX_EVEX_0F38A1,
PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3,
- PREFIX_EVEX_0F38A6,
- PREFIX_EVEX_0F38A7,
- PREFIX_EVEX_0F38A8,
- PREFIX_EVEX_0F38A9,
PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB,
- PREFIX_EVEX_0F38AC,
- PREFIX_EVEX_0F38AD,
- PREFIX_EVEX_0F38AE,
- PREFIX_EVEX_0F38AF,
PREFIX_EVEX_0F38B4,
PREFIX_EVEX_0F38B5,
- PREFIX_EVEX_0F38B6,
- PREFIX_EVEX_0F38B7,
- PREFIX_EVEX_0F38B8,
- PREFIX_EVEX_0F38B9,
- PREFIX_EVEX_0F38BA,
- PREFIX_EVEX_0F38BB,
- PREFIX_EVEX_0F38BC,
- PREFIX_EVEX_0F38BD,
- PREFIX_EVEX_0F38BE,
- PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4,
PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2,
PREFIX_EVEX_0F38CB,
PREFIX_EVEX_0F38CC,
PREFIX_EVEX_0F38CD,
- PREFIX_EVEX_0F38CF,
- PREFIX_EVEX_0F38DC,
- PREFIX_EVEX_0F38DD,
- PREFIX_EVEX_0F38DE,
- PREFIX_EVEX_0F38DF,
PREFIX_EVEX_0F3A00,
PREFIX_EVEX_0F3A01,
PREFIX_EVEX_0F3A03,
- PREFIX_EVEX_0F3A04,
PREFIX_EVEX_0F3A05,
PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09,
PREFIX_EVEX_0F3A0A,
PREFIX_EVEX_0F3A0B,
- PREFIX_EVEX_0F3A0F,
PREFIX_EVEX_0F3A14,
PREFIX_EVEX_0F3A15,
PREFIX_EVEX_0F3A16,
PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A,
PREFIX_EVEX_0F3A1B,
- PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E,
PREFIX_EVEX_0F3A1F,
PREFIX_EVEX_0F3A20,
PREFIX_EVEX_0F3A3F,
PREFIX_EVEX_0F3A42,
PREFIX_EVEX_0F3A43,
- PREFIX_EVEX_0F3A44,
PREFIX_EVEX_0F3A50,
PREFIX_EVEX_0F3A51,
PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72,
PREFIX_EVEX_0F3A73,
- PREFIX_EVEX_0F3ACE,
- PREFIX_EVEX_0F3ACF
};
enum
{
X86_64_06 = 0,
X86_64_07,
- X86_64_0D,
+ X86_64_0E,
X86_64_16,
X86_64_17,
X86_64_1E,
X86_64_6F,
X86_64_82,
X86_64_9A,
+ X86_64_C2,
+ X86_64_C3,
X86_64_C4,
X86_64_C5,
X86_64_CE,
X86_64_0F01_REG_0,
X86_64_0F01_REG_1,
X86_64_0F01_REG_2,
- X86_64_0F01_REG_3
+ X86_64_0F01_REG_3,
+ X86_64_VEX_0F3849,
+ X86_64_VEX_0F384B,
+ X86_64_VEX_0F385C,
+ X86_64_VEX_0F385E
};
enum
enum
{
- VEX_LEN_0F10_P_1 = 0,
- VEX_LEN_0F10_P_3,
- VEX_LEN_0F11_P_1,
- VEX_LEN_0F11_P_3,
- VEX_LEN_0F12_P_0_M_0,
+ VEX_LEN_0F12_P_0_M_0 = 0,
VEX_LEN_0F12_P_0_M_1,
- VEX_LEN_0F12_P_2,
+#define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
VEX_LEN_0F13_M_0,
VEX_LEN_0F16_P_0_M_0,
VEX_LEN_0F16_P_0_M_1,
- VEX_LEN_0F16_P_2,
+#define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
VEX_LEN_0F17_M_0,
- VEX_LEN_0F2A_P_1,
- VEX_LEN_0F2A_P_3,
- VEX_LEN_0F2C_P_1,
- VEX_LEN_0F2C_P_3,
- VEX_LEN_0F2D_P_1,
- VEX_LEN_0F2D_P_3,
- VEX_LEN_0F2E_P_0,
- VEX_LEN_0F2E_P_2,
- VEX_LEN_0F2F_P_0,
- VEX_LEN_0F2F_P_2,
VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2,
VEX_LEN_0F42_P_0,
VEX_LEN_0F4A_P_2,
VEX_LEN_0F4B_P_0,
VEX_LEN_0F4B_P_2,
- VEX_LEN_0F51_P_1,
- VEX_LEN_0F51_P_3,
- VEX_LEN_0F52_P_1,
- VEX_LEN_0F53_P_1,
- VEX_LEN_0F58_P_1,
- VEX_LEN_0F58_P_3,
- VEX_LEN_0F59_P_1,
- VEX_LEN_0F59_P_3,
- VEX_LEN_0F5A_P_1,
- VEX_LEN_0F5A_P_3,
- VEX_LEN_0F5C_P_1,
- VEX_LEN_0F5C_P_3,
- VEX_LEN_0F5D_P_1,
- VEX_LEN_0F5D_P_3,
- VEX_LEN_0F5E_P_1,
- VEX_LEN_0F5E_P_3,
- VEX_LEN_0F5F_P_1,
- VEX_LEN_0F5F_P_3,
VEX_LEN_0F6E_P_2,
+ VEX_LEN_0F77_P_0,
VEX_LEN_0F7E_P_1,
VEX_LEN_0F7E_P_2,
VEX_LEN_0F90_P_0,
VEX_LEN_0F99_P_2,
VEX_LEN_0FAE_R_2_M_0,
VEX_LEN_0FAE_R_3_M_0,
- VEX_LEN_0FC2_P_1,
- VEX_LEN_0FC2_P_3,
VEX_LEN_0FC4_P_2,
VEX_LEN_0FC5_P_2,
VEX_LEN_0FD6_P_2,
VEX_LEN_0F381A_P_2_M_0,
VEX_LEN_0F3836_P_2,
VEX_LEN_0F3841_P_2,
+ VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
+ VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
+ VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
+ VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
+ VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
+ VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
VEX_LEN_0F385A_P_2_M_0,
+ VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
VEX_LEN_0F38DB_P_2,
VEX_LEN_0F38F2_P_0,
VEX_LEN_0F38F3_R_1_P_0,
VEX_LEN_0F3A00_P_2,
VEX_LEN_0F3A01_P_2,
VEX_LEN_0F3A06_P_2,
- VEX_LEN_0F3A0A_P_2,
- VEX_LEN_0F3A0B_P_2,
VEX_LEN_0F3A14_P_2,
VEX_LEN_0F3A15_P_2,
VEX_LEN_0F3A16_P_2,
VEX_LEN_0F3A61_P_2,
VEX_LEN_0F3A62_P_2,
VEX_LEN_0F3A63_P_2,
- VEX_LEN_0F3A6A_P_2,
- VEX_LEN_0F3A6B_P_2,
- VEX_LEN_0F3A6E_P_2,
- VEX_LEN_0F3A6F_P_2,
- VEX_LEN_0F3A7A_P_2,
- VEX_LEN_0F3A7B_P_2,
- VEX_LEN_0F3A7E_P_2,
- VEX_LEN_0F3A7F_P_2,
VEX_LEN_0F3ADF_P_2,
VEX_LEN_0F3AF0_P_3,
+ VEX_LEN_0FXOP_08_85,
+ VEX_LEN_0FXOP_08_86,
+ VEX_LEN_0FXOP_08_87,
+ VEX_LEN_0FXOP_08_8E,
+ VEX_LEN_0FXOP_08_8F,
+ VEX_LEN_0FXOP_08_95,
+ VEX_LEN_0FXOP_08_96,
+ VEX_LEN_0FXOP_08_97,
+ VEX_LEN_0FXOP_08_9E,
+ VEX_LEN_0FXOP_08_9F,
+ VEX_LEN_0FXOP_08_A3,
+ VEX_LEN_0FXOP_08_A6,
+ VEX_LEN_0FXOP_08_B6,
+ VEX_LEN_0FXOP_08_C0,
+ VEX_LEN_0FXOP_08_C1,
+ VEX_LEN_0FXOP_08_C2,
+ VEX_LEN_0FXOP_08_C3,
VEX_LEN_0FXOP_08_CC,
VEX_LEN_0FXOP_08_CD,
VEX_LEN_0FXOP_08_CE,
VEX_LEN_0FXOP_08_ED,
VEX_LEN_0FXOP_08_EE,
VEX_LEN_0FXOP_08_EF,
- VEX_LEN_0FXOP_09_80,
- VEX_LEN_0FXOP_09_81
+ VEX_LEN_0FXOP_09_01,
+ VEX_LEN_0FXOP_09_02,
+ VEX_LEN_0FXOP_09_12_M_1,
+ VEX_LEN_0FXOP_09_82_W_0,
+ VEX_LEN_0FXOP_09_83_W_0,
+ VEX_LEN_0FXOP_09_90,
+ VEX_LEN_0FXOP_09_91,
+ VEX_LEN_0FXOP_09_92,
+ VEX_LEN_0FXOP_09_93,
+ VEX_LEN_0FXOP_09_94,
+ VEX_LEN_0FXOP_09_95,
+ VEX_LEN_0FXOP_09_96,
+ VEX_LEN_0FXOP_09_97,
+ VEX_LEN_0FXOP_09_98,
+ VEX_LEN_0FXOP_09_99,
+ VEX_LEN_0FXOP_09_9A,
+ VEX_LEN_0FXOP_09_9B,
+ VEX_LEN_0FXOP_09_C1,
+ VEX_LEN_0FXOP_09_C2,
+ VEX_LEN_0FXOP_09_C3,
+ VEX_LEN_0FXOP_09_C6,
+ VEX_LEN_0FXOP_09_C7,
+ VEX_LEN_0FXOP_09_CB,
+ VEX_LEN_0FXOP_09_D1,
+ VEX_LEN_0FXOP_09_D2,
+ VEX_LEN_0FXOP_09_D3,
+ VEX_LEN_0FXOP_09_D6,
+ VEX_LEN_0FXOP_09_D7,
+ VEX_LEN_0FXOP_09_DB,
+ VEX_LEN_0FXOP_09_E1,
+ VEX_LEN_0FXOP_09_E2,
+ VEX_LEN_0FXOP_09_E3,
+ VEX_LEN_0FXOP_0A_12,
+};
+
+enum
+{
+ EVEX_LEN_0F6E_P_2 = 0,
+ EVEX_LEN_0F7E_P_1,
+ EVEX_LEN_0F7E_P_2,
+ EVEX_LEN_0FC4_P_2,
+ EVEX_LEN_0FC5_P_2,
+ EVEX_LEN_0FD6_P_2,
+ EVEX_LEN_0F3816_P_2,
+ EVEX_LEN_0F3819_P_2_W_0,
+ EVEX_LEN_0F3819_P_2_W_1,
+ EVEX_LEN_0F381A_P_2_W_0_M_0,
+ EVEX_LEN_0F381A_P_2_W_1_M_0,
+ EVEX_LEN_0F381B_P_2_W_0_M_0,
+ EVEX_LEN_0F381B_P_2_W_1_M_0,
+ EVEX_LEN_0F3836_P_2,
+ EVEX_LEN_0F385A_P_2_W_0_M_0,
+ EVEX_LEN_0F385A_P_2_W_1_M_0,
+ EVEX_LEN_0F385B_P_2_W_0_M_0,
+ EVEX_LEN_0F385B_P_2_W_1_M_0,
+ EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2,
+ EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1,
+ EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1,
+ EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1,
+ EVEX_LEN_0F38C7_R_6_P_2_W_0,
+ EVEX_LEN_0F38C7_R_6_P_2_W_1,
+ EVEX_LEN_0F3A00_P_2_W_1,
+ EVEX_LEN_0F3A01_P_2_W_1,
+ EVEX_LEN_0F3A14_P_2,
+ EVEX_LEN_0F3A15_P_2,
+ EVEX_LEN_0F3A16_P_2,
+ EVEX_LEN_0F3A17_P_2,
+ EVEX_LEN_0F3A18_P_2_W_0,
+ EVEX_LEN_0F3A18_P_2_W_1,
+ EVEX_LEN_0F3A19_P_2_W_0,
+ EVEX_LEN_0F3A19_P_2_W_1,
+ EVEX_LEN_0F3A1A_P_2_W_0,
+ EVEX_LEN_0F3A1A_P_2_W_1,
+ EVEX_LEN_0F3A1B_P_2_W_0,
+ EVEX_LEN_0F3A1B_P_2_W_1,
+ EVEX_LEN_0F3A20_P_2,
+ EVEX_LEN_0F3A21_P_2_W_0,
+ EVEX_LEN_0F3A22_P_2,
+ EVEX_LEN_0F3A23_P_2_W_0,
+ EVEX_LEN_0F3A23_P_2_W_1,
+ EVEX_LEN_0F3A38_P_2_W_0,
+ EVEX_LEN_0F3A38_P_2_W_1,
+ EVEX_LEN_0F3A39_P_2_W_0,
+ EVEX_LEN_0F3A39_P_2_W_1,
+ EVEX_LEN_0F3A3A_P_2_W_0,
+ EVEX_LEN_0F3A3A_P_2_W_1,
+ EVEX_LEN_0F3A3B_P_2_W_0,
+ EVEX_LEN_0F3A3B_P_2_W_1,
+ EVEX_LEN_0F3A43_P_2_W_0,
+ EVEX_LEN_0F3A43_P_2_W_1
};
enum
{
- VEX_W_0F10_P_0 = 0,
- VEX_W_0F10_P_1,
- VEX_W_0F10_P_2,
- VEX_W_0F10_P_3,
- VEX_W_0F11_P_0,
- VEX_W_0F11_P_1,
- VEX_W_0F11_P_2,
- VEX_W_0F11_P_3,
- VEX_W_0F12_P_0_M_0,
- VEX_W_0F12_P_0_M_1,
- VEX_W_0F12_P_1,
- VEX_W_0F12_P_2,
- VEX_W_0F12_P_3,
- VEX_W_0F13_M_0,
- VEX_W_0F14,
- VEX_W_0F15,
- VEX_W_0F16_P_0_M_0,
- VEX_W_0F16_P_0_M_1,
- VEX_W_0F16_P_1,
- VEX_W_0F16_P_2,
- VEX_W_0F17_M_0,
- VEX_W_0F28,
- VEX_W_0F29,
- VEX_W_0F2B_M_0,
- VEX_W_0F2E_P_0,
- VEX_W_0F2E_P_2,
- VEX_W_0F2F_P_0,
- VEX_W_0F2F_P_2,
- VEX_W_0F41_P_0_LEN_1,
+ VEX_W_0F41_P_0_LEN_1 = 0,
VEX_W_0F41_P_2_LEN_1,
VEX_W_0F42_P_0_LEN_1,
VEX_W_0F42_P_2_LEN_1,
VEX_W_0F4A_P_2_LEN_1,
VEX_W_0F4B_P_0_LEN_1,
VEX_W_0F4B_P_2_LEN_1,
- VEX_W_0F50_M_0,
- VEX_W_0F51_P_0,
- VEX_W_0F51_P_1,
- VEX_W_0F51_P_2,
- VEX_W_0F51_P_3,
- VEX_W_0F52_P_0,
- VEX_W_0F52_P_1,
- VEX_W_0F53_P_0,
- VEX_W_0F53_P_1,
- VEX_W_0F58_P_0,
- VEX_W_0F58_P_1,
- VEX_W_0F58_P_2,
- VEX_W_0F58_P_3,
- VEX_W_0F59_P_0,
- VEX_W_0F59_P_1,
- VEX_W_0F59_P_2,
- VEX_W_0F59_P_3,
- VEX_W_0F5A_P_0,
- VEX_W_0F5A_P_1,
- VEX_W_0F5A_P_3,
- VEX_W_0F5B_P_0,
- VEX_W_0F5B_P_1,
- VEX_W_0F5B_P_2,
- VEX_W_0F5C_P_0,
- VEX_W_0F5C_P_1,
- VEX_W_0F5C_P_2,
- VEX_W_0F5C_P_3,
- VEX_W_0F5D_P_0,
- VEX_W_0F5D_P_1,
- VEX_W_0F5D_P_2,
- VEX_W_0F5D_P_3,
- VEX_W_0F5E_P_0,
- VEX_W_0F5E_P_1,
- VEX_W_0F5E_P_2,
- VEX_W_0F5E_P_3,
- VEX_W_0F5F_P_0,
- VEX_W_0F5F_P_1,
- VEX_W_0F5F_P_2,
- VEX_W_0F5F_P_3,
- VEX_W_0F60_P_2,
- VEX_W_0F61_P_2,
- VEX_W_0F62_P_2,
- VEX_W_0F63_P_2,
- VEX_W_0F64_P_2,
- VEX_W_0F65_P_2,
- VEX_W_0F66_P_2,
- VEX_W_0F67_P_2,
- VEX_W_0F68_P_2,
- VEX_W_0F69_P_2,
- VEX_W_0F6A_P_2,
- VEX_W_0F6B_P_2,
- VEX_W_0F6C_P_2,
- VEX_W_0F6D_P_2,
- VEX_W_0F6F_P_1,
- VEX_W_0F6F_P_2,
- VEX_W_0F70_P_1,
- VEX_W_0F70_P_2,
- VEX_W_0F70_P_3,
- VEX_W_0F71_R_2_P_2,
- VEX_W_0F71_R_4_P_2,
- VEX_W_0F71_R_6_P_2,
- VEX_W_0F72_R_2_P_2,
- VEX_W_0F72_R_4_P_2,
- VEX_W_0F72_R_6_P_2,
- VEX_W_0F73_R_2_P_2,
- VEX_W_0F73_R_3_P_2,
- VEX_W_0F73_R_6_P_2,
- VEX_W_0F73_R_7_P_2,
- VEX_W_0F74_P_2,
- VEX_W_0F75_P_2,
- VEX_W_0F76_P_2,
- VEX_W_0F77_P_0,
- VEX_W_0F7C_P_2,
- VEX_W_0F7C_P_3,
- VEX_W_0F7D_P_2,
- VEX_W_0F7D_P_3,
- VEX_W_0F7E_P_1,
- VEX_W_0F7F_P_1,
- VEX_W_0F7F_P_2,
VEX_W_0F90_P_0_LEN_0,
VEX_W_0F90_P_2_LEN_0,
VEX_W_0F91_P_0_LEN_0,
VEX_W_0F91_P_2_LEN_0,
VEX_W_0F92_P_0_LEN_0,
VEX_W_0F92_P_2_LEN_0,
- VEX_W_0F92_P_3_LEN_0,
VEX_W_0F93_P_0_LEN_0,
VEX_W_0F93_P_2_LEN_0,
- VEX_W_0F93_P_3_LEN_0,
VEX_W_0F98_P_0_LEN_0,
VEX_W_0F98_P_2_LEN_0,
VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0,
- VEX_W_0FAE_R_2_M_0,
- VEX_W_0FAE_R_3_M_0,
- VEX_W_0FC2_P_0,
- VEX_W_0FC2_P_1,
- VEX_W_0FC2_P_2,
- VEX_W_0FC2_P_3,
- VEX_W_0FC4_P_2,
- VEX_W_0FC5_P_2,
- VEX_W_0FD0_P_2,
- VEX_W_0FD0_P_3,
- VEX_W_0FD1_P_2,
- VEX_W_0FD2_P_2,
- VEX_W_0FD3_P_2,
- VEX_W_0FD4_P_2,
- VEX_W_0FD5_P_2,
- VEX_W_0FD6_P_2,
- VEX_W_0FD7_P_2_M_1,
- VEX_W_0FD8_P_2,
- VEX_W_0FD9_P_2,
- VEX_W_0FDA_P_2,
- VEX_W_0FDB_P_2,
- VEX_W_0FDC_P_2,
- VEX_W_0FDD_P_2,
- VEX_W_0FDE_P_2,
- VEX_W_0FDF_P_2,
- VEX_W_0FE0_P_2,
- VEX_W_0FE1_P_2,
- VEX_W_0FE2_P_2,
- VEX_W_0FE3_P_2,
- VEX_W_0FE4_P_2,
- VEX_W_0FE5_P_2,
- VEX_W_0FE6_P_1,
- VEX_W_0FE6_P_2,
- VEX_W_0FE6_P_3,
- VEX_W_0FE7_P_2_M_0,
- VEX_W_0FE8_P_2,
- VEX_W_0FE9_P_2,
- VEX_W_0FEA_P_2,
- VEX_W_0FEB_P_2,
- VEX_W_0FEC_P_2,
- VEX_W_0FED_P_2,
- VEX_W_0FEE_P_2,
- VEX_W_0FEF_P_2,
- VEX_W_0FF0_P_3_M_0,
- VEX_W_0FF1_P_2,
- VEX_W_0FF2_P_2,
- VEX_W_0FF3_P_2,
- VEX_W_0FF4_P_2,
- VEX_W_0FF5_P_2,
- VEX_W_0FF6_P_2,
- VEX_W_0FF7_P_2,
- VEX_W_0FF8_P_2,
- VEX_W_0FF9_P_2,
- VEX_W_0FFA_P_2,
- VEX_W_0FFB_P_2,
- VEX_W_0FFC_P_2,
- VEX_W_0FFD_P_2,
- VEX_W_0FFE_P_2,
- VEX_W_0F3800_P_2,
- VEX_W_0F3801_P_2,
- VEX_W_0F3802_P_2,
- VEX_W_0F3803_P_2,
- VEX_W_0F3804_P_2,
- VEX_W_0F3805_P_2,
- VEX_W_0F3806_P_2,
- VEX_W_0F3807_P_2,
- VEX_W_0F3808_P_2,
- VEX_W_0F3809_P_2,
- VEX_W_0F380A_P_2,
- VEX_W_0F380B_P_2,
VEX_W_0F380C_P_2,
VEX_W_0F380D_P_2,
VEX_W_0F380E_P_2,
VEX_W_0F380F_P_2,
+ VEX_W_0F3813_P_2,
VEX_W_0F3816_P_2,
- VEX_W_0F3817_P_2,
VEX_W_0F3818_P_2,
VEX_W_0F3819_P_2,
- VEX_W_0F381A_P_2_M_0,
- VEX_W_0F381C_P_2,
- VEX_W_0F381D_P_2,
- VEX_W_0F381E_P_2,
- VEX_W_0F3820_P_2,
- VEX_W_0F3821_P_2,
- VEX_W_0F3822_P_2,
- VEX_W_0F3823_P_2,
- VEX_W_0F3824_P_2,
- VEX_W_0F3825_P_2,
- VEX_W_0F3828_P_2,
- VEX_W_0F3829_P_2,
- VEX_W_0F382A_P_2_M_0,
- VEX_W_0F382B_P_2,
+ VEX_W_0F381A_P_2_M_0_L_0,
VEX_W_0F382C_P_2_M_0,
VEX_W_0F382D_P_2_M_0,
VEX_W_0F382E_P_2_M_0,
VEX_W_0F382F_P_2_M_0,
- VEX_W_0F3830_P_2,
- VEX_W_0F3831_P_2,
- VEX_W_0F3832_P_2,
- VEX_W_0F3833_P_2,
- VEX_W_0F3834_P_2,
- VEX_W_0F3835_P_2,
VEX_W_0F3836_P_2,
- VEX_W_0F3837_P_2,
- VEX_W_0F3838_P_2,
- VEX_W_0F3839_P_2,
- VEX_W_0F383A_P_2,
- VEX_W_0F383B_P_2,
- VEX_W_0F383C_P_2,
- VEX_W_0F383D_P_2,
- VEX_W_0F383E_P_2,
- VEX_W_0F383F_P_2,
- VEX_W_0F3840_P_2,
- VEX_W_0F3841_P_2,
VEX_W_0F3846_P_2,
+ VEX_W_0F3849_X86_64_P_0,
+ VEX_W_0F3849_X86_64_P_2,
+ VEX_W_0F3849_X86_64_P_3,
+ VEX_W_0F384B_X86_64_P_1,
+ VEX_W_0F384B_X86_64_P_2,
+ VEX_W_0F384B_X86_64_P_3,
VEX_W_0F3858_P_2,
VEX_W_0F3859_P_2,
- VEX_W_0F385A_P_2_M_0,
+ VEX_W_0F385A_P_2_M_0_L_0,
+ VEX_W_0F385C_X86_64_P_1,
+ VEX_W_0F385E_X86_64_P_0,
+ VEX_W_0F385E_X86_64_P_1,
+ VEX_W_0F385E_X86_64_P_2,
+ VEX_W_0F385E_X86_64_P_3,
VEX_W_0F3878_P_2,
VEX_W_0F3879_P_2,
VEX_W_0F38CF_P_2,
- VEX_W_0F38DB_P_2,
VEX_W_0F3A00_P_2,
VEX_W_0F3A01_P_2,
VEX_W_0F3A02_P_2,
VEX_W_0F3A04_P_2,
VEX_W_0F3A05_P_2,
- VEX_W_0F3A06_P_2,
- VEX_W_0F3A08_P_2,
- VEX_W_0F3A09_P_2,
- VEX_W_0F3A0A_P_2,
- VEX_W_0F3A0B_P_2,
- VEX_W_0F3A0C_P_2,
- VEX_W_0F3A0D_P_2,
- VEX_W_0F3A0E_P_2,
- VEX_W_0F3A0F_P_2,
- VEX_W_0F3A14_P_2,
- VEX_W_0F3A15_P_2,
- VEX_W_0F3A18_P_2,
- VEX_W_0F3A19_P_2,
- VEX_W_0F3A20_P_2,
- VEX_W_0F3A21_P_2,
+ VEX_W_0F3A06_P_2_L_0,
+ VEX_W_0F3A18_P_2_L_0,
+ VEX_W_0F3A19_P_2_L_0,
+ VEX_W_0F3A1D_P_2,
VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A31_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0,
VEX_W_0F3A33_P_2_LEN_0,
- VEX_W_0F3A38_P_2,
- VEX_W_0F3A39_P_2,
- VEX_W_0F3A40_P_2,
- VEX_W_0F3A41_P_2,
- VEX_W_0F3A42_P_2,
- VEX_W_0F3A46_P_2,
- VEX_W_0F3A48_P_2,
- VEX_W_0F3A49_P_2,
+ VEX_W_0F3A38_P_2_L_0,
+ VEX_W_0F3A39_P_2_L_0,
+ VEX_W_0F3A46_P_2_L_0,
VEX_W_0F3A4A_P_2,
VEX_W_0F3A4B_P_2,
VEX_W_0F3A4C_P_2,
- VEX_W_0F3A62_P_2,
- VEX_W_0F3A63_P_2,
VEX_W_0F3ACE_P_2,
VEX_W_0F3ACF_P_2,
- VEX_W_0F3ADF_P_2,
-
- EVEX_W_0F10_P_0,
- EVEX_W_0F10_P_1_M_0,
- EVEX_W_0F10_P_1_M_1,
- EVEX_W_0F10_P_2,
- EVEX_W_0F10_P_3_M_0,
- EVEX_W_0F10_P_3_M_1,
- EVEX_W_0F11_P_0,
- EVEX_W_0F11_P_1_M_0,
- EVEX_W_0F11_P_1_M_1,
- EVEX_W_0F11_P_2,
- EVEX_W_0F11_P_3_M_0,
- EVEX_W_0F11_P_3_M_1,
- EVEX_W_0F12_P_0_M_0,
+
+ VEX_W_0FXOP_08_85_L_0,
+ VEX_W_0FXOP_08_86_L_0,
+ VEX_W_0FXOP_08_87_L_0,
+ VEX_W_0FXOP_08_8E_L_0,
+ VEX_W_0FXOP_08_8F_L_0,
+ VEX_W_0FXOP_08_95_L_0,
+ VEX_W_0FXOP_08_96_L_0,
+ VEX_W_0FXOP_08_97_L_0,
+ VEX_W_0FXOP_08_9E_L_0,
+ VEX_W_0FXOP_08_9F_L_0,
+ VEX_W_0FXOP_08_A6_L_0,
+ VEX_W_0FXOP_08_B6_L_0,
+ VEX_W_0FXOP_08_C0_L_0,
+ VEX_W_0FXOP_08_C1_L_0,
+ VEX_W_0FXOP_08_C2_L_0,
+ VEX_W_0FXOP_08_C3_L_0,
+ VEX_W_0FXOP_08_CC_L_0,
+ VEX_W_0FXOP_08_CD_L_0,
+ VEX_W_0FXOP_08_CE_L_0,
+ VEX_W_0FXOP_08_CF_L_0,
+ VEX_W_0FXOP_08_EC_L_0,
+ VEX_W_0FXOP_08_ED_L_0,
+ VEX_W_0FXOP_08_EE_L_0,
+ VEX_W_0FXOP_08_EF_L_0,
+
+ VEX_W_0FXOP_09_80,
+ VEX_W_0FXOP_09_81,
+ VEX_W_0FXOP_09_82,
+ VEX_W_0FXOP_09_83,
+ VEX_W_0FXOP_09_C1_L_0,
+ VEX_W_0FXOP_09_C2_L_0,
+ VEX_W_0FXOP_09_C3_L_0,
+ VEX_W_0FXOP_09_C6_L_0,
+ VEX_W_0FXOP_09_C7_L_0,
+ VEX_W_0FXOP_09_CB_L_0,
+ VEX_W_0FXOP_09_D1_L_0,
+ VEX_W_0FXOP_09_D2_L_0,
+ VEX_W_0FXOP_09_D3_L_0,
+ VEX_W_0FXOP_09_D6_L_0,
+ VEX_W_0FXOP_09_D7_L_0,
+ VEX_W_0FXOP_09_DB_L_0,
+ VEX_W_0FXOP_09_E1_L_0,
+ VEX_W_0FXOP_09_E2_L_0,
+ VEX_W_0FXOP_09_E3_L_0,
+
+ EVEX_W_0F10_P_1,
+ EVEX_W_0F10_P_3,
+ EVEX_W_0F11_P_1,
+ EVEX_W_0F11_P_3,
EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_2,
EVEX_W_0F12_P_3,
- EVEX_W_0F13_P_0,
- EVEX_W_0F13_P_2,
- EVEX_W_0F14_P_0,
- EVEX_W_0F14_P_2,
- EVEX_W_0F15_P_0,
- EVEX_W_0F15_P_2,
- EVEX_W_0F16_P_0_M_0,
EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1,
- EVEX_W_0F16_P_2,
- EVEX_W_0F17_P_0,
- EVEX_W_0F17_P_2,
- EVEX_W_0F28_P_0,
- EVEX_W_0F28_P_2,
- EVEX_W_0F29_P_0,
- EVEX_W_0F29_P_2,
- EVEX_W_0F2A_P_1,
EVEX_W_0F2A_P_3,
- EVEX_W_0F2B_P_0,
- EVEX_W_0F2B_P_2,
- EVEX_W_0F2E_P_0,
- EVEX_W_0F2E_P_2,
- EVEX_W_0F2F_P_0,
- EVEX_W_0F2F_P_2,
- EVEX_W_0F51_P_0,
EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_2,
EVEX_W_0F51_P_3,
- EVEX_W_0F54_P_0,
- EVEX_W_0F54_P_2,
- EVEX_W_0F55_P_0,
- EVEX_W_0F55_P_2,
- EVEX_W_0F56_P_0,
- EVEX_W_0F56_P_2,
- EVEX_W_0F57_P_0,
- EVEX_W_0F57_P_2,
- EVEX_W_0F58_P_0,
EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_2,
EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_0,
EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_2,
EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0,
EVEX_W_0F5A_P_1,
EVEX_W_0F5B_P_0,
EVEX_W_0F5B_P_1,
EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_2,
EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_2,
EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_2,
EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_2,
EVEX_W_0F5F_P_3,
- EVEX_W_0F62_P_2,
+ EVEX_W_0F62,
EVEX_W_0F66_P_2,
- EVEX_W_0F6A_P_2,
- EVEX_W_0F6B_P_2,
- EVEX_W_0F6C_P_2,
- EVEX_W_0F6D_P_2,
- EVEX_W_0F6E_P_2,
+ EVEX_W_0F6A,
+ EVEX_W_0F6B,
+ EVEX_W_0F6C,
+ EVEX_W_0F6D,
EVEX_W_0F6F_P_1,
EVEX_W_0F6F_P_2,
EVEX_W_0F6F_P_3,
EVEX_W_0F7A_P_1,
EVEX_W_0F7A_P_2,
EVEX_W_0F7A_P_3,
- EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_2,
EVEX_W_0F7B_P_3,
EVEX_W_0F7E_P_1,
- EVEX_W_0F7E_P_2,
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_0,
EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3,
- EVEX_W_0FC6_P_0,
- EVEX_W_0FC6_P_2,
- EVEX_W_0FD2_P_2,
- EVEX_W_0FD3_P_2,
- EVEX_W_0FD4_P_2,
+ EVEX_W_0FD2,
+ EVEX_W_0FD3,
+ EVEX_W_0FD4,
EVEX_W_0FD6_P_2,
EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2,
EVEX_W_0FE6_P_3,
EVEX_W_0FE7_P_2,
- EVEX_W_0FF2_P_2,
- EVEX_W_0FF3_P_2,
- EVEX_W_0FF4_P_2,
- EVEX_W_0FFA_P_2,
- EVEX_W_0FFB_P_2,
- EVEX_W_0FFE_P_2,
- EVEX_W_0F380C_P_2,
+ EVEX_W_0FF2,
+ EVEX_W_0FF3,
+ EVEX_W_0FF4,
+ EVEX_W_0FFA,
+ EVEX_W_0FFB,
+ EVEX_W_0FFE,
EVEX_W_0F380D_P_2,
EVEX_W_0F3810_P_1,
EVEX_W_0F3810_P_2,
EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
- EVEX_W_0F3818_P_2,
EVEX_W_0F3819_P_2,
EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2,
EVEX_W_0F3824_P_1,
EVEX_W_0F3825_P_1,
EVEX_W_0F3825_P_2,
- EVEX_W_0F3826_P_1,
- EVEX_W_0F3826_P_2,
- EVEX_W_0F3828_P_1,
EVEX_W_0F3828_P_2,
- EVEX_W_0F3829_P_1,
EVEX_W_0F3829_P_2,
EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2,
- EVEX_W_0F382B_P_2,
+ EVEX_W_0F382B,
EVEX_W_0F3830_P_1,
EVEX_W_0F3831_P_1,
EVEX_W_0F3832_P_1,
EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2,
EVEX_W_0F3837_P_2,
- EVEX_W_0F3838_P_1,
- EVEX_W_0F3839_P_1,
EVEX_W_0F383A_P_1,
- EVEX_W_0F3840_P_2,
- EVEX_W_0F3854_P_2,
- EVEX_W_0F3855_P_2,
- EVEX_W_0F3858_P_2,
+ EVEX_W_0F3852_P_1,
EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2,
EVEX_W_0F385B_P_2,
- EVEX_W_0F3862_P_2,
- EVEX_W_0F3863_P_2,
- EVEX_W_0F3866_P_2,
EVEX_W_0F3870_P_2,
- EVEX_W_0F3871_P_2,
+ EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
- EVEX_W_0F3873_P_2,
- EVEX_W_0F3875_P_2,
- EVEX_W_0F3878_P_2,
- EVEX_W_0F3879_P_2,
+ EVEX_W_0F3872_P_3,
EVEX_W_0F387A_P_2,
EVEX_W_0F387B_P_2,
- EVEX_W_0F387D_P_2,
EVEX_W_0F3883_P_2,
- EVEX_W_0F388D_P_2,
EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2,
EVEX_W_0F38A1_P_2,
EVEX_W_0F3A00_P_2,
EVEX_W_0F3A01_P_2,
- EVEX_W_0F3A04_P_2,
EVEX_W_0F3A05_P_2,
EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2,
EVEX_W_0F3A0A_P_2,
EVEX_W_0F3A0B_P_2,
- EVEX_W_0F3A16_P_2,
EVEX_W_0F3A18_P_2,
EVEX_W_0F3A19_P_2,
EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2,
- EVEX_W_0F3A1D_P_2,
EVEX_W_0F3A21_P_2,
- EVEX_W_0F3A22_P_2,
EVEX_W_0F3A23_P_2,
EVEX_W_0F3A38_P_2,
EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2,
EVEX_W_0F3A3B_P_2,
- EVEX_W_0F3A3E_P_2,
- EVEX_W_0F3A3F_P_2,
EVEX_W_0F3A42_P_2,
EVEX_W_0F3A43_P_2,
- EVEX_W_0F3A50_P_2,
- EVEX_W_0F3A51_P_2,
- EVEX_W_0F3A56_P_2,
- EVEX_W_0F3A57_P_2,
- EVEX_W_0F3A66_P_2,
- EVEX_W_0F3A67_P_2,
EVEX_W_0F3A70_P_2,
- EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2,
- EVEX_W_0F3A73_P_2,
- EVEX_W_0F3ACE_P_2,
- EVEX_W_0F3ACF_P_2
};
typedef void (*op_rtn) (int bytemode, int sizeflag);
'F' => print 'w' or 'l' depending on address size prefix (loop insns)
'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
'H' => print ",pt" or ",pn" branch hint
- 'I' => honor following macro letter even in Intel mode (implemented only
- for some of the macro letters)
- 'J' => print 'l'
+ 'I' unused.
+ 'J' unused.
'K' => print 'd' or 'q' if rex prefix is present.
'L' => print 'l' if suffix_always is true
'M' => print 'r' if intel_mnemonic is false.
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
- '^' => print 'w' or 'l' depending on operand size prefix or
- suffix_always is true (lcall/ljmp).
+ '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
+ prefix or suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
- "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
- or suffix_always is true
+ "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
+ being false, or no operand at all in 64bit mode, or if suffix_always
+ is true.
"LB" => print "abs" in 64bit mode and behave as 'B' otherwise
"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
"LV" => print "abs" for 64bit operand and behave as 'S' otherwise
- "LW" => print 'd', 'q' depending on the VEX.W bit
+ "DQ" => print 'd' or 'q' depending on the VEX.W bit
+ "BW" => print 'b' or 'w' depending on the EVEX.W bit
"LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
an operand size prefix, or suffix_always is true. print
'q' if rex prefix is present.
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
- { X86_64_TABLE (X86_64_0D) },
+ { X86_64_TABLE (X86_64_0E) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- { "retT", { Iw, BND }, 0 },
- { "retT", { BND }, 0 },
+ { X86_64_TABLE (X86_64_C2) },
+ { X86_64_TABLE (X86_64_C3) },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
/* c8 */
{ "enterT", { Iw, Ib }, 0 },
{ "leaveT", { XX }, 0 },
- { "Jret{|f}P", { Iw }, 0 },
- { "Jret{|f}P", { XX }, 0 },
+ { "{l|}ret{|f}P", { Iw }, 0 },
+ { "{l|}ret{|f}P", { XX }, 0 },
{ "int3", { XX }, 0 },
{ "int", { Ib }, 0 },
{ X86_64_TABLE (X86_64_CE) },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
- { "sysret%LP", { XX }, 0 },
+ { "sysret%LQ", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
{ PREFIX_TABLE (PREFIX_0F09) },
{ "rdtsc", { XX }, 0 },
{ "rdmsr", { XX }, 0 },
{ "rdpmc", { XX }, 0 },
- { "sysenter", { XX }, 0 },
- { "sysexit", { XX }, 0 },
+ { "sysenter", { SEP }, 0 },
+ { "sysexit", { SEP }, 0 },
{ Bad_Opcode },
{ "getsec", { XX }, 0 },
/* 38 */
{ "cmovleS", { Gv, Ev }, 0 },
{ "cmovgS", { Gv, Ev }, 0 },
/* 50 */
- { MOD_TABLE (MOD_0F51) },
+ { MOD_TABLE (MOD_0F50) },
{ PREFIX_TABLE (PREFIX_0F51) },
{ PREFIX_TABLE (PREFIX_0F52) },
{ PREFIX_TABLE (PREFIX_0F53) },
}
vex;
static unsigned char need_vex;
-static unsigned char need_vex_reg;
-static unsigned char vex_w_done;
struct op
{
"%zmm28", "%zmm29", "%zmm30", "%zmm31"
};
+static const char **names_tmm;
+static const char *intel_names_tmm[] = {
+ "tmm0", "tmm1", "tmm2", "tmm3",
+ "tmm4", "tmm5", "tmm6", "tmm7"
+};
+static const char *att_names_tmm[] = {
+ "%tmm0", "%tmm1", "%tmm2", "%tmm3",
+ "%tmm4", "%tmm5", "%tmm6", "%tmm7"
+};
+
static const char **names_mask;
static const char *intel_names_mask[] = {
"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
- /* REG_0F1C_MOD_0 */
+ /* REG_0F1C_P_0_MOD_0 */
{
{ "cldemote", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
},
- /* REG_0F1E_MOD_3 */
+ /* REG_0F1E_P_1_MOD_3 */
{
{ "nopQ", { Ev }, 0 },
{ "rdsspK", { Rdq }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
+ { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
},
/* REG_0F71 */
{
{ MOD_TABLE (MOD_VEX_0FAE_REG_2) },
{ MOD_TABLE (MOD_VEX_0FAE_REG_3) },
},
+ /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
+ {
+ { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
+ },
/* REG_VEX_0F38F3 */
{
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
{ PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
},
- /* REG_XOP_LWPCB */
- {
- { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
- { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
- },
- /* REG_XOP_LWP */
- {
- { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
- { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
- },
- /* REG_XOP_TBM_01 */
+ /* REG_0FXOP_09_01_L_0 */
{
{ Bad_Opcode },
- { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcfill", { VexGdq, Edq }, 0 },
+ { "blsfill", { VexGdq, Edq }, 0 },
+ { "blcs", { VexGdq, Edq }, 0 },
+ { "tzmsk", { VexGdq, Edq }, 0 },
+ { "blcic", { VexGdq, Edq }, 0 },
+ { "blsic", { VexGdq, Edq }, 0 },
+ { "t1mskc", { VexGdq, Edq }, 0 },
},
- /* REG_XOP_TBM_02 */
+ /* REG_0FXOP_09_02_L_0 */
{
{ Bad_Opcode },
- { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcmsk", { VexGdq, Edq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blci", { VexGdq, Edq }, 0 },
},
-#define NEED_REG_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_REG_TABLE
+ /* REG_0FXOP_09_12_M_1_L_0 */
+ {
+ { "llwpcb", { Edq }, 0 },
+ { "slwpcb", { Edq }, 0 },
+ },
+ /* REG_0FXOP_0A_12_L_0 */
+ {
+ { "lwpins", { VexGdq, Ed, Id }, 0 },
+ { "lwpval", { VexGdq, Ed, Id }, 0 },
+ },
+
+#include "i386-dis-evex-reg.h"
};
static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
- /* PREFIX_MOD_0_0F01_REG_5 */
+ /* PREFIX_0F01_REG_3_RM_1 */
{
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmgexit", { Skip_MODRM }, 0 },
{ Bad_Opcode },
- { "rstorssp", { Mq }, PREFIX_OPCODE },
+ { "vmgexit", { Skip_MODRM }, 0 },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
+ /* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
+ { "rstorssp", { Mq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
+ {
+ { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
+ /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
{
{ Bad_Opcode },
{ "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
},
+ /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
+ {
+ { "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mcommit", { Skip_MODRM }, 0 },
+ },
+
+ /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
+ {
+ { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 },
+ },
+
/* PREFIX_0F09 */
{
{ "wbinvd", { XX }, 0 },
{
{ MOD_TABLE (MOD_0F12_PREFIX_0) },
{ "movsldup", { XM, EXx }, PREFIX_OPCODE },
- { "movlpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F12_PREFIX_2) },
{ "movddup", { XM, EXq }, PREFIX_OPCODE },
},
{
{ MOD_TABLE (MOD_0F16_PREFIX_0) },
{ "movshdup", { XM, EXx }, PREFIX_OPCODE },
- { "movhpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F16_PREFIX_2) },
},
/* PREFIX_0F1A */
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
+ { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
{ "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2sd%LQ", { XM, Ev }, 0 },
+ { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
},
/* PREFIX_0F2B */
/* PREFIX_0F2C */
{
{ "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
{ "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2D */
{
{ "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
{ "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2E */
{ "movdqa", { EXxS, XM }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_0 */
+ /* PREFIX_0FAE_REG_0_MOD_3 */
{
{ Bad_Opcode },
{ "rdfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_1 */
+ /* PREFIX_0FAE_REG_1_MOD_3 */
{
{ Bad_Opcode },
{ "rdgsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_2 */
+ /* PREFIX_0FAE_REG_2_MOD_3 */
{
{ Bad_Opcode },
{ "wrfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_3 */
+ /* PREFIX_0FAE_REG_3_MOD_3 */
{
{ Bad_Opcode },
{ "wrgsbase", { Ev }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_0 */
{
{ "xsave", { FXSAVE }, 0 },
- { "ptwrite%LQ", { Edq }, 0 },
+ { "ptwrite{%LQ|}", { Edq }, 0 },
},
- /* PREFIX_MOD_3_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_3 */
{
{ Bad_Opcode },
- { "ptwrite%LQ", { Edq }, 0 },
+ { "ptwrite{%LQ|}", { Edq }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_0 */
{
{ "xrstor", { FXSAVE }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_3 */
{
{ "lfence", { Skip_MODRM }, 0 },
{ "incsspK", { Rdq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_0 */
{
{ "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
{ "clrssbsy", { Mq }, PREFIX_OPCODE },
{ "clwb", { Mb }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_1_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_3 */
{
- { RM_TABLE (RM_0FAE_REG_6) },
+ { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
{ "umonitor", { Eva }, PREFIX_OPCODE },
{ "tpause", { Edq }, PREFIX_OPCODE },
{ "umwait", { Edq }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_7 */
+ /* PREFIX_0FAE_REG_7_MOD_0 */
{
{ "clflush", { Mb }, 0 },
{ Bad_Opcode },
{ "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC3 */
+ /* PREFIX_0FC3_MOD_0 */
{
- { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
+ { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_0 */
{
{ "vmptrld",{ Mq }, 0 },
{ "vmxon", { Mq }, 0 },
{ "vmclear",{ Mq }, 0 },
},
- /* PREFIX_MOD_3_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_3 */
{
{ "rdrand", { Ev }, 0 },
{ Bad_Opcode },
{ "rdrand", { Ev }, 0 }
},
- /* PREFIX_MOD_3_0FC7_REG_7 */
+ /* PREFIX_0FC7_REG_7_MOD_3 */
{
{ "rdseed", { Ev }, 0 },
{ "rdpid", { Em }, 0 },
/* PREFIX_0F38F0 */
{
- { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
+ { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
- { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
+ { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
+ { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
},
/* PREFIX_0F38F1 */
{
- { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
+ { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
- { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
+ { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
+ { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
},
/* PREFIX_0F38F5 */
/* PREFIX_0F38F8 */
{
{ Bad_Opcode },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
{ MOD_TABLE (MOD_0F38F8_PREFIX_2) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
},
/* PREFIX_0F38F9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
+ { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
+ { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A62 */
/* PREFIX_VEX_0F10 */
{
- { VEX_W_TABLE (VEX_W_0F10_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
- { VEX_W_TABLE (VEX_W_0F10_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
+ { "vmovups", { XM, EXx }, 0 },
+ { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
+ { "vmovupd", { XM, EXx }, 0 },
+ { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F11 */
{
- { VEX_W_TABLE (VEX_W_0F11_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
- { VEX_W_TABLE (VEX_W_0F11_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
+ { "vmovups", { EXxS, XM }, 0 },
+ { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
+ { "vmovupd", { EXxS, XM }, 0 },
+ { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
},
/* PREFIX_VEX_0F12 */
{
{ MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
- { VEX_W_TABLE (VEX_W_0F12_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
- { VEX_W_TABLE (VEX_W_0F12_P_3) },
+ { "vmovsldup", { XM, EXx }, 0 },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
+ { "vmovddup", { XM, EXymmq }, 0 },
},
/* PREFIX_VEX_0F16 */
{
{ MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
- { VEX_W_TABLE (VEX_W_0F16_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
+ { "vmovshdup", { XM, EXx }, 0 },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
},
/* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
+ { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
+ { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
},
/* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
+ { "vcvttss2si", { Gdq, EXxmm_md }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
+ { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
+ { "vcvtss2si", { Gdq, EXxmm_md }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
+ { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F2E */
{
- { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
+ { "vucomiss", { XMScalar, EXxmm_md }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
+ { "vucomisd", { XMScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F2F */
{
- { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
+ { "vcomiss", { XMScalar, EXxmm_md }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
+ { "vcomisd", { XMScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F41 */
/* PREFIX_VEX_0F51 */
{
- { VEX_W_TABLE (VEX_W_0F51_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
- { VEX_W_TABLE (VEX_W_0F51_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
+ { "vsqrtps", { XM, EXx }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsqrtpd", { XM, EXx }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F52 */
{
- { VEX_W_TABLE (VEX_W_0F52_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
+ { "vrsqrtps", { XM, EXx }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
},
/* PREFIX_VEX_0F53 */
{
- { VEX_W_TABLE (VEX_W_0F53_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
+ { "vrcpps", { XM, EXx }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
},
/* PREFIX_VEX_0F58 */
{
- { VEX_W_TABLE (VEX_W_0F58_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
- { VEX_W_TABLE (VEX_W_0F58_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
+ { "vaddps", { XM, Vex, EXx }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vaddpd", { XM, Vex, EXx }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F59 */
{
- { VEX_W_TABLE (VEX_W_0F59_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
- { VEX_W_TABLE (VEX_W_0F59_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
+ { "vmulps", { XM, Vex, EXx }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmulpd", { XM, Vex, EXx }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5A */
{
- { VEX_W_TABLE (VEX_W_0F5A_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
- { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
+ { "vcvtps2pd", { XM, EXxmmq }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5B */
{
- { VEX_W_TABLE (VEX_W_0F5B_P_0) },
- { VEX_W_TABLE (VEX_W_0F5B_P_1) },
- { VEX_W_TABLE (VEX_W_0F5B_P_2) },
+ { "vcvtdq2ps", { XM, EXx }, 0 },
+ { "vcvttps2dq", { XM, EXx }, 0 },
+ { "vcvtps2dq", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F5C */
{
- { VEX_W_TABLE (VEX_W_0F5C_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
- { VEX_W_TABLE (VEX_W_0F5C_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
+ { "vsubps", { XM, Vex, EXx }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsubpd", { XM, Vex, EXx }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5D */
{
- { VEX_W_TABLE (VEX_W_0F5D_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
- { VEX_W_TABLE (VEX_W_0F5D_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
+ { "vminps", { XM, Vex, EXx }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vminpd", { XM, Vex, EXx }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5E */
{
- { VEX_W_TABLE (VEX_W_0F5E_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
- { VEX_W_TABLE (VEX_W_0F5E_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
+ { "vdivps", { XM, Vex, EXx }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vdivpd", { XM, Vex, EXx }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5F */
{
- { VEX_W_TABLE (VEX_W_0F5F_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
- { VEX_W_TABLE (VEX_W_0F5F_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
+ { "vmaxps", { XM, Vex, EXx }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmaxpd", { XM, Vex, EXx }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F60_P_2) },
+ { "vpunpcklbw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F61_P_2) },
+ { "vpunpcklwd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F62 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F62_P_2) },
+ { "vpunpckldq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F63 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F63_P_2) },
+ { "vpacksswb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F64 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F64_P_2) },
+ { "vpcmpgtb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F65 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F65_P_2) },
+ { "vpcmpgtw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F66 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F66_P_2) },
+ { "vpcmpgtd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F67 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F67_P_2) },
+ { "vpackuswb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F68 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F68_P_2) },
+ { "vpunpckhbw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F69_P_2) },
+ { "vpunpckhwd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6A_P_2) },
+ { "vpunpckhdq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6B_P_2) },
+ { "vpackssdw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6C_P_2) },
+ { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6D_P_2) },
+ { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6E */
/* PREFIX_VEX_0F6F */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6F_P_1) },
- { VEX_W_TABLE (VEX_W_0F6F_P_2) },
+ { "vmovdqu", { XM, EXx }, 0 },
+ { "vmovdqa", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F70 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F70_P_1) },
- { VEX_W_TABLE (VEX_W_0F70_P_2) },
- { VEX_W_TABLE (VEX_W_0F70_P_3) },
+ { "vpshufhw", { XM, EXx, Ib }, 0 },
+ { "vpshufd", { XM, EXx, Ib }, 0 },
+ { "vpshuflw", { XM, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F71_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
+ { "vpsrlw", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F71_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
+ { "vpsraw", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F71_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
+ { "vpsllw", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F72_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
+ { "vpsrld", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F72_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
+ { "vpsrad", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F72_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
+ { "vpslld", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
+ { "vpsrlq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
+ { "vpsrldq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
+ { "vpsllq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
+ { "vpslldq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F74 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F74_P_2) },
+ { "vpcmpeqb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F75 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F75_P_2) },
+ { "vpcmpeqw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F76 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F76_P_2) },
+ { "vpcmpeqd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F77 */
{
- { VEX_W_TABLE (VEX_W_0F77_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
},
/* PREFIX_VEX_0F7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7C_P_2) },
- { VEX_W_TABLE (VEX_W_0F7C_P_3) },
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
+ { "vhaddps", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F7D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7D_P_2) },
- { VEX_W_TABLE (VEX_W_0F7D_P_3) },
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
+ { "vhsubps", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F7E */
/* PREFIX_VEX_0F7F */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7F_P_1) },
- { VEX_W_TABLE (VEX_W_0F7F_P_2) },
+ { "vmovdqu", { EXxS, XM }, 0 },
+ { "vmovdqa", { EXxS, XM }, 0 },
},
/* PREFIX_VEX_0F90 */
/* PREFIX_VEX_0FC2 */
{
- { VEX_W_TABLE (VEX_W_0FC2_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
+ { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
+ { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
},
/* PREFIX_VEX_0FC4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD0_P_2) },
- { VEX_W_TABLE (VEX_W_0FD0_P_3) },
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD1_P_2) },
+ { "vpsrlw", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FD2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD2_P_2) },
+ { "vpsrld", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FD3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD3_P_2) },
+ { "vpsrlq", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FD4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD4_P_2) },
+ { "vpaddq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD5_P_2) },
+ { "vpmullw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD8_P_2) },
+ { "vpsubusb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD9_P_2) },
+ { "vpsubusw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDA_P_2) },
+ { "vpminub", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDB_P_2) },
+ { "vpand", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDC_P_2) },
+ { "vpaddusb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDD_P_2) },
+ { "vpaddusw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDE_P_2) },
+ { "vpmaxub", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDF_P_2) },
+ { "vpandn", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE0_P_2) },
+ { "vpavgb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE1_P_2) },
+ { "vpsraw", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FE2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE2_P_2) },
+ { "vpsrad", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FE3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE3_P_2) },
+ { "vpavgw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE4_P_2) },
+ { "vpmulhuw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE5_P_2) },
+ { "vpmulhw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE6 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE6_P_1) },
- { VEX_W_TABLE (VEX_W_0FE6_P_2) },
- { VEX_W_TABLE (VEX_W_0FE6_P_3) },
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
},
/* PREFIX_VEX_0FE7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE8_P_2) },
+ { "vpsubsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE9_P_2) },
+ { "vpsubsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEA_P_2) },
+ { "vpminsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEB_P_2) },
+ { "vpor", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEC_P_2) },
+ { "vpaddsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FED */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FED_P_2) },
+ { "vpaddsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEE_P_2) },
+ { "vpmaxsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEF_P_2) },
+ { "vpxor", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF1_P_2) },
+ { "vpsllw", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FF2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF2_P_2) },
+ { "vpslld", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FF3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF3_P_2) },
+ { "vpsllq", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FF4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF4_P_2) },
+ { "vpmuludq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF5_P_2) },
+ { "vpmaddwd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF6_P_2) },
+ { "vpsadbw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF8_P_2) },
+ { "vpsubb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF9_P_2) },
+ { "vpsubw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFA_P_2) },
+ { "vpsubd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFB_P_2) },
+ { "vpsubq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFC_P_2) },
+ { "vpaddb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFD_P_2) },
+ { "vpaddw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFE_P_2) },
+ { "vpaddd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3800 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3800_P_2) },
+ { "vpshufb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3801 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3801_P_2) },
+ { "vphaddw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3802 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3802_P_2) },
+ { "vphaddd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3803 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3803_P_2) },
+ { "vphaddsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3804 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3804_P_2) },
+ { "vpmaddubsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3805 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3805_P_2) },
+ { "vphsubw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3806 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3806_P_2) },
+ { "vphsubd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3807 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3807_P_2) },
+ { "vphsubsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3808 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3808_P_2) },
+ { "vpsignb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3809 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3809_P_2) },
+ { "vpsignw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F380A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380A_P_2) },
+ { "vpsignd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F380B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380B_P_2) },
+ { "vpmulhrsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F380C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtph2ps", { XM, EXxmmq }, 0 },
+ { VEX_W_TABLE (VEX_W_0F3813_P_2) },
},
/* PREFIX_VEX_0F3816 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3817_P_2) },
+ { "vptest", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F3818 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381C_P_2) },
+ { "vpabsb", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F381D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381D_P_2) },
+ { "vpabsw", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F381E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381E_P_2) },
+ { "vpabsd", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F3820 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3820_P_2) },
+ { "vpmovsxbw", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3821 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3821_P_2) },
+ { "vpmovsxbd", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3822 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3822_P_2) },
+ { "vpmovsxbq", { XM, EXxmmdw }, 0 },
},
/* PREFIX_VEX_0F3823 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3823_P_2) },
+ { "vpmovsxwd", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3824 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3824_P_2) },
+ { "vpmovsxwq", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3825 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3825_P_2) },
+ { "vpmovsxdq", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3828 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3828_P_2) },
+ { "vpmuldq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3829 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3829_P_2) },
+ { "vpcmpeqq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F382A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F382B_P_2) },
+ { "vpackusdw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F382C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3830_P_2) },
+ { "vpmovzxbw", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3831 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3831_P_2) },
+ { "vpmovzxbd", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3832 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3832_P_2) },
+ { "vpmovzxbq", { XM, EXxmmdw }, 0 },
},
/* PREFIX_VEX_0F3833 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3833_P_2) },
+ { "vpmovzxwd", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3834 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3834_P_2) },
+ { "vpmovzxwq", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3835 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+ { "vpmovzxdq", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3836 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3837_P_2) },
+ { "vpcmpgtq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3838 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3838_P_2) },
+ { "vpminsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3839 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3839_P_2) },
+ { "vpminsd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383A_P_2) },
+ { "vpminuw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383B_P_2) },
+ { "vpminud", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383C_P_2) },
+ { "vpmaxsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383D_P_2) },
+ { "vpmaxsd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383E_P_2) },
+ { "vpmaxuw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383F_P_2) },
+ { "vpmaxud", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3840 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3840_P_2) },
+ { "vpmulld", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3841 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
+ { "vpsrlv%DQ", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3846 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsllv%LW", { XM, Vex, EXx }, 0 },
+ { "vpsllv%DQ", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3849_X86_64 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
+ },
+
+ /* PREFIX_VEX_0F384B_X86_64 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
+ { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
},
/* PREFIX_VEX_0F3858 */
{ MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
},
+ /* PREFIX_VEX_0F385C_X86_64 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_VEX_0F385E_X86_64 */
+ {
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
+ },
+
/* PREFIX_VEX_0F3878 */
{
{ Bad_Opcode },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
+ { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, 0 },
},
/* PREFIX_VEX_0F3891 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
+ { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
},
/* PREFIX_VEX_0F3892 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F3897 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F3898 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F3899 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38A6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38A8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38A9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38CF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
+ { "vroundps", { XM, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A09 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
+ { "vroundpd", { XM, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
+ { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
+ { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
+ { "vblendps", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
+ { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
+ { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
+ { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A14 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
},
/* PREFIX_VEX_0F3A20 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
+ { "vdpps", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A41 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
+ { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A44 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
+ { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A49 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
+ { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A4A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
+ { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A6B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
+ { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
+ { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A6F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
+ { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A78 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A79 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A7A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
+ { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A7B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
+ { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A7E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
+ { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A7F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
+ { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3ACE */
{ VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
},
-#define NEED_PREFIX_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_PREFIX_TABLE
+#include "i386-dis-evex-prefix.h"
};
static const struct dis386 x86_64_table[][2] = {
{ "popP", { es }, 0 },
},
- /* X86_64_0D */
+ /* X86_64_0E */
{
{ "pushP", { cs }, 0 },
},
/* X86_64_63 */
{
{ "arpl", { Ew, Gw }, 0 },
- { "movs{lq|xd}", { Gv, Ed }, 0 },
+ { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
/* X86_64_6D */
/* X86_64_9A */
{
- { "Jcall{T|}", { Ap }, 0 },
+ { "{l|}call{T|}", { Ap }, 0 },
+ },
+
+ /* X86_64_C2 */
+ {
+ { "retP", { Iw, BND }, 0 },
+ { "ret@", { Iw, BND }, 0 },
+ },
+
+ /* X86_64_C3 */
+ {
+ { "retP", { BND }, 0 },
+ { "ret@", { BND }, 0 },
},
/* X86_64_C4 */
/* X86_64_EA */
{
- { "Jjmp{T|}", { Ap }, 0 },
+ { "{l|}jmp{T|}", { Ap }, 0 },
},
/* X86_64_0F01_REG_0 */
{
- { "sgdt{Q|IQ}", { M }, 0 },
+ { "sgdt{Q|Q}", { M }, 0 },
{ "sgdt", { M }, 0 },
},
/* X86_64_0F01_REG_1 */
{
- { "sidt{Q|IQ}", { M }, 0 },
+ { "sidt{Q|Q}", { M }, 0 },
{ "sidt", { M }, 0 },
},
{ "lidt{Q|Q}", { M }, 0 },
{ "lidt", { M }, 0 },
},
+
+ /* X86_64_VEX_0F3849 */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
+ },
+
+ /* X86_64_VEX_0F384B */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
+ },
+
+ /* X86_64_VEX_0F385C */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
+ },
+
+ /* X86_64_VEX_0F385E */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
+ },
};
static const struct dis386 three_byte_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{
/* 00 */
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_TBM_01) },
- { REG_TABLE (REG_XOP_TBM_02) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_LWPCB) },
+ { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
- { "vfrczss", { XM, EXd }, 0 },
- { "vfrczsd", { XM, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
- { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
/* 98 */
- { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
{ Bad_Opcode },
- { "vphaddbw", { XM, EXxmm }, 0 },
- { "vphaddbd", { XM, EXxmm }, 0 },
- { "vphaddbq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddwd", { XM, EXxmm }, 0 },
- { "vphaddwq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
/* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphadddq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* d0 */
{ Bad_Opcode },
- { "vphaddubw", { XM, EXxmm }, 0 },
- { "vphaddubd", { XM, EXxmm }, 0 },
- { "vphaddubq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphadduwd", { XM, EXxmm }, 0 },
- { "vphadduwq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddudq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* e0 */
{ Bad_Opcode },
- { "vphsubbw", { XM, EXxmm }, 0 },
- { "vphsubwd", { XM, EXxmm }, 0 },
- { "vphsubdq", { XM, EXxmm }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { "bextr", { Gv, Ev, Iq }, 0 },
+ { "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_LWP) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F11) },
{ PREFIX_TABLE (PREFIX_VEX_0F12) },
{ MOD_TABLE (MOD_VEX_0F13) },
- { VEX_W_TABLE (VEX_W_0F14) },
- { VEX_W_TABLE (VEX_W_0F15) },
+ { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F16) },
{ MOD_TABLE (MOD_VEX_0F17) },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
- { VEX_W_TABLE (VEX_W_0F28) },
- { VEX_W_TABLE (VEX_W_0F29) },
+ { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
+ { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F2A) },
{ MOD_TABLE (MOD_VEX_0F2B) },
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
{ PREFIX_TABLE (PREFIX_VEX_0F51) },
{ PREFIX_TABLE (PREFIX_VEX_0F52) },
{ PREFIX_TABLE (PREFIX_VEX_0F53) },
- { "vandpX", { XM, Vex, EXx }, 0 },
- { "vandnpX", { XM, Vex, EXx }, 0 },
- { "vorpX", { XM, Vex, EXx }, 0 },
- { "vxorpX", { XM, Vex, EXx }, 0 },
+ { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
/* 58 */
{ PREFIX_TABLE (PREFIX_VEX_0F58) },
{ PREFIX_TABLE (PREFIX_VEX_0F59) },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0FC4) },
{ PREFIX_TABLE (PREFIX_VEX_0FC5) },
- { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
+ { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
/* c8 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F3847) },
/* 48 */
{ Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F3849) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F384B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F3859) },
{ PREFIX_TABLE (PREFIX_VEX_0F385A) },
{ Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F385C) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F385E) },
{ Bad_Opcode },
/* 60 */
{ Bad_Opcode },
},
};
-#define NEED_OPCODE_TABLE
#include "i386-dis-evex.h"
-#undef NEED_OPCODE_TABLE
-static const struct dis386 vex_len_table[][2] = {
- /* VEX_LEN_0F10_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F10_P_1) },
- { VEX_W_TABLE (VEX_W_0F10_P_1) },
- },
-
- /* VEX_LEN_0F10_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F10_P_3) },
- { VEX_W_TABLE (VEX_W_0F10_P_3) },
- },
-
- /* VEX_LEN_0F11_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F11_P_1) },
- { VEX_W_TABLE (VEX_W_0F11_P_1) },
- },
-
- /* VEX_LEN_0F11_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F11_P_3) },
- { VEX_W_TABLE (VEX_W_0F11_P_3) },
- },
- /* VEX_LEN_0F12_P_0_M_0 */
+static const struct dis386 vex_len_table[][2] = {
+ /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
+ { "vmovlpX", { XM, Vex, EXq }, 0 },
},
/* VEX_LEN_0F12_P_0_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
- },
-
- /* VEX_LEN_0F12_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F12_P_2) },
+ { "vmovhlps", { XM, Vex, EXq }, 0 },
},
/* VEX_LEN_0F13_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F13_M_0) },
+ { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
},
- /* VEX_LEN_0F16_P_0_M_0 */
+ /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
+ { "vmovhpX", { XM, Vex, EXq }, 0 },
},
/* VEX_LEN_0F16_P_0_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
- },
-
- /* VEX_LEN_0F16_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F16_P_2) },
+ { "vmovlhps", { XM, Vex, EXq }, 0 },
},
/* VEX_LEN_0F17_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F17_M_0) },
- },
-
- /* VEX_LEN_0F2A_P_1 */
- {
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
- },
-
- /* VEX_LEN_0F2A_P_3 */
- {
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
- },
-
- /* VEX_LEN_0F2C_P_1 */
- {
- { "vcvttss2si", { Gv, EXdScalar }, 0 },
- { "vcvttss2si", { Gv, EXdScalar }, 0 },
- },
-
- /* VEX_LEN_0F2C_P_3 */
- {
- { "vcvttsd2si", { Gv, EXqScalar }, 0 },
- { "vcvttsd2si", { Gv, EXqScalar }, 0 },
- },
-
- /* VEX_LEN_0F2D_P_1 */
- {
- { "vcvtss2si", { Gv, EXdScalar }, 0 },
- { "vcvtss2si", { Gv, EXdScalar }, 0 },
- },
-
- /* VEX_LEN_0F2D_P_3 */
- {
- { "vcvtsd2si", { Gv, EXqScalar }, 0 },
- { "vcvtsd2si", { Gv, EXqScalar }, 0 },
- },
-
- /* VEX_LEN_0F2E_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F2E_P_0) },
- { VEX_W_TABLE (VEX_W_0F2E_P_0) },
- },
-
- /* VEX_LEN_0F2E_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F2E_P_2) },
- { VEX_W_TABLE (VEX_W_0F2E_P_2) },
- },
-
- /* VEX_LEN_0F2F_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F2F_P_0) },
- { VEX_W_TABLE (VEX_W_0F2F_P_0) },
- },
-
- /* VEX_LEN_0F2F_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F2F_P_2) },
- { VEX_W_TABLE (VEX_W_0F2F_P_2) },
+ { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
},
/* VEX_LEN_0F41_P_0 */
{ VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
},
- /* VEX_LEN_0F51_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F51_P_1) },
- { VEX_W_TABLE (VEX_W_0F51_P_1) },
- },
-
- /* VEX_LEN_0F51_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F51_P_3) },
- { VEX_W_TABLE (VEX_W_0F51_P_3) },
- },
-
- /* VEX_LEN_0F52_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F52_P_1) },
- { VEX_W_TABLE (VEX_W_0F52_P_1) },
- },
-
- /* VEX_LEN_0F53_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F53_P_1) },
- { VEX_W_TABLE (VEX_W_0F53_P_1) },
- },
-
- /* VEX_LEN_0F58_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F58_P_1) },
- { VEX_W_TABLE (VEX_W_0F58_P_1) },
- },
-
- /* VEX_LEN_0F58_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F58_P_3) },
- { VEX_W_TABLE (VEX_W_0F58_P_3) },
- },
-
- /* VEX_LEN_0F59_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F59_P_1) },
- { VEX_W_TABLE (VEX_W_0F59_P_1) },
- },
-
- /* VEX_LEN_0F59_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F59_P_3) },
- { VEX_W_TABLE (VEX_W_0F59_P_3) },
- },
-
- /* VEX_LEN_0F5A_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5A_P_1) },
- { VEX_W_TABLE (VEX_W_0F5A_P_1) },
- },
-
- /* VEX_LEN_0F5A_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5A_P_3) },
- { VEX_W_TABLE (VEX_W_0F5A_P_3) },
- },
-
- /* VEX_LEN_0F5C_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5C_P_1) },
- { VEX_W_TABLE (VEX_W_0F5C_P_1) },
- },
-
- /* VEX_LEN_0F5C_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5C_P_3) },
- { VEX_W_TABLE (VEX_W_0F5C_P_3) },
- },
-
- /* VEX_LEN_0F5D_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5D_P_1) },
- { VEX_W_TABLE (VEX_W_0F5D_P_1) },
- },
-
- /* VEX_LEN_0F5D_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5D_P_3) },
- { VEX_W_TABLE (VEX_W_0F5D_P_3) },
- },
-
- /* VEX_LEN_0F5E_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5E_P_1) },
- { VEX_W_TABLE (VEX_W_0F5E_P_1) },
- },
-
- /* VEX_LEN_0F5E_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5E_P_3) },
- { VEX_W_TABLE (VEX_W_0F5E_P_3) },
- },
-
- /* VEX_LEN_0F5F_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5F_P_1) },
- { VEX_W_TABLE (VEX_W_0F5F_P_1) },
- },
-
- /* VEX_LEN_0F5F_P_3 */
+ /* VEX_LEN_0F6E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F5F_P_3) },
- { VEX_W_TABLE (VEX_W_0F5F_P_3) },
+ { "vmovK", { XMScalar, Edq }, 0 },
},
- /* VEX_LEN_0F6E_P_2 */
+ /* VEX_LEN_0F77_P_1 */
{
- { "vmovK", { XMScalar, Edq }, 0 },
- { "vmovK", { XMScalar, Edq }, 0 },
+ { "vzeroupper", { XX }, 0 },
+ { "vzeroall", { XX }, 0 },
},
/* VEX_LEN_0F7E_P_1 */
{
- { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+ { "vmovq", { XMScalar, EXxmm_mq }, 0 },
},
/* VEX_LEN_0F7E_P_2 */
{
{ "vmovK", { Edq, XMScalar }, 0 },
- { "vmovK", { Edq, XMScalar }, 0 },
},
/* VEX_LEN_0F90_P_0 */
/* VEX_LEN_0F92_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
},
/* VEX_LEN_0F93_P_0 */
/* VEX_LEN_0F93_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
},
/* VEX_LEN_0F98_P_0 */
/* VEX_LEN_0FAE_R_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
+ { "vldmxcsr", { Md }, 0 },
},
/* VEX_LEN_0FAE_R_3_M_0 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
- },
-
- /* VEX_LEN_0FC2_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- },
-
- /* VEX_LEN_0FC2_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ { "vstmxcsr", { Md }, 0 },
},
/* VEX_LEN_0FC4_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FC4_P_2) },
+ { "vpinsrw", { XM, Vex, Edqw, Ib }, 0 },
},
/* VEX_LEN_0FC5_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FC5_P_2) },
+ { "vpextrw", { Gdq, XS, Ib }, 0 },
},
/* VEX_LEN_0FD6_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ { "vmovq", { EXqS, XMScalar }, 0 },
},
/* VEX_LEN_0FF7_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF7_P_2) },
+ { "vmaskmovdqu", { XM, XS }, 0 },
},
/* VEX_LEN_0F3816_P_2 */
/* VEX_LEN_0F381A_P_2_M_0 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
+ { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0_L_0) },
},
/* VEX_LEN_0F3836_P_2 */
/* VEX_LEN_0F3841_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3841_P_2) },
+ { "vphminposuw", { XM, EXx }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
+ {
+ { "ldtilecfg", { M }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
+ {
+ { "tilerelease", { Skip_MODRM }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
+ {
+ { "sttilecfg", { M }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
+ {
+ { "tilezero", { TMM, Skip_MODRM }, 0 },
+ },
+
+ /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
+ {
+ { "tilestored", { MVexSIBMEM, TMM }, 0 },
+ },
+ /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
+ {
+ { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
+ },
+
+ /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
+ {
+ { "tileloadd", { TMM, MVexSIBMEM }, 0 },
},
/* VEX_LEN_0F385A_P_2_M_0 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
+ { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0_L_0) },
+ },
+
+ /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
+ {
+ { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
+ {
+ { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
+ {
+ { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
+ {
+ { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
+ {
+ { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
},
/* VEX_LEN_0F38DB_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
+ { "vaesimc", { XM, EXx }, 0 },
},
/* VEX_LEN_0F38F2_P_0 */
/* VEX_LEN_0F3A06_P_2 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
- },
-
- /* VEX_LEN_0F3A0A_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- },
-
- /* VEX_LEN_0F3A0B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A06_P_2_L_0) },
},
/* VEX_LEN_0F3A14_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
+ { "vpextrb", { Edqb, XM, Ib }, 0 },
},
/* VEX_LEN_0F3A15_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
+ { "vpextrw", { Edqw, XM, Ib }, 0 },
},
/* VEX_LEN_0F3A16_P_2 */
/* VEX_LEN_0F3A18_P_2 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A18_P_2_L_0) },
},
/* VEX_LEN_0F3A19_P_2 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A19_P_2_L_0) },
},
/* VEX_LEN_0F3A20_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
+ { "vpinsrb", { XM, Vex, Edqb, Ib }, 0 },
},
/* VEX_LEN_0F3A21_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
+ { "vinsertps", { XM, Vex, EXd, Ib }, 0 },
},
/* VEX_LEN_0F3A22_P_2 */
{
- { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
+ { "vpinsrK", { XM, Vex, Edq, Ib }, 0 },
},
/* VEX_LEN_0F3A30_P_2 */
/* VEX_LEN_0F3A38_P_2 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A38_P_2_L_0) },
},
/* VEX_LEN_0F3A39_P_2 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A39_P_2_L_0) },
},
/* VEX_LEN_0F3A41_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
+ { "vdppd", { XM, Vex, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A46_P_2 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A46_P_2_L_0) },
},
/* VEX_LEN_0F3A60_P_2 */
{
- { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
+ { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A61_P_2 */
{
- { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
+ { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A62_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
+ { "vpcmpistrm", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A63_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
+ { "vpcmpistri", { XM, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0F3ADF_P_2 */
+ {
+ { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3A6A_P_2 */
+ /* VEX_LEN_0F3AF0_P_3 */
{
- { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { "rorxS", { Gdq, Edq, Ib }, 0 },
},
- /* VEX_LEN_0F3A6B_P_2 */
+ /* VEX_LEN_0FXOP_08_85 */
{
- { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
},
- /* VEX_LEN_0F3A6E_P_2 */
+ /* VEX_LEN_0FXOP_08_86 */
{
- { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
},
- /* VEX_LEN_0F3A6F_P_2 */
+ /* VEX_LEN_0FXOP_08_87 */
{
- { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
},
- /* VEX_LEN_0F3A7A_P_2 */
+ /* VEX_LEN_0FXOP_08_8E */
{
- { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
},
- /* VEX_LEN_0F3A7B_P_2 */
+ /* VEX_LEN_0FXOP_08_8F */
{
- { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
},
- /* VEX_LEN_0F3A7E_P_2 */
+ /* VEX_LEN_0FXOP_08_95 */
{
- { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
},
- /* VEX_LEN_0F3A7F_P_2 */
+ /* VEX_LEN_0FXOP_08_96 */
{
- { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
},
- /* VEX_LEN_0F3ADF_P_2 */
+ /* VEX_LEN_0FXOP_08_97 */
{
- { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
},
- /* VEX_LEN_0F3AF0_P_3 */
+ /* VEX_LEN_0FXOP_08_9E */
{
- { "rorxS", { Gdq, Edq, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_9F */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_A3 */
+ {
+ { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_A6 */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_B6 */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_C0 */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_C1 */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_C2 */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
+ },
+
+ /* VEX_LEN_0FXOP_08_C3 */
+ {
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
},
/* VEX_LEN_0FXOP_08_CC */
{
- { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
},
/* VEX_LEN_0FXOP_08_CD */
{
- { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
},
/* VEX_LEN_0FXOP_08_CE */
{
- { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
},
/* VEX_LEN_0FXOP_08_CF */
{
- { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
},
/* VEX_LEN_0FXOP_08_EC */
{
- { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
},
/* VEX_LEN_0FXOP_08_ED */
{
- { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
},
/* VEX_LEN_0FXOP_08_EE */
{
- { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
},
/* VEX_LEN_0FXOP_08_EF */
{
- { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
},
- /* VEX_LEN_0FXOP_09_80 */
+ /* VEX_LEN_0FXOP_09_01 */
{
- { "vfrczps", { XM, EXxmm }, 0 },
- { "vfrczps", { XM, EXymmq }, 0 },
+ { REG_TABLE (REG_0FXOP_09_01_L_0) },
},
- /* VEX_LEN_0FXOP_09_81 */
+ /* VEX_LEN_0FXOP_09_02 */
{
- { "vfrczpd", { XM, EXxmm }, 0 },
- { "vfrczpd", { XM, EXymmq }, 0 },
+ { REG_TABLE (REG_0FXOP_09_02_L_0) },
},
-};
-static const struct dis386 vex_w_table[][2] = {
+ /* VEX_LEN_0FXOP_09_12_M_1 */
{
- /* VEX_W_0F10_P_0 */
- { "vmovups", { XM, EXx }, 0 },
+ { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_82_W_0 */
{
- /* VEX_W_0F10_P_1 */
- { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
+ { "vfrczss", { XM, EXd }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_83_W_0 */
{
- /* VEX_W_0F10_P_2 */
- { "vmovupd", { XM, EXx }, 0 },
+ { "vfrczsd", { XM, EXq }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_90 */
{
- /* VEX_W_0F10_P_3 */
- { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
+ { "vprotb", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_91 */
{
- /* VEX_W_0F11_P_0 */
- { "vmovups", { EXxS, XM }, 0 },
+ { "vprotw", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_92 */
{
- /* VEX_W_0F11_P_1 */
- { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
+ { "vprotd", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_93 */
{
- /* VEX_W_0F11_P_2 */
- { "vmovupd", { EXxS, XM }, 0 },
+ { "vprotq", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_94 */
{
- /* VEX_W_0F11_P_3 */
- { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
+ { "vpshlb", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_95 */
{
- /* VEX_W_0F12_P_0_M_0 */
- { "vmovlps", { XM, Vex128, EXq }, 0 },
+ { "vpshlw", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_96 */
{
- /* VEX_W_0F12_P_0_M_1 */
- { "vmovhlps", { XM, Vex128, EXq }, 0 },
+ { "vpshld", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_97 */
{
- /* VEX_W_0F12_P_1 */
- { "vmovsldup", { XM, EXx }, 0 },
+ { "vpshlq", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_98 */
{
- /* VEX_W_0F12_P_2 */
- { "vmovlpd", { XM, Vex128, EXq }, 0 },
+ { "vpshab", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_99 */
{
- /* VEX_W_0F12_P_3 */
- { "vmovddup", { XM, EXymmq }, 0 },
+ { "vpshaw", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_9A */
{
- /* VEX_W_0F13_M_0 */
- { "vmovlpX", { EXq, XM }, 0 },
+ { "vpshad", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_9B */
{
- /* VEX_W_0F14 */
- { "vunpcklpX", { XM, Vex, EXx }, 0 },
+ { "vpshaq", { XM, EXx, VexW }, 0 },
},
+
+ /* VEX_LEN_0FXOP_09_C1 */
{
- /* VEX_W_0F15 */
- { "vunpckhpX", { XM, Vex, EXx }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_C2 */
{
- /* VEX_W_0F16_P_0_M_0 */
- { "vmovhps", { XM, Vex128, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_C3 */
{
- /* VEX_W_0F16_P_0_M_1 */
- { "vmovlhps", { XM, Vex128, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_C6 */
{
- /* VEX_W_0F16_P_1 */
- { "vmovshdup", { XM, EXx }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_C7 */
{
- /* VEX_W_0F16_P_2 */
- { "vmovhpd", { XM, Vex128, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_CB */
{
- /* VEX_W_0F17_M_0 */
- { "vmovhpX", { EXq, XM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_D1 */
{
- /* VEX_W_0F28 */
- { "vmovapX", { XM, EXx }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_D2 */
{
- /* VEX_W_0F29 */
- { "vmovapX", { EXxS, XM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_D3 */
{
- /* VEX_W_0F2B_M_0 */
- { "vmovntpX", { Mx, XM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_D6 */
{
- /* VEX_W_0F2E_P_0 */
- { "vucomiss", { XMScalar, EXdScalar }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_D7 */
{
- /* VEX_W_0F2E_P_2 */
- { "vucomisd", { XMScalar, EXqScalar }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_DB */
{
- /* VEX_W_0F2F_P_0 */
- { "vcomiss", { XMScalar, EXdScalar }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_E1 */
{
- /* VEX_W_0F2F_P_2 */
- { "vcomisd", { XMScalar, EXqScalar }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_E2 */
{
- /* VEX_W_0F41_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
},
+
+ /* VEX_LEN_0FXOP_09_E3 */
{
- /* VEX_W_0F41_P_2_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
},
+
+ /* VEX_LEN_0FXOP_0A_12 */
{
- /* VEX_W_0F42_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
+ { REG_TABLE (REG_0FXOP_0A_12_L_0) },
+ },
+};
+
+#include "i386-dis-evex-len.h"
+
+static const struct dis386 vex_w_table[][2] = {
+ {
+ /* VEX_W_0F41_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F41_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
+ },
+ {
+ /* VEX_W_0F42_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
},
{
/* VEX_W_0F42_P_2_LEN_1 */
{ MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
},
{
- /* VEX_W_0F50_M_0 */
- { "vmovmskpX", { Gdq, XS }, 0 },
- },
- {
- /* VEX_W_0F51_P_0 */
- { "vsqrtps", { XM, EXx }, 0 },
+ /* VEX_W_0F90_P_0_LEN_0 */
+ { "kmovw", { MaskG, MaskE }, 0 },
+ { "kmovq", { MaskG, MaskE }, 0 },
},
{
- /* VEX_W_0F51_P_1 */
- { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F90_P_2_LEN_0 */
+ { "kmovb", { MaskG, MaskBDE }, 0 },
+ { "kmovd", { MaskG, MaskBDE }, 0 },
},
{
- /* VEX_W_0F51_P_2 */
- { "vsqrtpd", { XM, EXx }, 0 },
+ /* VEX_W_0F91_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
},
{
- /* VEX_W_0F51_P_3 */
- { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F91_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
},
{
- /* VEX_W_0F52_P_0 */
- { "vrsqrtps", { XM, EXx }, 0 },
+ /* VEX_W_0F92_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
},
{
- /* VEX_W_0F52_P_1 */
- { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F92_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
},
{
- /* VEX_W_0F53_P_0 */
- { "vrcpps", { XM, EXx }, 0 },
+ /* VEX_W_0F93_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
},
{
- /* VEX_W_0F53_P_1 */
- { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F93_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
},
{
- /* VEX_W_0F58_P_0 */
- { "vaddps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F98_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
},
{
- /* VEX_W_0F58_P_1 */
- { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F98_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
},
{
- /* VEX_W_0F58_P_2 */
- { "vaddpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F99_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
},
{
- /* VEX_W_0F58_P_3 */
- { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F99_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
},
{
- /* VEX_W_0F59_P_0 */
- { "vmulps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F380C_P_2 */
+ { "vpermilps", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F59_P_1 */
- { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F380D_P_2 */
+ { "vpermilpd", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F59_P_2 */
- { "vmulpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F380E_P_2 */
+ { "vtestps", { XM, EXx }, 0 },
},
{
- /* VEX_W_0F59_P_3 */
- { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F380F_P_2 */
+ { "vtestpd", { XM, EXx }, 0 },
},
{
- /* VEX_W_0F5A_P_0 */
- { "vcvtps2pd", { XM, EXxmmq }, 0 },
+ /* VEX_W_0F3813_P_2 */
+ { "vcvtph2ps", { XM, EXxmmq }, 0 },
},
{
- /* VEX_W_0F5A_P_1 */
- { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F3816_P_2 */
+ { "vpermps", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F5A_P_3 */
- { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F3818_P_2 */
+ { "vbroadcastss", { XM, EXxmm_md }, 0 },
},
{
- /* VEX_W_0F5B_P_0 */
- { "vcvtdq2ps", { XM, EXx }, 0 },
+ /* VEX_W_0F3819_P_2 */
+ { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
},
{
- /* VEX_W_0F5B_P_1 */
- { "vcvttps2dq", { XM, EXx }, 0 },
+ /* VEX_W_0F381A_P_2_M_0_L_0 */
+ { "vbroadcastf128", { XM, Mxmm }, 0 },
},
{
- /* VEX_W_0F5B_P_2 */
- { "vcvtps2dq", { XM, EXx }, 0 },
+ /* VEX_W_0F382C_P_2_M_0 */
+ { "vmaskmovps", { XM, Vex, Mx }, 0 },
},
{
- /* VEX_W_0F5C_P_0 */
- { "vsubps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F382D_P_2_M_0 */
+ { "vmaskmovpd", { XM, Vex, Mx }, 0 },
},
{
- /* VEX_W_0F5C_P_1 */
- { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F382E_P_2_M_0 */
+ { "vmaskmovps", { Mx, Vex, XM }, 0 },
},
{
- /* VEX_W_0F5C_P_2 */
- { "vsubpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F382F_P_2_M_0 */
+ { "vmaskmovpd", { Mx, Vex, XM }, 0 },
},
{
- /* VEX_W_0F5C_P_3 */
- { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F3836_P_2 */
+ { "vpermd", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F5D_P_0 */
- { "vminps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3846_P_2 */
+ { "vpsravd", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F5D_P_1 */
- { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F3849_X86_64_P_0 */
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
},
{
- /* VEX_W_0F5D_P_2 */
- { "vminpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3849_X86_64_P_2 */
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
},
{
- /* VEX_W_0F5D_P_3 */
- { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F3849_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
},
{
- /* VEX_W_0F5E_P_0 */
- { "vdivps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F384B_X86_64_P_1 */
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
},
{
- /* VEX_W_0F5E_P_1 */
- { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F384B_X86_64_P_2 */
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
},
{
- /* VEX_W_0F5E_P_2 */
- { "vdivpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F384B_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
},
{
- /* VEX_W_0F5E_P_3 */
- { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F3858_P_2 */
+ { "vpbroadcastd", { XM, EXxmm_md }, 0 },
},
{
- /* VEX_W_0F5F_P_0 */
- { "vmaxps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3859_P_2 */
+ { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
},
{
- /* VEX_W_0F5F_P_1 */
- { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F385A_P_2_M_0_L_0 */
+ { "vbroadcasti128", { XM, Mxmm }, 0 },
},
{
- /* VEX_W_0F5F_P_2 */
- { "vmaxpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F385C_X86_64_P_1 */
+ { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
},
{
- /* VEX_W_0F5F_P_3 */
- { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F385E_X86_64_P_0 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
},
{
- /* VEX_W_0F60_P_2 */
- { "vpunpcklbw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F385E_X86_64_P_1 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
},
{
- /* VEX_W_0F61_P_2 */
- { "vpunpcklwd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F385E_X86_64_P_2 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
},
{
- /* VEX_W_0F62_P_2 */
- { "vpunpckldq", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F385E_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
},
{
- /* VEX_W_0F63_P_2 */
- { "vpacksswb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3878_P_2 */
+ { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
},
{
- /* VEX_W_0F64_P_2 */
- { "vpcmpgtb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3879_P_2 */
+ { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
},
{
- /* VEX_W_0F65_P_2 */
- { "vpcmpgtw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F38CF_P_2 */
+ { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
},
{
- /* VEX_W_0F66_P_2 */
- { "vpcmpgtd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A00_P_2 */
+ { Bad_Opcode },
+ { "vpermq", { XM, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F67_P_2 */
- { "vpackuswb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A01_P_2 */
+ { Bad_Opcode },
+ { "vpermpd", { XM, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F68_P_2 */
- { "vpunpckhbw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A02_P_2 */
+ { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F69_P_2 */
- { "vpunpckhwd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A04_P_2 */
+ { "vpermilps", { XM, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F6A_P_2 */
- { "vpunpckhdq", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A05_P_2 */
+ { "vpermilpd", { XM, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F6B_P_2 */
- { "vpackssdw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A06_P_2_L_0 */
+ { "vperm2f128", { XM, Vex, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F6C_P_2 */
- { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A18_P_2_L_0 */
+ { "vinsertf128", { XM, Vex, EXxmm, Ib }, 0 },
},
{
- /* VEX_W_0F6D_P_2 */
- { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3A19_P_2_L_0 */
+ { "vextractf128", { EXxmm, XM, Ib }, 0 },
},
{
- /* VEX_W_0F6F_P_1 */
- { "vmovdqu", { XM, EXx }, 0 },
+ /* VEX_W_0F3A1D_P_2 */
+ { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
},
{
- /* VEX_W_0F6F_P_2 */
- { "vmovdqa", { XM, EXx }, 0 },
+ /* VEX_W_0F3A30_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
},
{
- /* VEX_W_0F70_P_1 */
- { "vpshufhw", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F3A31_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
},
{
- /* VEX_W_0F70_P_2 */
- { "vpshufd", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F3A32_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
},
{
- /* VEX_W_0F70_P_3 */
- { "vpshuflw", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F3A33_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
},
{
- /* VEX_W_0F71_R_2_P_2 */
- { "vpsrlw", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3A38_P_2_L_0 */
+ { "vinserti128", { XM, Vex, EXxmm, Ib }, 0 },
},
{
- /* VEX_W_0F71_R_4_P_2 */
- { "vpsraw", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3A39_P_2_L_0 */
+ { "vextracti128", { EXxmm, XM, Ib }, 0 },
},
{
- /* VEX_W_0F71_R_6_P_2 */
- { "vpsllw", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3A46_P_2_L_0 */
+ { "vperm2i128", { XM, Vex, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F72_R_2_P_2 */
- { "vpsrld", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3A4A_P_2 */
+ { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
{
- /* VEX_W_0F72_R_4_P_2 */
- { "vpsrad", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3A4B_P_2 */
+ { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
{
- /* VEX_W_0F72_R_6_P_2 */
- { "vpslld", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3A4C_P_2 */
+ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
},
{
- /* VEX_W_0F73_R_2_P_2 */
- { "vpsrlq", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3ACE_P_2 */
+ { Bad_Opcode },
+ { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F73_R_3_P_2 */
- { "vpsrldq", { Vex, XS, Ib }, 0 },
+ /* VEX_W_0F3ACF_P_2 */
+ { Bad_Opcode },
+ { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
},
+ /* VEX_W_0FXOP_08_85_L_0 */
{
- /* VEX_W_0F73_R_6_P_2 */
- { "vpsllq", { Vex, XS, Ib }, 0 },
+ { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_86_L_0 */
{
- /* VEX_W_0F73_R_7_P_2 */
- { "vpslldq", { Vex, XS, Ib }, 0 },
+ { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_87_L_0 */
{
- /* VEX_W_0F74_P_2 */
- { "vpcmpeqb", { XM, Vex, EXx }, 0 },
+ { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_8E_L_0 */
{
- /* VEX_W_0F75_P_2 */
- { "vpcmpeqw", { XM, Vex, EXx }, 0 },
+ { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_8F_L_0 */
{
- /* VEX_W_0F76_P_2 */
- { "vpcmpeqd", { XM, Vex, EXx }, 0 },
+ { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_95_L_0 */
{
- /* VEX_W_0F77_P_0 */
- { "", { VZERO }, 0 },
+ { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_96_L_0 */
{
- /* VEX_W_0F7C_P_2 */
- { "vhaddpd", { XM, Vex, EXx }, 0 },
+ { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_97_L_0 */
{
- /* VEX_W_0F7C_P_3 */
- { "vhaddps", { XM, Vex, EXx }, 0 },
+ { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_9E_L_0 */
{
- /* VEX_W_0F7D_P_2 */
- { "vhsubpd", { XM, Vex, EXx }, 0 },
+ { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_9F_L_0 */
{
- /* VEX_W_0F7D_P_3 */
- { "vhsubps", { XM, Vex, EXx }, 0 },
+ { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_A6_L_0 */
{
- /* VEX_W_0F7E_P_1 */
- { "vmovq", { XMScalar, EXqScalar }, 0 },
+ { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_B6_L_0 */
{
- /* VEX_W_0F7F_P_1 */
- { "vmovdqu", { EXxS, XM }, 0 },
+ { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
+ /* VEX_W_0FXOP_08_C0_L_0 */
{
- /* VEX_W_0F7F_P_2 */
- { "vmovdqa", { EXxS, XM }, 0 },
+ { "vprotb", { XM, EXx, Ib }, 0 },
},
+ /* VEX_W_0FXOP_08_C1_L_0 */
{
- /* VEX_W_0F90_P_0_LEN_0 */
- { "kmovw", { MaskG, MaskE }, 0 },
- { "kmovq", { MaskG, MaskE }, 0 },
+ { "vprotw", { XM, EXx, Ib }, 0 },
},
+ /* VEX_W_0FXOP_08_C2_L_0 */
{
- /* VEX_W_0F90_P_2_LEN_0 */
- { "kmovb", { MaskG, MaskBDE }, 0 },
- { "kmovd", { MaskG, MaskBDE }, 0 },
+ { "vprotd", { XM, EXx, Ib }, 0 },
},
+ /* VEX_W_0FXOP_08_C3_L_0 */
{
- /* VEX_W_0F91_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
+ { "vprotq", { XM, EXx, Ib }, 0 },
},
+ /* VEX_W_0FXOP_08_CC_L_0 */
{
- /* VEX_W_0F91_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
+ { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_CD_L_0 */
{
- /* VEX_W_0F92_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
+ { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_CE_L_0 */
{
- /* VEX_W_0F92_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
+ { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_CF_L_0 */
{
- /* VEX_W_0F92_P_3_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
+ { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_EC_L_0 */
{
- /* VEX_W_0F93_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
+ { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_ED_L_0 */
{
- /* VEX_W_0F93_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
+ { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_EE_L_0 */
{
- /* VEX_W_0F93_P_3_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
+ { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_08_EF_L_0 */
{
- /* VEX_W_0F98_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
+ { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
},
+ /* VEX_W_0FXOP_09_80 */
{
- /* VEX_W_0F98_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
+ { "vfrczps", { XM, EXx }, 0 },
},
+ /* VEX_W_0FXOP_09_81 */
{
- /* VEX_W_0F99_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
+ { "vfrczpd", { XM, EXx }, 0 },
},
+ /* VEX_W_0FXOP_09_82 */
{
- /* VEX_W_0F99_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
},
+ /* VEX_W_0FXOP_09_83 */
{
- /* VEX_W_0FAE_R_2_M_0 */
- { "vldmxcsr", { Md }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
},
+ /* VEX_W_0FXOP_09_C1_L_0 */
{
- /* VEX_W_0FAE_R_3_M_0 */
- { "vstmxcsr", { Md }, 0 },
+ { "vphaddbw", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_C2_L_0 */
{
- /* VEX_W_0FC2_P_0 */
- { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
+ { "vphaddbd", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_C3_L_0 */
{
- /* VEX_W_0FC2_P_1 */
- { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
+ { "vphaddbq", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_C6_L_0 */
{
- /* VEX_W_0FC2_P_2 */
- { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
+ { "vphaddwd", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_C7_L_0 */
{
- /* VEX_W_0FC2_P_3 */
- { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
+ { "vphaddwq", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_CB_L_0 */
{
- /* VEX_W_0FC4_P_2 */
- { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
+ { "vphadddq", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_D1_L_0 */
{
- /* VEX_W_0FC5_P_2 */
- { "vpextrw", { Gdq, XS, Ib }, 0 },
+ { "vphaddubw", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_D2_L_0 */
{
- /* VEX_W_0FD0_P_2 */
- { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ { "vphaddubd", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_D3_L_0 */
{
- /* VEX_W_0FD0_P_3 */
- { "vaddsubps", { XM, Vex, EXx }, 0 },
+ { "vphaddubq", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_D6_L_0 */
{
- /* VEX_W_0FD1_P_2 */
- { "vpsrlw", { XM, Vex, EXxmm }, 0 },
+ { "vphadduwd", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_D7_L_0 */
{
- /* VEX_W_0FD2_P_2 */
- { "vpsrld", { XM, Vex, EXxmm }, 0 },
+ { "vphadduwq", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_DB_L_0 */
{
- /* VEX_W_0FD3_P_2 */
- { "vpsrlq", { XM, Vex, EXxmm }, 0 },
+ { "vphaddudq", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_E1_L_0 */
{
- /* VEX_W_0FD4_P_2 */
- { "vpaddq", { XM, Vex, EXx }, 0 },
+ { "vphsubbw", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_E2_L_0 */
{
- /* VEX_W_0FD5_P_2 */
- { "vpmullw", { XM, Vex, EXx }, 0 },
+ { "vphsubwd", { XM, EXxmm }, 0 },
},
+ /* VEX_W_0FXOP_09_E3_L_0 */
{
- /* VEX_W_0FD6_P_2 */
- { "vmovq", { EXqScalarS, XMScalar }, 0 },
+ { "vphsubdq", { XM, EXxmm }, 0 },
},
+
+#include "i386-dis-evex-w.h"
+};
+
+static const struct dis386 mod_table[][2] = {
{
- /* VEX_W_0FD7_P_2_M_1 */
- { "vpmovmskb", { Gdq, XS }, 0 },
+ /* MOD_8D */
+ { "leaS", { Gv, M }, 0 },
},
{
- /* VEX_W_0FD8_P_2 */
- { "vpsubusb", { XM, Vex, EXx }, 0 },
+ /* MOD_C6_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C6_REG_7) },
},
{
- /* VEX_W_0FD9_P_2 */
- { "vpsubusw", { XM, Vex, EXx }, 0 },
+ /* MOD_C7_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C7_REG_7) },
},
{
- /* VEX_W_0FDA_P_2 */
- { "vpminub", { XM, Vex, EXx }, 0 },
+ /* MOD_FF_REG_3 */
+ { "{l|}call^", { indirEp }, 0 },
},
{
- /* VEX_W_0FDB_P_2 */
- { "vpand", { XM, Vex, EXx }, 0 },
+ /* MOD_FF_REG_5 */
+ { "{l|}jmp^", { indirEp }, 0 },
},
{
- /* VEX_W_0FDC_P_2 */
- { "vpaddusb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F01_REG_0 */
+ { X86_64_TABLE (X86_64_0F01_REG_0) },
+ { RM_TABLE (RM_0F01_REG_0) },
},
{
- /* VEX_W_0FDD_P_2 */
- { "vpaddusw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F01_REG_1 */
+ { X86_64_TABLE (X86_64_0F01_REG_1) },
+ { RM_TABLE (RM_0F01_REG_1) },
},
{
- /* VEX_W_0FDE_P_2 */
- { "vpmaxub", { XM, Vex, EXx }, 0 },
+ /* MOD_0F01_REG_2 */
+ { X86_64_TABLE (X86_64_0F01_REG_2) },
+ { RM_TABLE (RM_0F01_REG_2) },
},
{
- /* VEX_W_0FDF_P_2 */
- { "vpandn", { XM, Vex, EXx }, 0 },
+ /* MOD_0F01_REG_3 */
+ { X86_64_TABLE (X86_64_0F01_REG_3) },
+ { RM_TABLE (RM_0F01_REG_3) },
},
{
- /* VEX_W_0FE0_P_2 */
- { "vpavgb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F01_REG_5 */
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
+ { RM_TABLE (RM_0F01_REG_5_MOD_3) },
},
{
- /* VEX_W_0FE1_P_2 */
- { "vpsraw", { XM, Vex, EXxmm }, 0 },
+ /* MOD_0F01_REG_7 */
+ { "invlpg", { Mb }, 0 },
+ { RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
- /* VEX_W_0FE2_P_2 */
- { "vpsrad", { XM, Vex, EXxmm }, 0 },
+ /* MOD_0F12_PREFIX_0 */
+ { "movlpX", { XM, EXq }, 0 },
+ { "movhlps", { XM, EXq }, 0 },
},
{
- /* VEX_W_0FE3_P_2 */
- { "vpavgw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F12_PREFIX_2 */
+ { "movlpX", { XM, EXq }, 0 },
},
{
- /* VEX_W_0FE4_P_2 */
- { "vpmulhuw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F13 */
+ { "movlpX", { EXq, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FE5_P_2 */
- { "vpmulhw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F16_PREFIX_0 */
+ { "movhpX", { XM, EXq }, 0 },
+ { "movlhps", { XM, EXq }, 0 },
},
{
- /* VEX_W_0FE6_P_1 */
- { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ /* MOD_0F16_PREFIX_2 */
+ { "movhpX", { XM, EXq }, 0 },
},
{
- /* VEX_W_0FE6_P_2 */
- { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ /* MOD_0F17 */
+ { "movhpX", { EXq, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FE6_P_3 */
- { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
+ /* MOD_0F18_REG_0 */
+ { "prefetchnta", { Mb }, 0 },
},
{
- /* VEX_W_0FE7_P_2_M_0 */
- { "vmovntdq", { Mx, XM }, 0 },
+ /* MOD_0F18_REG_1 */
+ { "prefetcht0", { Mb }, 0 },
},
{
- /* VEX_W_0FE8_P_2 */
- { "vpsubsb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F18_REG_2 */
+ { "prefetcht1", { Mb }, 0 },
},
{
- /* VEX_W_0FE9_P_2 */
- { "vpsubsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F18_REG_3 */
+ { "prefetcht2", { Mb }, 0 },
},
{
- /* VEX_W_0FEA_P_2 */
- { "vpminsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F18_REG_4 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* VEX_W_0FEB_P_2 */
- { "vpor", { XM, Vex, EXx }, 0 },
+ /* MOD_0F18_REG_5 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* VEX_W_0FEC_P_2 */
- { "vpaddsb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F18_REG_6 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* VEX_W_0FED_P_2 */
- { "vpaddsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F18_REG_7 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* VEX_W_0FEE_P_2 */
- { "vpmaxsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F1A_PREFIX_0 */
+ { "bndldx", { Gbnd, Mv_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
},
{
- /* VEX_W_0FEF_P_2 */
- { "vpxor", { XM, Vex, EXx }, 0 },
+ /* MOD_0F1B_PREFIX_0 */
+ { "bndstx", { Mv_bnd, Gbnd }, 0 },
+ { "nopQ", { Ev }, 0 },
},
{
- /* VEX_W_0FF0_P_3_M_0 */
- { "vlddqu", { XM, M }, 0 },
+ /* MOD_0F1B_PREFIX_1 */
+ { "bndmk", { Gbnd, Mv_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
},
{
- /* VEX_W_0FF1_P_2 */
- { "vpsllw", { XM, Vex, EXxmm }, 0 },
+ /* MOD_0F1C_PREFIX_0 */
+ { REG_TABLE (REG_0F1C_P_0_MOD_0) },
+ { "nopQ", { Ev }, 0 },
},
{
- /* VEX_W_0FF2_P_2 */
- { "vpslld", { XM, Vex, EXxmm }, 0 },
+ /* MOD_0F1E_PREFIX_1 */
+ { "nopQ", { Ev }, 0 },
+ { REG_TABLE (REG_0F1E_P_1_MOD_3) },
},
{
- /* VEX_W_0FF3_P_2 */
- { "vpsllq", { XM, Vex, EXxmm }, 0 },
+ /* MOD_0F24 */
+ { Bad_Opcode },
+ { "movL", { Rd, Td }, 0 },
},
{
- /* VEX_W_0FF4_P_2 */
- { "vpmuludq", { XM, Vex, EXx }, 0 },
+ /* MOD_0F26 */
+ { Bad_Opcode },
+ { "movL", { Td, Rd }, 0 },
},
{
- /* VEX_W_0FF5_P_2 */
- { "vpmaddwd", { XM, Vex, EXx }, 0 },
+ /* MOD_0F2B_PREFIX_0 */
+ {"movntps", { Mx, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FF6_P_2 */
- { "vpsadbw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F2B_PREFIX_1 */
+ {"movntss", { Md, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FF7_P_2 */
- { "vmaskmovdqu", { XM, XS }, 0 },
+ /* MOD_0F2B_PREFIX_2 */
+ {"movntpd", { Mx, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FF8_P_2 */
- { "vpsubb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F2B_PREFIX_3 */
+ {"movntsd", { Mq, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FF9_P_2 */
- { "vpsubw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F50 */
+ { Bad_Opcode },
+ { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
- /* VEX_W_0FFA_P_2 */
- { "vpsubd", { XM, Vex, EXx }, 0 },
+ /* MOD_0F71_REG_2 */
+ { Bad_Opcode },
+ { "psrlw", { MS, Ib }, 0 },
},
{
- /* VEX_W_0FFB_P_2 */
- { "vpsubq", { XM, Vex, EXx }, 0 },
+ /* MOD_0F71_REG_4 */
+ { Bad_Opcode },
+ { "psraw", { MS, Ib }, 0 },
},
{
- /* VEX_W_0FFC_P_2 */
- { "vpaddb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F71_REG_6 */
+ { Bad_Opcode },
+ { "psllw", { MS, Ib }, 0 },
},
{
- /* VEX_W_0FFD_P_2 */
- { "vpaddw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F72_REG_2 */
+ { Bad_Opcode },
+ { "psrld", { MS, Ib }, 0 },
},
{
- /* VEX_W_0FFE_P_2 */
- { "vpaddd", { XM, Vex, EXx }, 0 },
+ /* MOD_0F72_REG_4 */
+ { Bad_Opcode },
+ { "psrad", { MS, Ib }, 0 },
},
{
- /* VEX_W_0F3800_P_2 */
- { "vpshufb", { XM, Vex, EXx }, 0 },
+ /* MOD_0F72_REG_6 */
+ { Bad_Opcode },
+ { "pslld", { MS, Ib }, 0 },
},
{
- /* VEX_W_0F3801_P_2 */
- { "vphaddw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F73_REG_2 */
+ { Bad_Opcode },
+ { "psrlq", { MS, Ib }, 0 },
},
{
- /* VEX_W_0F3802_P_2 */
- { "vphaddd", { XM, Vex, EXx }, 0 },
+ /* MOD_0F73_REG_3 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F73_REG_3) },
},
{
- /* VEX_W_0F3803_P_2 */
- { "vphaddsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F73_REG_6 */
+ { Bad_Opcode },
+ { "psllq", { MS, Ib }, 0 },
},
{
- /* VEX_W_0F3804_P_2 */
- { "vpmaddubsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0F73_REG_7 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F73_REG_7) },
},
{
- /* VEX_W_0F3805_P_2 */
- { "vphsubw", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_0 */
+ { "fxsave", { FXSAVE }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
},
{
- /* VEX_W_0F3806_P_2 */
- { "vphsubd", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_1 */
+ { "fxrstor", { FXSAVE }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
},
{
- /* VEX_W_0F3807_P_2 */
- { "vphsubsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_2 */
+ { "ldmxcsr", { Md }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
},
{
- /* VEX_W_0F3808_P_2 */
- { "vpsignb", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_3 */
+ { "stmxcsr", { Md }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
},
{
- /* VEX_W_0F3809_P_2 */
- { "vpsignw", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_4 */
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
},
{
- /* VEX_W_0F380A_P_2 */
- { "vpsignd", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_5 */
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
},
{
- /* VEX_W_0F380B_P_2 */
- { "vpmulhrsw", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_6 */
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
},
{
- /* VEX_W_0F380C_P_2 */
- { "vpermilps", { XM, Vex, EXx }, 0 },
+ /* MOD_0FAE_REG_7 */
+ { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
+ { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
},
{
- /* VEX_W_0F380D_P_2 */
- { "vpermilpd", { XM, Vex, EXx }, 0 },
+ /* MOD_0FB2 */
+ { "lssS", { Gv, Mp }, 0 },
},
{
- /* VEX_W_0F380E_P_2 */
- { "vtestps", { XM, EXx }, 0 },
+ /* MOD_0FB4 */
+ { "lfsS", { Gv, Mp }, 0 },
},
{
- /* VEX_W_0F380F_P_2 */
- { "vtestpd", { XM, EXx }, 0 },
+ /* MOD_0FB5 */
+ { "lgsS", { Gv, Mp }, 0 },
},
{
- /* VEX_W_0F3816_P_2 */
- { "vpermps", { XM, Vex, EXx }, 0 },
+ /* MOD_0FC3 */
+ { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
},
{
- /* VEX_W_0F3817_P_2 */
- { "vptest", { XM, EXx }, 0 },
+ /* MOD_0FC7_REG_3 */
+ { "xrstors", { FXSAVE }, 0 },
},
{
- /* VEX_W_0F3818_P_2 */
- { "vbroadcastss", { XM, EXxmm_md }, 0 },
+ /* MOD_0FC7_REG_4 */
+ { "xsavec", { FXSAVE }, 0 },
},
{
- /* VEX_W_0F3819_P_2 */
- { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
+ /* MOD_0FC7_REG_5 */
+ { "xsaves", { FXSAVE }, 0 },
},
{
- /* VEX_W_0F381A_P_2_M_0 */
- { "vbroadcastf128", { XM, Mxmm }, 0 },
+ /* MOD_0FC7_REG_6 */
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
},
{
- /* VEX_W_0F381C_P_2 */
- { "vpabsb", { XM, EXx }, 0 },
+ /* MOD_0FC7_REG_7 */
+ { "vmptrst", { Mq }, 0 },
+ { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
},
{
- /* VEX_W_0F381D_P_2 */
- { "vpabsw", { XM, EXx }, 0 },
+ /* MOD_0FD7 */
+ { Bad_Opcode },
+ { "pmovmskb", { Gdq, MS }, 0 },
},
{
- /* VEX_W_0F381E_P_2 */
- { "vpabsd", { XM, EXx }, 0 },
+ /* MOD_0FE7_PREFIX_2 */
+ { "movntdq", { Mx, XM }, 0 },
},
{
- /* VEX_W_0F3820_P_2 */
- { "vpmovsxbw", { XM, EXxmmq }, 0 },
+ /* MOD_0FF0_PREFIX_3 */
+ { "lddqu", { XM, M }, 0 },
},
{
- /* VEX_W_0F3821_P_2 */
- { "vpmovsxbd", { XM, EXxmmqd }, 0 },
+ /* MOD_0F382A_PREFIX_2 */
+ { "movntdqa", { XM, Mx }, 0 },
},
{
- /* VEX_W_0F3822_P_2 */
- { "vpmovsxbq", { XM, EXxmmdw }, 0 },
+ /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
+ { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
},
{
- /* VEX_W_0F3823_P_2 */
- { "vpmovsxwd", { XM, EXxmmq }, 0 },
+ /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
},
{
- /* VEX_W_0F3824_P_2 */
- { "vpmovsxwq", { XM, EXxmmqd }, 0 },
+ /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
},
{
- /* VEX_W_0F3825_P_2 */
- { "vpmovsxdq", { XM, EXxmmq }, 0 },
+ /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
},
{
- /* VEX_W_0F3828_P_2 */
- { "vpmuldq", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
},
{
- /* VEX_W_0F3829_P_2 */
- { "vpcmpeqq", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
},
{
- /* VEX_W_0F382A_P_2_M_0 */
- { "vmovntdqa", { XM, Mx }, 0 },
+ /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
},
{
- /* VEX_W_0F382B_P_2 */
- { "vpackusdw", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
},
{
- /* VEX_W_0F382C_P_2_M_0 */
- { "vmaskmovps", { XM, Vex, Mx }, 0 },
+ /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
},
{
- /* VEX_W_0F382D_P_2_M_0 */
- { "vmaskmovpd", { XM, Vex, Mx }, 0 },
+ /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
},
{
- /* VEX_W_0F382E_P_2_M_0 */
- { "vmaskmovps", { Mx, Vex, XM }, 0 },
+ /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
},
{
- /* VEX_W_0F382F_P_2_M_0 */
- { "vmaskmovpd", { Mx, Vex, XM }, 0 },
+ /* MOD_0F38F5_PREFIX_2 */
+ { "wrussK", { M, Gdq }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3830_P_2 */
- { "vpmovzxbw", { XM, EXxmmq }, 0 },
+ /* MOD_0F38F6_PREFIX_0 */
+ { "wrssK", { M, Gdq }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3831_P_2 */
- { "vpmovzxbd", { XM, EXxmmqd }, 0 },
+ /* MOD_0F38F8_PREFIX_1 */
+ { "enqcmds", { Gva, M }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3832_P_2 */
- { "vpmovzxbq", { XM, EXxmmdw }, 0 },
+ /* MOD_0F38F8_PREFIX_2 */
+ { "movdir64b", { Gva, M }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3833_P_2 */
- { "vpmovzxwd", { XM, EXxmmq }, 0 },
+ /* MOD_0F38F8_PREFIX_3 */
+ { "enqcmd", { Gva, M }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3834_P_2 */
- { "vpmovzxwq", { XM, EXxmmqd }, 0 },
+ /* MOD_0F38F9_PREFIX_0 */
+ { "movdiri", { Ev, Gv }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3835_P_2 */
- { "vpmovzxdq", { XM, EXxmmq }, 0 },
+ /* MOD_62_32BIT */
+ { "bound{S|}", { Gv, Ma }, 0 },
+ { EVEX_TABLE (EVEX_0F) },
},
{
- /* VEX_W_0F3836_P_2 */
- { "vpermd", { XM, Vex, EXx }, 0 },
+ /* MOD_C4_32BIT */
+ { "lesS", { Gv, Mp }, 0 },
+ { VEX_C4_TABLE (VEX_0F) },
},
{
- /* VEX_W_0F3837_P_2 */
- { "vpcmpgtq", { XM, Vex, EXx }, 0 },
+ /* MOD_C5_32BIT */
+ { "ldsS", { Gv, Mp }, 0 },
+ { VEX_C5_TABLE (VEX_0F) },
},
{
- /* VEX_W_0F3838_P_2 */
- { "vpminsb", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F12_PREFIX_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
},
{
- /* VEX_W_0F3839_P_2 */
- { "vpminsd", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F12_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
},
{
- /* VEX_W_0F383A_P_2 */
- { "vpminuw", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F13 */
+ { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
},
{
- /* VEX_W_0F383B_P_2 */
- { "vpminud", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F16_PREFIX_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
},
{
- /* VEX_W_0F383C_P_2 */
- { "vpmaxsb", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F16_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
},
{
- /* VEX_W_0F383D_P_2 */
- { "vpmaxsd", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F17 */
+ { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
},
{
- /* VEX_W_0F383E_P_2 */
- { "vpmaxuw", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_0F2B */
+ { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F383F_P_2 */
- { "vpmaxud", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3840_P_2 */
- { "vpmulld", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3841_P_2 */
- { "vphminposuw", { XM, EXx }, 0 },
+ /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandb", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3846_P_2 */
- { "vpsravd", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandd", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3858_P_2 */
- { "vpbroadcastd", { XM, EXxmm_md }, 0 },
+ /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3859_P_2 */
- { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
+ /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F385A_P_2_M_0 */
- { "vbroadcasti128", { XM, Mxmm }, 0 },
+ /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3878_P_2 */
- { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
+ /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3879_P_2 */
- { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
+ /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotw", { MaskG, MaskR }, 0 },
},
{
- /* VEX_W_0F38CF_P_2 */
- { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
+ /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotq", { MaskG, MaskR }, 0 },
},
{
- /* VEX_W_0F38DB_P_2 */
- { "vaesimc", { XM, EXx }, 0 },
+ /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotb", { MaskG, MaskR }, 0 },
},
{
- /* VEX_W_0F3A00_P_2 */
+ /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
{ Bad_Opcode },
- { "vpermq", { XM, EXx, Ib }, 0 },
+ { "knotd", { MaskG, MaskR }, 0 },
},
{
- /* VEX_W_0F3A01_P_2 */
+ /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
{ Bad_Opcode },
- { "vpermpd", { XM, EXx, Ib }, 0 },
+ { "korw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A02_P_2 */
- { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A04_P_2 */
- { "vpermilps", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "korb", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A05_P_2 */
- { "vpermilpd", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kord", { MaskG, MaskVex, MaskR }, 0 },
},
- {
- /* VEX_W_0F3A06_P_2 */
- { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
+ {
+ /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A08_P_2 */
- { "vroundps", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A09_P_2 */
- { "vroundpd", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A0A_P_2 */
- { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
+ /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A0B_P_2 */
- { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
+ /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A0C_P_2 */
- { "vblendps", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A0D_P_2 */
- { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A0E_P_2 */
- { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxord", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A0F_P_2 */
- { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A14_P_2 */
- { "vpextrb", { Edqb, XM, Ib }, 0 },
+ /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A15_P_2 */
- { "vpextrw", { Edqw, XM, Ib }, 0 },
+ /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A18_P_2 */
- { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
+ /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A19_P_2 */
- { "vextractf128", { EXxmm, XM, Ib }, 0 },
+ /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A20_P_2 */
- { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
+ /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A21_P_2 */
- { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
+ /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
},
{
- /* VEX_W_0F3A30_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
+ /* MOD_VEX_0F50 */
+ { Bad_Opcode },
+ { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
- /* VEX_W_0F3A31_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
+ /* MOD_VEX_0F71_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
},
{
- /* VEX_W_0F3A32_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
+ /* MOD_VEX_0F71_REG_4 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
},
{
- /* VEX_W_0F3A33_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
+ /* MOD_VEX_0F71_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
},
{
- /* VEX_W_0F3A38_P_2 */
- { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
+ /* MOD_VEX_0F72_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
},
{
- /* VEX_W_0F3A39_P_2 */
- { "vextracti128", { EXxmm, XM, Ib }, 0 },
+ /* MOD_VEX_0F72_REG_4 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
},
{
- /* VEX_W_0F3A40_P_2 */
- { "vdpps", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_0F72_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
},
{
- /* VEX_W_0F3A41_P_2 */
- { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
+ /* MOD_VEX_0F73_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
},
{
- /* VEX_W_0F3A42_P_2 */
- { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
+ /* MOD_VEX_0F73_REG_3 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
},
{
- /* VEX_W_0F3A46_P_2 */
- { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
+ /* MOD_VEX_0F73_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
},
{
- /* VEX_W_0F3A48_P_2 */
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ /* MOD_VEX_0F73_REG_7 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
},
{
- /* VEX_W_0F3A49_P_2 */
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovw", { Ew, MaskG }, 0 },
+ { Bad_Opcode },
},
{
- /* VEX_W_0F3A4A_P_2 */
- { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovq", { Eq, MaskG }, 0 },
+ { Bad_Opcode },
},
{
- /* VEX_W_0F3A4B_P_2 */
- { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovb", { Eb, MaskG }, 0 },
+ { Bad_Opcode },
},
{
- /* VEX_W_0F3A4C_P_2 */
- { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovd", { Ed, MaskG }, 0 },
+ { Bad_Opcode },
},
{
- /* VEX_W_0F3A62_P_2 */
- { "vpcmpistrm", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { MaskG, Rdq }, 0 },
},
{
- /* VEX_W_0F3A63_P_2 */
- { "vpcmpistri", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { MaskG, Rdq }, 0 },
},
{
- /* VEX_W_0F3ACE_P_2 */
+ /* MOD_VEX_0F92_P_3_LEN_0 */
{ Bad_Opcode },
- { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
+ { "kmovK", { MaskG, Rdq }, 0 },
},
{
- /* VEX_W_0F3ACF_P_2 */
+ /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
{ Bad_Opcode },
- { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
+ { "kmovw", { Gdq, MaskR }, 0 },
},
{
- /* VEX_W_0F3ADF_P_2 */
- { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
+ /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { Gdq, MaskR }, 0 },
},
-#define NEED_VEX_W_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_VEX_W_TABLE
-};
-
-static const struct dis386 mod_table[][2] = {
{
- /* MOD_8D */
- { "leaS", { Gv, M }, 0 },
+ /* MOD_VEX_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovK", { Gdq, MaskR }, 0 },
},
{
- /* MOD_C6_REG_7 */
+ /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
{ Bad_Opcode },
- { RM_TABLE (RM_C6_REG_7) },
+ { "kortestw", { MaskG, MaskR }, 0 },
},
{
- /* MOD_C7_REG_7 */
+ /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
{ Bad_Opcode },
- { RM_TABLE (RM_C7_REG_7) },
+ { "kortestq", { MaskG, MaskR }, 0 },
},
{
- /* MOD_FF_REG_3 */
- { "Jcall^", { indirEp }, 0 },
+ /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestb", { MaskG, MaskR }, 0 },
},
{
- /* MOD_FF_REG_5 */
- { "Jjmp^", { indirEp }, 0 },
+ /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestd", { MaskG, MaskR }, 0 },
},
{
- /* MOD_0F01_REG_0 */
- { X86_64_TABLE (X86_64_0F01_REG_0) },
- { RM_TABLE (RM_0F01_REG_0) },
- },
- {
- /* MOD_0F01_REG_1 */
- { X86_64_TABLE (X86_64_0F01_REG_1) },
- { RM_TABLE (RM_0F01_REG_1) },
- },
- {
- /* MOD_0F01_REG_2 */
- { X86_64_TABLE (X86_64_0F01_REG_2) },
- { RM_TABLE (RM_0F01_REG_2) },
- },
- {
- /* MOD_0F01_REG_3 */
- { X86_64_TABLE (X86_64_0F01_REG_3) },
- { RM_TABLE (RM_0F01_REG_3) },
- },
- {
- /* MOD_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
- { RM_TABLE (RM_0F01_REG_5) },
- },
- {
- /* MOD_0F01_REG_7 */
- { "invlpg", { Mb }, 0 },
- { RM_TABLE (RM_0F01_REG_7) },
+ /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "ktestw", { MaskG, MaskR }, 0 },
},
{
- /* MOD_0F12_PREFIX_0 */
- { "movlps", { XM, EXq }, PREFIX_OPCODE },
- { "movhlps", { XM, EXq }, PREFIX_OPCODE },
+ /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "ktestq", { MaskG, MaskR }, 0 },
},
{
- /* MOD_0F13 */
- { "movlpX", { EXq, XM }, PREFIX_OPCODE },
+ /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "ktestb", { MaskG, MaskR }, 0 },
},
{
- /* MOD_0F16_PREFIX_0 */
- { "movhps", { XM, EXq }, 0 },
- { "movlhps", { XM, EXq }, 0 },
+ /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "ktestd", { MaskG, MaskR }, 0 },
},
{
- /* MOD_0F17 */
- { "movhpX", { EXq, XM }, PREFIX_OPCODE },
+ /* MOD_VEX_0FAE_REG_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
},
{
- /* MOD_0F18_REG_0 */
- { "prefetchnta", { Mb }, 0 },
+ /* MOD_VEX_0FAE_REG_3 */
+ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
},
{
- /* MOD_0F18_REG_1 */
- { "prefetcht0", { Mb }, 0 },
+ /* MOD_VEX_0FD7_PREFIX_2 */
+ { Bad_Opcode },
+ { "vpmovmskb", { Gdq, XS }, 0 },
},
{
- /* MOD_0F18_REG_2 */
- { "prefetcht1", { Mb }, 0 },
+ /* MOD_VEX_0FE7_PREFIX_2 */
+ { "vmovntdq", { Mx, XM }, 0 },
},
{
- /* MOD_0F18_REG_3 */
- { "prefetcht2", { Mb }, 0 },
+ /* MOD_VEX_0FF0_PREFIX_3 */
+ { "vlddqu", { XM, M }, 0 },
},
{
- /* MOD_0F18_REG_4 */
- { "nop/reserved", { Mb }, 0 },
+ /* MOD_VEX_0F381A_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
},
{
- /* MOD_0F18_REG_5 */
- { "nop/reserved", { Mb }, 0 },
+ /* MOD_VEX_0F382A_PREFIX_2 */
+ { "vmovntdqa", { XM, Mx }, 0 },
},
{
- /* MOD_0F18_REG_6 */
- { "nop/reserved", { Mb }, 0 },
+ /* MOD_VEX_0F382C_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
},
{
- /* MOD_0F18_REG_7 */
- { "nop/reserved", { Mb }, 0 },
+ /* MOD_VEX_0F382D_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
},
{
- /* MOD_0F1A_PREFIX_0 */
- { "bndldx", { Gbnd, Mv_bnd }, 0 },
- { "nopQ", { Ev }, 0 },
+ /* MOD_VEX_0F382E_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
},
{
- /* MOD_0F1B_PREFIX_0 */
- { "bndstx", { Mv_bnd, Gbnd }, 0 },
- { "nopQ", { Ev }, 0 },
+ /* MOD_VEX_0F382F_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
},
{
- /* MOD_0F1B_PREFIX_1 */
- { "bndmk", { Gbnd, Mv_bnd }, 0 },
- { "nopQ", { Ev }, 0 },
+ /* MOD_VEX_0F385A_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
},
{
- /* MOD_0F1C_PREFIX_0 */
- { REG_TABLE (REG_0F1C_MOD_0) },
- { "nopQ", { Ev }, 0 },
+ /* MOD_VEX_0F388C_PREFIX_2 */
+ { "vpmaskmov%DQ", { XM, Vex, Mx }, 0 },
},
{
- /* MOD_0F1E_PREFIX_1 */
- { "nopQ", { Ev }, 0 },
- { REG_TABLE (REG_0F1E_MOD_3) },
+ /* MOD_VEX_0F388E_PREFIX_2 */
+ { "vpmaskmov%DQ", { Mx, Vex, XM }, 0 },
},
{
- /* MOD_0F24 */
+ /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
{ Bad_Opcode },
- { "movL", { Rd, Td }, 0 },
+ { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F26 */
+ /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
{ Bad_Opcode },
- { "movL", { Td, Rd }, 0 },
- },
- {
- /* MOD_0F2B_PREFIX_0 */
- {"movntps", { Mx, XM }, PREFIX_OPCODE },
- },
- {
- /* MOD_0F2B_PREFIX_1 */
- {"movntss", { Md, XM }, PREFIX_OPCODE },
- },
- {
- /* MOD_0F2B_PREFIX_2 */
- {"movntpd", { Mx, XM }, PREFIX_OPCODE },
- },
- {
- /* MOD_0F2B_PREFIX_3 */
- {"movntsd", { Mq, XM }, PREFIX_OPCODE },
+ { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F51 */
+ /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
{ Bad_Opcode },
- { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
+ { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F71_REG_2 */
+ /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
{ Bad_Opcode },
- { "psrlw", { MS, Ib }, 0 },
+ { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F71_REG_4 */
+ /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
{ Bad_Opcode },
- { "psraw", { MS, Ib }, 0 },
+ { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F71_REG_6 */
+ /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
{ Bad_Opcode },
- { "psllw", { MS, Ib }, 0 },
+ { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F72_REG_2 */
+ /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
{ Bad_Opcode },
- { "psrld", { MS, Ib }, 0 },
+ { "kshiftld", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F72_REG_4 */
+ /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
{ Bad_Opcode },
- { "psrad", { MS, Ib }, 0 },
+ { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
},
{
- /* MOD_0F72_REG_6 */
+ /* MOD_VEX_0FXOP_09_12 */
{ Bad_Opcode },
- { "pslld", { MS, Ib }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
},
+
+#include "i386-dis-evex-mod.h"
+};
+
+static const struct dis386 rm_table[][8] = {
{
- /* MOD_0F73_REG_2 */
- { Bad_Opcode },
- { "psrlq", { MS, Ib }, 0 },
+ /* RM_C6_REG_7 */
+ { "xabort", { Skip_MODRM, Ib }, 0 },
},
{
- /* MOD_0F73_REG_3 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F73_REG_3) },
+ /* RM_C7_REG_7 */
+ { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
},
{
- /* MOD_0F73_REG_6 */
- { Bad_Opcode },
- { "psllq", { MS, Ib }, 0 },
+ /* RM_0F01_REG_0 */
+ { "enclv", { Skip_MODRM }, 0 },
+ { "vmcall", { Skip_MODRM }, 0 },
+ { "vmlaunch", { Skip_MODRM }, 0 },
+ { "vmresume", { Skip_MODRM }, 0 },
+ { "vmxoff", { Skip_MODRM }, 0 },
+ { "pconfig", { Skip_MODRM }, 0 },
},
{
- /* MOD_0F73_REG_7 */
+ /* RM_0F01_REG_1 */
+ { "monitor", { { OP_Monitor, 0 } }, 0 },
+ { "mwait", { { OP_Mwait, 0 } }, 0 },
+ { "clac", { Skip_MODRM }, 0 },
+ { "stac", { Skip_MODRM }, 0 },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F73_REG_7) },
- },
- {
- /* MOD_0FAE_REG_0 */
- { "fxsave", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
- },
- {
- /* MOD_0FAE_REG_1 */
- { "fxrstor", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
- },
- {
- /* MOD_0FAE_REG_2 */
- { "ldmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
- },
- {
- /* MOD_0FAE_REG_3 */
- { "stmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
- },
- {
- /* MOD_0FAE_REG_4 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
- },
- {
- /* MOD_0FAE_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
- },
- {
- /* MOD_0FAE_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "encls", { Skip_MODRM }, 0 },
},
{
- /* MOD_0FAE_REG_7 */
- { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
- { RM_TABLE (RM_0FAE_REG_7) },
+ /* RM_0F01_REG_2 */
+ { "xgetbv", { Skip_MODRM }, 0 },
+ { "xsetbv", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vmfunc", { Skip_MODRM }, 0 },
+ { "xend", { Skip_MODRM }, 0 },
+ { "xtest", { Skip_MODRM }, 0 },
+ { "enclu", { Skip_MODRM }, 0 },
},
{
- /* MOD_0FB2 */
- { "lssS", { Gv, Mp }, 0 },
+ /* RM_0F01_REG_3 */
+ { "vmrun", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
+ { "vmload", { Skip_MODRM }, 0 },
+ { "vmsave", { Skip_MODRM }, 0 },
+ { "stgi", { Skip_MODRM }, 0 },
+ { "clgi", { Skip_MODRM }, 0 },
+ { "skinit", { Skip_MODRM }, 0 },
+ { "invlpga", { Skip_MODRM }, 0 },
},
{
- /* MOD_0FB4 */
- { "lfsS", { Gv, Mp }, 0 },
+ /* RM_0F01_REG_5_MOD_3 */
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "rdpkru", { Skip_MODRM }, 0 },
+ { "wrpkru", { Skip_MODRM }, 0 },
},
{
- /* MOD_0FB5 */
- { "lgsS", { Gv, Mp }, 0 },
+ /* RM_0F01_REG_7_MOD_3 */
+ { "swapgs", { Skip_MODRM }, 0 },
+ { "rdtscp", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
+ { "clzero", { Skip_MODRM }, 0 },
+ { "rdpru", { Skip_MODRM }, 0 },
},
{
- /* MOD_0FC3 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
+ /* RM_0F1E_P_1_MOD_3_REG_7 */
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
+ { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
},
{
- /* MOD_0FC7_REG_3 */
- { "xrstors", { FXSAVE }, 0 },
+ /* RM_0FAE_REG_6_MOD_3 */
+ { "mfence", { Skip_MODRM }, 0 },
},
{
- /* MOD_0FC7_REG_4 */
- { "xsavec", { FXSAVE }, 0 },
+ /* RM_0FAE_REG_7_MOD_3 */
+ { "sfence", { Skip_MODRM }, 0 },
+
},
{
- /* MOD_0FC7_REG_5 */
- { "xsaves", { FXSAVE }, 0 },
- },
- {
- /* MOD_0FC7_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
- },
- {
- /* MOD_0FC7_REG_7 */
- { "vmptrst", { Mq }, 0 },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
- },
- {
- /* MOD_0FD7 */
- { Bad_Opcode },
- { "pmovmskb", { Gdq, MS }, 0 },
- },
- {
- /* MOD_0FE7_PREFIX_2 */
- { "movntdq", { Mx, XM }, 0 },
- },
- {
- /* MOD_0FF0_PREFIX_3 */
- { "lddqu", { XM, M }, 0 },
- },
- {
- /* MOD_0F382A_PREFIX_2 */
- { "movntdqa", { XM, Mx }, 0 },
- },
- {
- /* MOD_0F38F5_PREFIX_2 */
- { "wrussK", { M, Gdq }, PREFIX_OPCODE },
- },
- {
- /* MOD_0F38F6_PREFIX_0 */
- { "wrssK", { M, Gdq }, PREFIX_OPCODE },
- },
- {
- /* MOD_0F38F8_PREFIX_2 */
- { "movdir64b", { Gva, M }, PREFIX_OPCODE },
- },
- {
- /* MOD_0F38F9_PREFIX_0 */
- { "movdiri", { Em, Gv }, PREFIX_OPCODE },
- },
- {
- /* MOD_62_32BIT */
- { "bound{S|}", { Gv, Ma }, 0 },
- { EVEX_TABLE (EVEX_0F) },
- },
- {
- /* MOD_C4_32BIT */
- { "lesS", { Gv, Mp }, 0 },
- { VEX_C4_TABLE (VEX_0F) },
- },
- {
- /* MOD_C5_32BIT */
- { "ldsS", { Gv, Mp }, 0 },
- { VEX_C5_TABLE (VEX_0F) },
- },
- {
- /* MOD_VEX_0F12_PREFIX_0 */
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
- },
- {
- /* MOD_VEX_0F13 */
- { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
- },
- {
- /* MOD_VEX_0F16_PREFIX_0 */
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
- },
- {
- /* MOD_VEX_0F17 */
- { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
- },
- {
- /* MOD_VEX_0F2B */
- { VEX_W_TABLE (VEX_W_0F2B_M_0) },
- },
- {
- /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
- { Bad_Opcode },
- { "kandw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
- { Bad_Opcode },
- { "kandq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
- { Bad_Opcode },
- { "kandb", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
- { Bad_Opcode },
- { "kandd", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
- { Bad_Opcode },
- { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
- { Bad_Opcode },
- { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
- { Bad_Opcode },
- { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
- { Bad_Opcode },
- { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
- { Bad_Opcode },
- { "knotw", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
- { Bad_Opcode },
- { "knotq", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
- { Bad_Opcode },
- { "knotb", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
- { Bad_Opcode },
- { "knotd", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
- { Bad_Opcode },
- { "korw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
- { Bad_Opcode },
- { "korq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
- { Bad_Opcode },
- { "korb", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
- { Bad_Opcode },
- { "kord", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
- { Bad_Opcode },
- { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
- { Bad_Opcode },
- { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
- { Bad_Opcode },
- { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
- { Bad_Opcode },
- { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
- { Bad_Opcode },
- { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
- { Bad_Opcode },
- { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
- { Bad_Opcode },
- { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
- { Bad_Opcode },
- { "kxord", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
- { Bad_Opcode },
- { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
- { Bad_Opcode },
- { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
- { Bad_Opcode },
- { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
- { Bad_Opcode },
- { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
- { Bad_Opcode },
- { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
- { Bad_Opcode },
- { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
- { Bad_Opcode },
- { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
- },
- {
- /* MOD_VEX_0F50 */
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F50_M_0) },
- },
- {
- /* MOD_VEX_0F71_REG_2 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
- },
- {
- /* MOD_VEX_0F71_REG_4 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
- },
- {
- /* MOD_VEX_0F71_REG_6 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
- },
- {
- /* MOD_VEX_0F72_REG_2 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
- },
- {
- /* MOD_VEX_0F72_REG_4 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
- },
- {
- /* MOD_VEX_0F72_REG_6 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
- },
- {
- /* MOD_VEX_0F73_REG_2 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
- },
- {
- /* MOD_VEX_0F73_REG_3 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
- },
- {
- /* MOD_VEX_0F73_REG_6 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
- },
- {
- /* MOD_VEX_0F73_REG_7 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
- },
- {
- /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
- { "kmovw", { Ew, MaskG }, 0 },
- { Bad_Opcode },
- },
- {
- /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
- { "kmovq", { Eq, MaskG }, 0 },
- { Bad_Opcode },
- },
- {
- /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
- { "kmovb", { Eb, MaskG }, 0 },
- { Bad_Opcode },
- },
- {
- /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
- { "kmovd", { Ed, MaskG }, 0 },
- { Bad_Opcode },
- },
- {
- /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
- { Bad_Opcode },
- { "kmovw", { MaskG, Rdq }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
- { Bad_Opcode },
- { "kmovb", { MaskG, Rdq }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
- { Bad_Opcode },
- { "kmovd", { MaskG, Rdq }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
- { Bad_Opcode },
- { "kmovq", { MaskG, Rdq }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
- { Bad_Opcode },
- { "kmovw", { Gdq, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
- { Bad_Opcode },
- { "kmovb", { Gdq, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
- { Bad_Opcode },
- { "kmovd", { Gdq, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
- { Bad_Opcode },
- { "kmovq", { Gdq, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
- { Bad_Opcode },
- { "kortestw", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
- { Bad_Opcode },
- { "kortestq", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
- { Bad_Opcode },
- { "kortestb", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
- { Bad_Opcode },
- { "kortestd", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
- { Bad_Opcode },
- { "ktestw", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
- { Bad_Opcode },
- { "ktestq", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
- { Bad_Opcode },
- { "ktestb", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
- { Bad_Opcode },
- { "ktestd", { MaskG, MaskR }, 0 },
- },
- {
- /* MOD_VEX_0FAE_REG_2 */
- { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
- },
- {
- /* MOD_VEX_0FAE_REG_3 */
- { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
- },
- {
- /* MOD_VEX_0FD7_PREFIX_2 */
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
- },
- {
- /* MOD_VEX_0FE7_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
- },
- {
- /* MOD_VEX_0FF0_PREFIX_3 */
- { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
- },
- {
- /* MOD_VEX_0F381A_PREFIX_2 */
- { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F382A_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F382C_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F382D_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F382E_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F382F_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F385A_PREFIX_2 */
- { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F388C_PREFIX_2 */
- { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
- },
- {
- /* MOD_VEX_0F388E_PREFIX_2 */
- { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftld", { MaskG, MaskR, Ib }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
- { Bad_Opcode },
- { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
- },
-#define NEED_MOD_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_MOD_TABLE
-};
-
-static const struct dis386 rm_table[][8] = {
- {
- /* RM_C6_REG_7 */
- { "xabort", { Skip_MODRM, Ib }, 0 },
- },
- {
- /* RM_C7_REG_7 */
- { "xbeginT", { Skip_MODRM, Jv }, 0 },
- },
- {
- /* RM_0F01_REG_0 */
- { Bad_Opcode },
- { "vmcall", { Skip_MODRM }, 0 },
- { "vmlaunch", { Skip_MODRM }, 0 },
- { "vmresume", { Skip_MODRM }, 0 },
- { "vmxoff", { Skip_MODRM }, 0 },
- { "pconfig", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0F01_REG_1 */
- { "monitor", { { OP_Monitor, 0 } }, 0 },
- { "mwait", { { OP_Mwait, 0 } }, 0 },
- { "clac", { Skip_MODRM }, 0 },
- { "stac", { Skip_MODRM }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { "encls", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0F01_REG_2 */
- { "xgetbv", { Skip_MODRM }, 0 },
- { "xsetbv", { Skip_MODRM }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { "vmfunc", { Skip_MODRM }, 0 },
- { "xend", { Skip_MODRM }, 0 },
- { "xtest", { Skip_MODRM }, 0 },
- { "enclu", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0F01_REG_3 */
- { "vmrun", { Skip_MODRM }, 0 },
- { "vmmcall", { Skip_MODRM }, 0 },
- { "vmload", { Skip_MODRM }, 0 },
- { "vmsave", { Skip_MODRM }, 0 },
- { "stgi", { Skip_MODRM }, 0 },
- { "clgi", { Skip_MODRM }, 0 },
- { "skinit", { Skip_MODRM }, 0 },
- { "invlpga", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { "rdpkru", { Skip_MODRM }, 0 },
- { "wrpkru", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0F01_REG_7 */
- { "swapgs", { Skip_MODRM }, 0 },
- { "rdtscp", { Skip_MODRM }, 0 },
- { "monitorx", { { OP_Monitor, 0 } }, 0 },
- { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
- { "clzero", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0F1E_MOD_3_REG_7 */
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
- { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- },
- {
- /* RM_0FAE_REG_6 */
- { "mfence", { Skip_MODRM }, 0 },
- },
- {
- /* RM_0FAE_REG_7 */
- { "sfence", { Skip_MODRM }, 0 },
-
+ /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
},
};
#define BND_PREFIX (0xf2 | 0x400)
#define NOTRACK_PREFIX (0x3e | 0x100)
+/* Remember if the current op is a jump instruction. */
+static bfd_boolean op_is_jump = FALSE;
+
static int
ckprefix (void)
{
int newrex, i, length;
rex = 0;
- rex_ignored = 0;
prefixes = 0;
used_prefixes = 0;
rex_used = 0;
enum x86_64_isa
{
- amd64 = 0,
+ amd64 = 1,
intel64
};
dp = &vex_len_table[dp->op[1].bytemode][vindex];
break;
+ case USE_EVEX_LEN_TABLE:
+ if (!vex.evex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ vindex = 0;
+ break;
+ case 256:
+ vindex = 1;
+ break;
+ case 512:
+ vindex = 2;
+ break;
+ default:
+ abort ();
+ break;
+ }
+
+ dp = &evex_len_table[dp->op[1].bytemode][vindex];
+ break;
+
case USE_XOP_8F_TABLE:
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
/* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
break;
}
need_vex = 1;
- need_vex_reg = 1;
codep++;
vindex = *codep++;
dp = &xop_table[vex_table_index][vindex];
modrm.mod = (*codep >> 6) & 3;
modrm.reg = (*codep >> 3) & 7;
modrm.rm = *codep & 7;
+
+ /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
+ having to decode the bits for every otherwise valid encoding. */
+ if (vex.prefix)
+ return &bad_opcode;
break;
case USE_VEX_C4_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
switch ((*codep & 0x1f))
{
vex_table_index = VEX_0F;
break;
case 0x2:
- vex_table_index = VEX_0F38;
- break;
- case 0x3:
- vex_table_index = VEX_0F3A;
- break;
- }
- codep++;
- vex.w = *codep & 0x80;
- if (address_mode == mode_64bit)
- {
- if (vex.w)
- rex |= REX_W;
- }
- else
- {
- /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
- is ignored, other REX bits are 0 and the highest bit in
- VEX.vvvv is also ignored (but we mustn't clear it here). */
- rex = 0;
- }
- vex.register_specifier = (~(*codep >> 3)) & 0xf;
- vex.length = (*codep & 0x4) ? 256 : 128;
- switch ((*codep & 0x3))
- {
- case 0:
- break;
- case 1:
- vex.prefix = DATA_PREFIX_OPCODE;
- break;
- case 2:
- vex.prefix = REPE_PREFIX_OPCODE;
- break;
- case 3:
- vex.prefix = REPNE_PREFIX_OPCODE;
- break;
- }
- need_vex = 1;
- need_vex_reg = 1;
- codep++;
- vindex = *codep++;
- dp = &vex_table[vex_table_index][vindex];
- end_codep = codep;
- /* There is no MODRM byte for VEX0F 77. */
- if (vex_table_index != VEX_0F || vindex != 0x77)
- {
- FETCH_DATA (info, codep + 1);
- modrm.mod = (*codep >> 6) & 3;
- modrm.reg = (*codep >> 3) & 7;
- modrm.rm = *codep & 7;
- }
- break;
-
- case USE_VEX_C5_TABLE:
- /* VEX prefix. */
- FETCH_DATA (info, codep + 2);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
- rex = (*codep & 0x80) ? 0 : REX_R;
-
- /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
- VEX.vvvv is 1. */
- vex.register_specifier = (~(*codep >> 3)) & 0xf;
- vex.length = (*codep & 0x4) ? 256 : 128;
- switch ((*codep & 0x3))
- {
- case 0:
- break;
- case 1:
- vex.prefix = DATA_PREFIX_OPCODE;
- break;
- case 2:
- vex.prefix = REPE_PREFIX_OPCODE;
- break;
- case 3:
- vex.prefix = REPNE_PREFIX_OPCODE;
- break;
- }
- need_vex = 1;
- need_vex_reg = 1;
- codep++;
- vindex = *codep++;
- dp = &vex_table[dp->op[1].bytemode][vindex];
- end_codep = codep;
- /* There is no MODRM byte for VEX 77. */
- if (vindex != 0x77)
- {
- FETCH_DATA (info, codep + 1);
- modrm.mod = (*codep >> 6) & 3;
- modrm.reg = (*codep >> 3) & 7;
- modrm.rm = *codep & 7;
- }
- break;
-
- case USE_VEX_W_TABLE:
- if (!need_vex)
- abort ();
-
- dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
- break;
-
- case USE_EVEX_TABLE:
- two_source_ops = 0;
- /* EVEX prefix. */
- vex.evex = 1;
- FETCH_DATA (info, codep + 4);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
- /* The first byte after 0x62. */
- rex = ~(*codep >> 5) & 0x7;
- vex.r = *codep & 0x10;
- switch ((*codep & 0xf))
- {
- default:
- return &bad_opcode;
- case 0x1:
- vex_table_index = EVEX_0F;
- break;
- case 0x2:
- vex_table_index = EVEX_0F38;
+ vex_table_index = VEX_0F38;
break;
case 0x3:
- vex_table_index = EVEX_0F3A;
+ vex_table_index = VEX_0F3A;
break;
}
-
- /* The second byte after 0x62. */
codep++;
vex.w = *codep & 0x80;
- if (vex.w && address_mode == mode_64bit)
- rex |= REX_W;
-
+ if (address_mode == mode_64bit)
+ {
+ if (vex.w)
+ rex |= REX_W;
+ }
+ else
+ {
+ /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
+ is ignored, other REX bits are 0 and the highest bit in
+ VEX.vvvv is also ignored (but we mustn't clear it here). */
+ rex = 0;
+ }
vex.register_specifier = (~(*codep >> 3)) & 0xf;
-
- /* The U bit. */
- if (!(*codep & 0x4))
- return &bad_opcode;
-
+ vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
case 0:
vex.prefix = REPNE_PREFIX_OPCODE;
break;
}
-
- /* The third byte after 0x62. */
- codep++;
-
- /* Remember the static rounding bits. */
- vex.ll = (*codep >> 5) & 3;
- vex.b = (*codep & 0x10) != 0;
-
- vex.v = *codep & 0x8;
- vex.mask_register_specifier = *codep & 0x7;
- vex.zeroing = *codep & 0x80;
-
- if (address_mode != mode_64bit)
- {
- /* In 16/32-bit mode silently ignore following bits. */
- rex &= ~REX_B;
- vex.r = 1;
- vex.v = 1;
- }
-
need_vex = 1;
- need_vex_reg = 1;
codep++;
vindex = *codep++;
- dp = &evex_table[vex_table_index][vindex];
+ dp = &vex_table[vex_table_index][vindex];
end_codep = codep;
- FETCH_DATA (info, codep + 1);
- modrm.mod = (*codep >> 6) & 3;
- modrm.reg = (*codep >> 3) & 7;
- modrm.rm = *codep & 7;
-
- /* Set vector length. */
- if (modrm.mod == 3 && vex.b)
- vex.length = 512;
- else
- {
- switch (vex.ll)
- {
- case 0x0:
- vex.length = 128;
- break;
- case 0x1:
- vex.length = 256;
- break;
- case 0x2:
- vex.length = 512;
- break;
- default:
- return &bad_opcode;
- }
- }
- break;
-
- case 0:
- dp = &bad_opcode;
- break;
-
- default:
- abort ();
- }
-
- if (dp->name != NULL)
- return dp;
- else
- return get_valid_dis386 (dp, info);
-}
-
-static void
-get_sib (disassemble_info *info, int sizeflag)
-{
- /* If modrm.mod == 3, operand must be register. */
- if (need_modrm
- && ((sizeflag & AFLAG) || address_mode == mode_64bit)
- && modrm.mod != 3
- && modrm.rm == 4)
- {
- FETCH_DATA (info, codep + 2);
- sib.index = (codep [1] >> 3) & 7;
- sib.scale = (codep [1] >> 6) & 3;
- sib.base = codep [1] & 7;
- }
-}
-
-static int
-print_insn (bfd_vma pc, disassemble_info *info)
-{
- const struct dis386 *dp;
- int i;
- char *op_txt[MAX_OPERANDS];
- int needcomma;
- int sizeflag, orig_sizeflag;
- const char *p;
- struct dis_private priv;
- int prefix_length;
-
- priv.orig_sizeflag = AFLAG | DFLAG;
- if ((info->mach & bfd_mach_i386_i386) != 0)
- address_mode = mode_32bit;
- else if (info->mach == bfd_mach_i386_i8086)
- {
- address_mode = mode_16bit;
- priv.orig_sizeflag = 0;
- }
- else
- address_mode = mode_64bit;
-
- if (intel_syntax == (char) -1)
- intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
-
- for (p = info->disassembler_options; p != NULL; )
- {
- if (CONST_STRNEQ (p, "amd64"))
- isa64 = amd64;
- else if (CONST_STRNEQ (p, "intel64"))
- isa64 = intel64;
- else if (CONST_STRNEQ (p, "x86-64"))
- {
- address_mode = mode_64bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
- }
- else if (CONST_STRNEQ (p, "i386"))
- {
- address_mode = mode_32bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
- }
- else if (CONST_STRNEQ (p, "i8086"))
- {
- address_mode = mode_16bit;
- priv.orig_sizeflag = 0;
- }
- else if (CONST_STRNEQ (p, "intel"))
- {
- intel_syntax = 1;
- if (CONST_STRNEQ (p + 5, "-mnemonic"))
- intel_mnemonic = 1;
- }
- else if (CONST_STRNEQ (p, "att"))
- {
- intel_syntax = 0;
- if (CONST_STRNEQ (p + 3, "-mnemonic"))
- intel_mnemonic = 0;
- }
- else if (CONST_STRNEQ (p, "addr"))
- {
- if (address_mode == mode_64bit)
- {
- if (p[4] == '3' && p[5] == '2')
- priv.orig_sizeflag &= ~AFLAG;
- else if (p[4] == '6' && p[5] == '4')
- priv.orig_sizeflag |= AFLAG;
- }
- else
- {
- if (p[4] == '1' && p[5] == '6')
- priv.orig_sizeflag &= ~AFLAG;
- else if (p[4] == '3' && p[5] == '2')
- priv.orig_sizeflag |= AFLAG;
- }
- }
- else if (CONST_STRNEQ (p, "data"))
+ /* There is no MODRM byte for VEX0F 77. */
+ if (vex_table_index != VEX_0F || vindex != 0x77)
{
- if (p[4] == '1' && p[5] == '6')
- priv.orig_sizeflag &= ~DFLAG;
- else if (p[4] == '3' && p[5] == '2')
- priv.orig_sizeflag |= DFLAG;
- }
- else if (CONST_STRNEQ (p, "suffix"))
- priv.orig_sizeflag |= SUFFIX_ALWAYS;
-
- p = strchr (p, ',');
- if (p != NULL)
- p++;
- }
-
- if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
- {
- (*info->fprintf_func) (info->stream,
- _("64-bit address is disabled"));
- return -1;
- }
-
- if (intel_syntax)
- {
- names64 = intel_names64;
- names32 = intel_names32;
- names16 = intel_names16;
- names8 = intel_names8;
- names8rex = intel_names8rex;
- names_seg = intel_names_seg;
- names_mm = intel_names_mm;
- names_bnd = intel_names_bnd;
- names_xmm = intel_names_xmm;
- names_ymm = intel_names_ymm;
- names_zmm = intel_names_zmm;
- index64 = intel_index64;
- index32 = intel_index32;
- names_mask = intel_names_mask;
- index16 = intel_index16;
- open_char = '[';
- close_char = ']';
- separator_char = '+';
- scale_char = '*';
- }
- else
- {
- names64 = att_names64;
- names32 = att_names32;
- names16 = att_names16;
- names8 = att_names8;
- names8rex = att_names8rex;
- names_seg = att_names_seg;
- names_mm = att_names_mm;
- names_bnd = att_names_bnd;
- names_xmm = att_names_xmm;
- names_ymm = att_names_ymm;
- names_zmm = att_names_zmm;
- index64 = att_index64;
- index32 = att_index32;
- names_mask = att_names_mask;
- index16 = att_index16;
- open_char = '(';
- close_char = ')';
- separator_char = ',';
- scale_char = ',';
- }
-
- /* The output looks better if we put 7 bytes on a line, since that
- puts most long word instructions on a single line. Use 8 bytes
- for Intel L1OM. */
- if ((info->mach & bfd_mach_l1om) != 0)
- info->bytes_per_line = 8;
- else
- info->bytes_per_line = 7;
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+ break;
- info->private_data = &priv;
- priv.max_fetched = priv.the_buffer;
- priv.insn_start = pc;
+ case USE_VEX_C5_TABLE:
+ /* VEX prefix. */
+ FETCH_DATA (info, codep + 2);
+ rex = (*codep & 0x80) ? 0 : REX_R;
- obuf[0] = 0;
- for (i = 0; i < MAX_OPERANDS; ++i)
- {
- op_out[i][0] = 0;
- op_index[i] = -1;
- }
+ /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
+ VEX.vvvv is 1. */
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ vex.length = (*codep & 0x4) ? 256 : 128;
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+ need_vex = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &vex_table[dp->op[1].bytemode][vindex];
+ end_codep = codep;
+ /* There is no MODRM byte for VEX 77. */
+ if (vindex != 0x77)
+ {
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+ break;
- the_info = info;
- start_pc = pc;
- start_codep = priv.the_buffer;
- codep = priv.the_buffer;
+ case USE_VEX_W_TABLE:
+ if (!need_vex)
+ abort ();
- if (OPCODES_SIGSETJMP (priv.bailout) != 0)
- {
- const char *name;
+ dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
+ break;
- /* Getting here means we tried for data but didn't get it. That
- means we have an incomplete instruction of some sort. Just
- print the first byte as a prefix or a .byte pseudo-op. */
- if (codep > priv.the_buffer)
+ case USE_EVEX_TABLE:
+ two_source_ops = 0;
+ /* EVEX prefix. */
+ vex.evex = 1;
+ FETCH_DATA (info, codep + 4);
+ /* The first byte after 0x62. */
+ rex = ~(*codep >> 5) & 0x7;
+ vex.r = *codep & 0x10;
+ switch ((*codep & 0xf))
{
- name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
- if (name != NULL)
- (*info->fprintf_func) (info->stream, "%s", name);
- else
- {
- /* Just print the first byte as a .byte instruction. */
- (*info->fprintf_func) (info->stream, ".byte 0x%x",
- (unsigned int) priv.the_buffer[0]);
- }
-
- return 1;
+ default:
+ return &bad_opcode;
+ case 0x1:
+ vex_table_index = EVEX_0F;
+ break;
+ case 0x2:
+ vex_table_index = EVEX_0F38;
+ break;
+ case 0x3:
+ vex_table_index = EVEX_0F3A;
+ break;
}
- return -1;
- }
-
- obufp = obuf;
- sizeflag = priv.orig_sizeflag;
+ /* The second byte after 0x62. */
+ codep++;
+ vex.w = *codep & 0x80;
+ if (vex.w && address_mode == mode_64bit)
+ rex |= REX_W;
- if (!ckprefix () || rex_used)
- {
- /* Too many prefixes or unused REX prefixes. */
- for (i = 0;
- i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
- i++)
- (*info->fprintf_func) (info->stream, "%s%s",
- i == 0 ? "" : " ",
- prefix_name (all_prefixes[i], sizeflag));
- return i;
- }
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
- insn_codep = codep;
+ /* The U bit. */
+ if (!(*codep & 0x4))
+ return &bad_opcode;
- FETCH_DATA (info, codep + 1);
- two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
- if (((prefixes & PREFIX_FWAIT)
- && ((*codep < 0xd8) || (*codep > 0xdf))))
- {
- /* Handle prefixes before fwait. */
- for (i = 0; i < fwait_prefix && all_prefixes[i];
- i++)
- (*info->fprintf_func) (info->stream, "%s ",
- prefix_name (all_prefixes[i], sizeflag));
- (*info->fprintf_func) (info->stream, "fwait");
- return i + 1;
- }
+ /* The third byte after 0x62. */
+ codep++;
- if (*codep == 0x0f)
- {
- unsigned char threebyte;
+ /* Remember the static rounding bits. */
+ vex.ll = (*codep >> 5) & 3;
+ vex.b = (*codep & 0x10) != 0;
- codep++;
- FETCH_DATA (info, codep + 1);
- threebyte = *codep;
- dp = &dis386_twobyte[threebyte];
- need_modrm = twobyte_has_modrm[*codep];
- codep++;
- }
- else
- {
- dp = &dis386[*codep];
- need_modrm = onebyte_has_modrm[*codep];
- codep++;
- }
+ vex.v = *codep & 0x8;
+ vex.mask_register_specifier = *codep & 0x7;
+ vex.zeroing = *codep & 0x80;
- /* Save sizeflag for printing the extra prefixes later before updating
- it for mnemonic and operand processing. The prefix names depend
- only on the address mode. */
- orig_sizeflag = sizeflag;
- if (prefixes & PREFIX_ADDR)
- sizeflag ^= AFLAG;
- if ((prefixes & PREFIX_DATA))
- sizeflag ^= DFLAG;
+ if (address_mode != mode_64bit)
+ {
+ /* In 16/32-bit mode silently ignore following bits. */
+ rex &= ~REX_B;
+ vex.r = 1;
+ vex.v = 1;
+ }
- end_codep = codep;
- if (need_modrm)
- {
+ need_vex = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &evex_table[vex_table_index][vindex];
+ end_codep = codep;
FETCH_DATA (info, codep + 1);
modrm.mod = (*codep >> 6) & 3;
modrm.reg = (*codep >> 3) & 7;
modrm.rm = *codep & 7;
- }
- need_vex = 0;
- need_vex_reg = 0;
- vex_w_done = 0;
- memset (&vex, 0, sizeof (vex));
-
- if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
- {
- get_sib (info, sizeflag);
- dofloat (sizeflag);
- }
- else
- {
- dp = get_valid_dis386 (dp, info);
- if (dp != NULL && putop (dp->name, sizeflag) == 0)
+ /* Set vector length. */
+ if (modrm.mod == 3 && vex.b)
+ vex.length = 512;
+ else
{
- get_sib (info, sizeflag);
- for (i = 0; i < MAX_OPERANDS; ++i)
+ switch (vex.ll)
{
- obufp = op_out[i];
- op_ad = MAX_OPERANDS - 1 - i;
- if (dp->op[i].rtn)
- (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
- /* For EVEX instruction after the last operand masking
- should be printed. */
- if (i == 0 && vex.evex)
- {
- /* Don't print {%k0}. */
- if (vex.mask_register_specifier)
- {
- oappend ("{");
- oappend (names_mask[vex.mask_register_specifier]);
- oappend ("}");
- }
- if (vex.zeroing)
- oappend ("{z}");
- }
- }
- }
- }
-
- /* Check if the REX prefix is used. */
- if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
- all_prefixes[last_rex_prefix] = 0;
-
- /* Check if the SEG prefix is used. */
- if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
- | PREFIX_FS | PREFIX_GS)) != 0
- && (used_prefixes & active_seg_prefix) != 0)
- all_prefixes[last_seg_prefix] = 0;
+ case 0x0:
+ vex.length = 128;
+ break;
+ case 0x1:
+ vex.length = 256;
+ break;
+ case 0x2:
+ vex.length = 512;
+ break;
+ default:
+ return &bad_opcode;
+ }
+ }
+ break;
- /* Check if the ADDR prefix is used. */
- if ((prefixes & PREFIX_ADDR) != 0
- && (used_prefixes & PREFIX_ADDR) != 0)
- all_prefixes[last_addr_prefix] = 0;
+ case 0:
+ dp = &bad_opcode;
+ break;
- /* Check if the DATA prefix is used. */
- if ((prefixes & PREFIX_DATA) != 0
- && (used_prefixes & PREFIX_DATA) != 0)
- all_prefixes[last_data_prefix] = 0;
+ default:
+ abort ();
+ }
- /* Print the extra prefixes. */
- prefix_length = 0;
- for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
- if (all_prefixes[i])
- {
- const char *name;
- name = prefix_name (all_prefixes[i], orig_sizeflag);
- if (name == NULL)
- abort ();
- prefix_length += strlen (name) + 1;
- (*info->fprintf_func) (info->stream, "%s ", name);
- }
+ if (dp->name != NULL)
+ return dp;
+ else
+ return get_valid_dis386 (dp, info);
+}
- /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
- unused, opcode is invalid. Since the PREFIX_DATA prefix may be
- used by putop and MMX/SSE operand and may be overriden by the
- PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
- separately. */
- if (dp->prefix_requirement == PREFIX_OPCODE
- && dp != &bad_opcode
- && (((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
- && (used_prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
- || ((((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
- == PREFIX_DATA)
- && (used_prefixes & PREFIX_DATA) == 0))))
+static void
+get_sib (disassemble_info *info, int sizeflag)
+{
+ /* If modrm.mod == 3, operand must be register. */
+ if (need_modrm
+ && ((sizeflag & AFLAG) || address_mode == mode_64bit)
+ && modrm.mod != 3
+ && modrm.rm == 4)
{
- (*info->fprintf_func) (info->stream, "(bad)");
- return end_codep - priv.the_buffer;
+ FETCH_DATA (info, codep + 2);
+ sib.index = (codep [1] >> 3) & 7;
+ sib.scale = (codep [1] >> 6) & 3;
+ sib.base = codep [1] & 7;
}
+}
- /* Check maximum code length. */
- if ((codep - start_codep) > MAX_CODE_LENGTH)
+static int
+print_insn (bfd_vma pc, disassemble_info *info)
+{
+ const struct dis386 *dp;
+ int i;
+ char *op_txt[MAX_OPERANDS];
+ int needcomma;
+ int sizeflag, orig_sizeflag;
+ const char *p;
+ struct dis_private priv;
+ int prefix_length;
+
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ if ((info->mach & bfd_mach_i386_i386) != 0)
+ address_mode = mode_32bit;
+ else if (info->mach == bfd_mach_i386_i8086)
{
- (*info->fprintf_func) (info->stream, "(bad)");
- return MAX_CODE_LENGTH;
+ address_mode = mode_16bit;
+ priv.orig_sizeflag = 0;
}
+ else
+ address_mode = mode_64bit;
- obufp = mnemonicendp;
- for (i = strlen (obuf) + prefix_length; i < 6; i++)
- oappend (" ");
- oappend (" ");
- (*info->fprintf_func) (info->stream, "%s", obuf);
+ if (intel_syntax == (char) -1)
+ intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
- /* The enter and bound instructions are printed with operands in the same
- order as the intel book; everything else is printed in reverse order. */
- if (intel_syntax || two_source_ops)
+ for (p = info->disassembler_options; p != NULL; )
{
- bfd_vma riprel;
-
- for (i = 0; i < MAX_OPERANDS; ++i)
- op_txt[i] = op_out[i];
-
- if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
- && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
+ if (CONST_STRNEQ (p, "amd64"))
+ isa64 = amd64;
+ else if (CONST_STRNEQ (p, "intel64"))
+ isa64 = intel64;
+ else if (CONST_STRNEQ (p, "x86-64"))
{
- op_txt[2] = op_out[3];
- op_txt[3] = op_out[2];
+ address_mode = mode_64bit;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
-
- for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
+ else if (CONST_STRNEQ (p, "i386"))
{
- op_ad = op_index[i];
- op_index[i] = op_index[MAX_OPERANDS - 1 - i];
- op_index[MAX_OPERANDS - 1 - i] = op_ad;
- riprel = op_riprel[i];
- op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
- op_riprel[MAX_OPERANDS - 1 - i] = riprel;
+ address_mode = mode_32bit;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
- }
- else
- {
- for (i = 0; i < MAX_OPERANDS; ++i)
- op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
- }
-
- needcomma = 0;
- for (i = 0; i < MAX_OPERANDS; ++i)
- if (*op_txt[i])
- {
- if (needcomma)
- (*info->fprintf_func) (info->stream, ",");
- if (op_index[i] != -1 && !op_riprel[i])
- (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
- else
- (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
- needcomma = 1;
- }
-
- for (i = 0; i < MAX_OPERANDS; i++)
- if (op_index[i] != -1 && op_riprel[i])
- {
- (*info->fprintf_func) (info->stream, " # ");
- (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
- + op_address[op_index[i]]), info);
- break;
- }
- return codep - priv.the_buffer;
-}
-
-static const char *float_mem[] = {
- /* d8 */
- "fadd{s|}",
- "fmul{s|}",
- "fcom{s|}",
- "fcomp{s|}",
- "fsub{s|}",
- "fsubr{s|}",
- "fdiv{s|}",
- "fdivr{s|}",
- /* d9 */
- "fld{s|}",
- "(bad)",
- "fst{s|}",
- "fstp{s|}",
- "fldenvIC",
- "fldcw",
- "fNstenvIC",
- "fNstcw",
- /* da */
- "fiadd{l|}",
- "fimul{l|}",
- "ficom{l|}",
- "ficomp{l|}",
- "fisub{l|}",
- "fisubr{l|}",
- "fidiv{l|}",
- "fidivr{l|}",
- /* db */
- "fild{l|}",
- "fisttp{l|}",
- "fist{l|}",
- "fistp{l|}",
- "(bad)",
- "fld{t||t|}",
- "(bad)",
- "fstp{t||t|}",
- /* dc */
- "fadd{l|}",
- "fmul{l|}",
- "fcom{l|}",
- "fcomp{l|}",
- "fsub{l|}",
- "fsubr{l|}",
- "fdiv{l|}",
- "fdivr{l|}",
- /* dd */
- "fld{l|}",
- "fisttp{ll|}",
- "fst{l||}",
- "fstp{l|}",
- "frstorIC",
- "(bad)",
- "fNsaveIC",
- "fNstsw",
- /* de */
- "fiadd{s|}",
- "fimul{s|}",
- "ficom{s|}",
- "ficomp{s|}",
- "fisub{s|}",
- "fisubr{s|}",
- "fidiv{s|}",
- "fidivr{s|}",
- /* df */
- "fild{s|}",
- "fisttp{s|}",
- "fist{s|}",
- "fistp{s|}",
- "fbld",
- "fild{ll|}",
- "fbstp",
- "fistp{ll|}",
-};
+ else if (CONST_STRNEQ (p, "i8086"))
+ {
+ address_mode = mode_16bit;
+ priv.orig_sizeflag &= ~(AFLAG | DFLAG);
+ }
+ else if (CONST_STRNEQ (p, "intel"))
+ {
+ intel_syntax = 1;
+ if (CONST_STRNEQ (p + 5, "-mnemonic"))
+ intel_mnemonic = 1;
+ }
+ else if (CONST_STRNEQ (p, "att"))
+ {
+ intel_syntax = 0;
+ if (CONST_STRNEQ (p + 3, "-mnemonic"))
+ intel_mnemonic = 0;
+ }
+ else if (CONST_STRNEQ (p, "addr"))
+ {
+ if (address_mode == mode_64bit)
+ {
+ if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag &= ~AFLAG;
+ else if (p[4] == '6' && p[5] == '4')
+ priv.orig_sizeflag |= AFLAG;
+ }
+ else
+ {
+ if (p[4] == '1' && p[5] == '6')
+ priv.orig_sizeflag &= ~AFLAG;
+ else if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag |= AFLAG;
+ }
+ }
+ else if (CONST_STRNEQ (p, "data"))
+ {
+ if (p[4] == '1' && p[5] == '6')
+ priv.orig_sizeflag &= ~DFLAG;
+ else if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag |= DFLAG;
+ }
+ else if (CONST_STRNEQ (p, "suffix"))
+ priv.orig_sizeflag |= SUFFIX_ALWAYS;
-static const unsigned char float_mem_mode[] = {
- /* d8 */
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- /* d9 */
- d_mode,
- 0,
- d_mode,
- d_mode,
- 0,
- w_mode,
- 0,
- w_mode,
- /* da */
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- /* db */
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- 0,
- t_mode,
- 0,
- t_mode,
- /* dc */
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- /* dd */
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- 0,
- 0,
- 0,
- w_mode,
- /* de */
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- /* df */
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- t_mode,
- q_mode,
- t_mode,
- q_mode
-};
+ p = strchr (p, ',');
+ if (p != NULL)
+ p++;
+ }
-#define ST { OP_ST, 0 }
-#define STi { OP_STi, 0 }
+ if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
+ {
+ (*info->fprintf_func) (info->stream,
+ _("64-bit address is disabled"));
+ return -1;
+ }
-#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
-#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
-#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
-#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
-#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
-#define FGRPda_5 NULL, { { NULL, 6 } }, 0
-#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
-#define FGRPde_3 NULL, { { NULL, 8 } }, 0
-#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
+ if (intel_syntax)
+ {
+ names64 = intel_names64;
+ names32 = intel_names32;
+ names16 = intel_names16;
+ names8 = intel_names8;
+ names8rex = intel_names8rex;
+ names_seg = intel_names_seg;
+ names_mm = intel_names_mm;
+ names_bnd = intel_names_bnd;
+ names_xmm = intel_names_xmm;
+ names_ymm = intel_names_ymm;
+ names_zmm = intel_names_zmm;
+ names_tmm = intel_names_tmm;
+ index64 = intel_index64;
+ index32 = intel_index32;
+ names_mask = intel_names_mask;
+ index16 = intel_index16;
+ open_char = '[';
+ close_char = ']';
+ separator_char = '+';
+ scale_char = '*';
+ }
+ else
+ {
+ names64 = att_names64;
+ names32 = att_names32;
+ names16 = att_names16;
+ names8 = att_names8;
+ names8rex = att_names8rex;
+ names_seg = att_names_seg;
+ names_mm = att_names_mm;
+ names_bnd = att_names_bnd;
+ names_xmm = att_names_xmm;
+ names_ymm = att_names_ymm;
+ names_zmm = att_names_zmm;
+ names_tmm = att_names_tmm;
+ index64 = att_index64;
+ index32 = att_index32;
+ names_mask = att_names_mask;
+ index16 = att_index16;
+ open_char = '(';
+ close_char = ')';
+ separator_char = ',';
+ scale_char = ',';
+ }
-static const struct dis386 float_reg[][8] = {
- /* d8 */
- {
- { "fadd", { ST, STi }, 0 },
- { "fmul", { ST, STi }, 0 },
- { "fcom", { STi }, 0 },
- { "fcomp", { STi }, 0 },
- { "fsub", { ST, STi }, 0 },
- { "fsubr", { ST, STi }, 0 },
- { "fdiv", { ST, STi }, 0 },
- { "fdivr", { ST, STi }, 0 },
- },
- /* d9 */
- {
- { "fld", { STi }, 0 },
- { "fxch", { STi }, 0 },
- { FGRPd9_2 },
- { Bad_Opcode },
- { FGRPd9_4 },
- { FGRPd9_5 },
- { FGRPd9_6 },
- { FGRPd9_7 },
- },
- /* da */
- {
- { "fcmovb", { ST, STi }, 0 },
- { "fcmove", { ST, STi }, 0 },
- { "fcmovbe",{ ST, STi }, 0 },
- { "fcmovu", { ST, STi }, 0 },
- { Bad_Opcode },
- { FGRPda_5 },
- { Bad_Opcode },
- { Bad_Opcode },
- },
- /* db */
- {
- { "fcmovnb",{ ST, STi }, 0 },
- { "fcmovne",{ ST, STi }, 0 },
- { "fcmovnbe",{ ST, STi }, 0 },
- { "fcmovnu",{ ST, STi }, 0 },
- { FGRPdb_4 },
- { "fucomi", { ST, STi }, 0 },
- { "fcomi", { ST, STi }, 0 },
- { Bad_Opcode },
- },
- /* dc */
- {
- { "fadd", { STi, ST }, 0 },
- { "fmul", { STi, ST }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { "fsub{!M|r}", { STi, ST }, 0 },
- { "fsub{M|}", { STi, ST }, 0 },
- { "fdiv{!M|r}", { STi, ST }, 0 },
- { "fdiv{M|}", { STi, ST }, 0 },
- },
- /* dd */
- {
- { "ffree", { STi }, 0 },
- { Bad_Opcode },
- { "fst", { STi }, 0 },
- { "fstp", { STi }, 0 },
- { "fucom", { STi }, 0 },
- { "fucomp", { STi }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- },
- /* de */
- {
- { "faddp", { STi, ST }, 0 },
- { "fmulp", { STi, ST }, 0 },
- { Bad_Opcode },
- { FGRPde_3 },
- { "fsub{!M|r}p", { STi, ST }, 0 },
- { "fsub{M|}p", { STi, ST }, 0 },
- { "fdiv{!M|r}p", { STi, ST }, 0 },
- { "fdiv{M|}p", { STi, ST }, 0 },
- },
- /* df */
- {
- { "ffreep", { STi }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { FGRPdf_4 },
- { "fucomip", { ST, STi }, 0 },
- { "fcomip", { ST, STi }, 0 },
- { Bad_Opcode },
- },
-};
+ /* The output looks better if we put 7 bytes on a line, since that
+ puts most long word instructions on a single line. Use 8 bytes
+ for Intel L1OM. */
+ if ((info->mach & bfd_mach_l1om) != 0)
+ info->bytes_per_line = 8;
+ else
+ info->bytes_per_line = 7;
+
+ info->private_data = &priv;
+ priv.max_fetched = priv.the_buffer;
+ priv.insn_start = pc;
+
+ obuf[0] = 0;
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ op_out[i][0] = 0;
+ op_index[i] = -1;
+ }
+
+ the_info = info;
+ start_pc = pc;
+ start_codep = priv.the_buffer;
+ codep = priv.the_buffer;
+
+ if (OPCODES_SIGSETJMP (priv.bailout) != 0)
+ {
+ const char *name;
-static char *fgrps[][8] = {
- /* Bad opcode 0 */
- {
- "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
+ /* Getting here means we tried for data but didn't get it. That
+ means we have an incomplete instruction of some sort. Just
+ print the first byte as a prefix or a .byte pseudo-op. */
+ if (codep > priv.the_buffer)
+ {
+ name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
+ if (name != NULL)
+ (*info->fprintf_func) (info->stream, "%s", name);
+ else
+ {
+ /* Just print the first byte as a .byte instruction. */
+ (*info->fprintf_func) (info->stream, ".byte 0x%x",
+ (unsigned int) priv.the_buffer[0]);
+ }
- /* d9_2 1 */
- {
- "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
+ return 1;
+ }
- /* d9_4 2 */
- {
- "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
- },
+ return -1;
+ }
- /* d9_5 3 */
- {
- "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
- },
+ obufp = obuf;
+ sizeflag = priv.orig_sizeflag;
- /* d9_6 4 */
- {
- "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
- },
+ if (!ckprefix () || rex_used)
+ {
+ /* Too many prefixes or unused REX prefixes. */
+ for (i = 0;
+ i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
+ i++)
+ (*info->fprintf_func) (info->stream, "%s%s",
+ i == 0 ? "" : " ",
+ prefix_name (all_prefixes[i], sizeflag));
+ return i;
+ }
- /* d9_7 5 */
- {
- "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
- },
+ insn_codep = codep;
- /* da_5 6 */
- {
- "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
+ FETCH_DATA (info, codep + 1);
+ two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
- /* db_4 7 */
- {
- "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
- "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
- },
+ if (((prefixes & PREFIX_FWAIT)
+ && ((*codep < 0xd8) || (*codep > 0xdf))))
+ {
+ /* Handle prefixes before fwait. */
+ for (i = 0; i < fwait_prefix && all_prefixes[i];
+ i++)
+ (*info->fprintf_func) (info->stream, "%s ",
+ prefix_name (all_prefixes[i], sizeflag));
+ (*info->fprintf_func) (info->stream, "fwait");
+ return i + 1;
+ }
- /* de_3 8 */
- {
- "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
+ if (*codep == 0x0f)
+ {
+ unsigned char threebyte;
+
+ codep++;
+ FETCH_DATA (info, codep + 1);
+ threebyte = *codep;
+ dp = &dis386_twobyte[threebyte];
+ need_modrm = twobyte_has_modrm[*codep];
+ codep++;
+ }
+ else
+ {
+ dp = &dis386[*codep];
+ need_modrm = onebyte_has_modrm[*codep];
+ codep++;
+ }
+
+ /* Save sizeflag for printing the extra prefixes later before updating
+ it for mnemonic and operand processing. The prefix names depend
+ only on the address mode. */
+ orig_sizeflag = sizeflag;
+ if (prefixes & PREFIX_ADDR)
+ sizeflag ^= AFLAG;
+ if ((prefixes & PREFIX_DATA))
+ sizeflag ^= DFLAG;
+
+ end_codep = codep;
+ if (need_modrm)
+ {
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+
+ need_vex = 0;
+ memset (&vex, 0, sizeof (vex));
+
+ if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
+ {
+ get_sib (info, sizeflag);
+ dofloat (sizeflag);
+ }
+ else
+ {
+ dp = get_valid_dis386 (dp, info);
+ if (dp != NULL && putop (dp->name, sizeflag) == 0)
+ {
+ get_sib (info, sizeflag);
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ obufp = op_out[i];
+ op_ad = MAX_OPERANDS - 1 - i;
+ if (dp->op[i].rtn)
+ (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
+ /* For EVEX instruction after the last operand masking
+ should be printed. */
+ if (i == 0 && vex.evex)
+ {
+ /* Don't print {%k0}. */
+ if (vex.mask_register_specifier)
+ {
+ oappend ("{");
+ oappend (names_mask[vex.mask_register_specifier]);
+ oappend ("}");
+ }
+ if (vex.zeroing)
+ oappend ("{z}");
+ }
+ }
+ }
+ }
+
+ /* Clear instruction information. */
+ if (the_info)
+ {
+ the_info->insn_info_valid = 0;
+ the_info->branch_delay_insns = 0;
+ the_info->data_size = 0;
+ the_info->insn_type = dis_noninsn;
+ the_info->target = 0;
+ the_info->target2 = 0;
+ }
+
+ /* Reset jump operation indicator. */
+ op_is_jump = FALSE;
- /* df_4 9 */
{
- "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
-};
+ int jump_detection = 0;
-static void
-swap_operand (void)
-{
- mnemonicendp[0] = '.';
- mnemonicendp[1] = 's';
- mnemonicendp += 2;
-}
+ /* Extract flags. */
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ if ((dp->op[i].rtn == OP_J)
+ || (dp->op[i].rtn == OP_indirE))
+ jump_detection |= 1;
+ else if ((dp->op[i].rtn == BND_Fixup)
+ || (!dp->op[i].rtn && !dp->op[i].bytemode))
+ jump_detection |= 2;
+ else if ((dp->op[i].bytemode == cond_jump_mode)
+ || (dp->op[i].bytemode == loop_jcxz_mode))
+ jump_detection |= 4;
+ }
-static void
-OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-}
+ /* Determine if this is a jump or branch. */
+ if ((jump_detection & 0x3) == 0x3)
+ {
+ op_is_jump = TRUE;
+ if (jump_detection & 0x4)
+ the_info->insn_type = dis_condbranch;
+ else
+ the_info->insn_type =
+ (dp->name && !strncmp(dp->name, "call", 4))
+ ? dis_jsr : dis_branch;
+ }
+ }
-static void
-dofloat (int sizeflag)
-{
- const struct dis386 *dp;
- unsigned char floatop;
+ /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
+ are all 0s in inverted form. */
+ if (need_vex && vex.register_specifier != 0)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
- floatop = codep[-1];
+ /* Check if the REX prefix is used. */
+ if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
+ all_prefixes[last_rex_prefix] = 0;
- if (modrm.mod != 3)
+ /* Check if the SEG prefix is used. */
+ if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
+ | PREFIX_FS | PREFIX_GS)) != 0
+ && (used_prefixes & active_seg_prefix) != 0)
+ all_prefixes[last_seg_prefix] = 0;
+
+ /* Check if the ADDR prefix is used. */
+ if ((prefixes & PREFIX_ADDR) != 0
+ && (used_prefixes & PREFIX_ADDR) != 0)
+ all_prefixes[last_addr_prefix] = 0;
+
+ /* Check if the DATA prefix is used. */
+ if ((prefixes & PREFIX_DATA) != 0
+ && (used_prefixes & PREFIX_DATA) != 0
+ && !need_vex)
+ all_prefixes[last_data_prefix] = 0;
+
+ /* Print the extra prefixes. */
+ prefix_length = 0;
+ for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
+ if (all_prefixes[i])
+ {
+ const char *name;
+ name = prefix_name (all_prefixes[i], orig_sizeflag);
+ if (name == NULL)
+ abort ();
+ prefix_length += strlen (name) + 1;
+ (*info->fprintf_func) (info->stream, "%s ", name);
+ }
+
+ /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
+ unused, opcode is invalid. Since the PREFIX_DATA prefix may be
+ used by putop and MMX/SSE operand and may be overriden by the
+ PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
+ separately. */
+ if (dp->prefix_requirement == PREFIX_OPCODE
+ && (((need_vex
+ ? vex.prefix == REPE_PREFIX_OPCODE
+ || vex.prefix == REPNE_PREFIX_OPCODE
+ : (prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
+ && (used_prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
+ || (((need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : ((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+ == PREFIX_DATA))
+ && (used_prefixes & PREFIX_DATA) == 0))
+ || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
{
- int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
- putop (float_mem[fp_indx], sizeflag);
- obufp = op_out[0];
- op_ad = 2;
- OP_E (float_mem_mode[fp_indx], sizeflag);
- return;
+ /* Check maximum code length. */
+ if ((codep - start_codep) > MAX_CODE_LENGTH)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return MAX_CODE_LENGTH;
}
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- dp = &float_reg[floatop - 0xd8][modrm.reg];
- if (dp->name == NULL)
+ obufp = mnemonicendp;
+ for (i = strlen (obuf) + prefix_length; i < 6; i++)
+ oappend (" ");
+ oappend (" ");
+ (*info->fprintf_func) (info->stream, "%s", obuf);
+
+ /* The enter and bound instructions are printed with operands in the same
+ order as the intel book; everything else is printed in reverse order. */
+ if (intel_syntax || two_source_ops)
{
- putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
+ bfd_vma riprel;
- /* Instruction fnstsw is only one with strange arg. */
- if (floatop == 0xdf && codep[-1] == 0xe0)
- strcpy (op_out[0], names16[0]);
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ op_txt[i] = op_out[i];
+
+ if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
+ && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
+ {
+ op_txt[2] = op_out[3];
+ op_txt[3] = op_out[2];
+ }
+
+ for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
+ {
+ op_ad = op_index[i];
+ op_index[i] = op_index[MAX_OPERANDS - 1 - i];
+ op_index[MAX_OPERANDS - 1 - i] = op_ad;
+ riprel = op_riprel[i];
+ op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
+ op_riprel[MAX_OPERANDS - 1 - i] = riprel;
+ }
}
else
{
- putop (dp->name, sizeflag);
-
- obufp = op_out[0];
- op_ad = 2;
- if (dp->op[0].rtn)
- (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
-
- obufp = op_out[1];
- op_ad = 1;
- if (dp->op[1].rtn)
- (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
}
-}
-/* Like oappend (below), but S is a string starting with '%'.
- In Intel syntax, the '%' is elided. */
-static void
-oappend_maybe_intel (const char *s)
-{
- oappend (s + intel_syntax);
-}
+ needcomma = 0;
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ if (*op_txt[i])
+ {
+ if (needcomma)
+ (*info->fprintf_func) (info->stream, ",");
+ if (op_index[i] != -1 && !op_riprel[i])
+ {
+ bfd_vma target = (bfd_vma) op_address[op_index[i]];
-static void
-OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- oappend_maybe_intel ("%st");
-}
+ if (the_info && op_is_jump)
+ {
+ the_info->insn_info_valid = 1;
+ the_info->branch_delay_insns = 0;
+ the_info->data_size = 0;
+ the_info->target = target;
+ the_info->target2 = 0;
+ }
+ (*info->print_address_func) (target, info);
+ }
+ else
+ (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
+ needcomma = 1;
+ }
-static void
-OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- sprintf (scratchbuf, "%%st(%d)", modrm.rm);
- oappend_maybe_intel (scratchbuf);
+ for (i = 0; i < MAX_OPERANDS; i++)
+ if (op_index[i] != -1 && op_riprel[i])
+ {
+ (*info->fprintf_func) (info->stream, " # ");
+ (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
+ + op_address[op_index[i]]), info);
+ break;
+ }
+ return codep - priv.the_buffer;
}
-/* Capital letters in template are macros. */
-static int
-putop (const char *in_template, int sizeflag)
-{
- const char *p;
- int alt = 0;
- int cond = 1;
- unsigned int l = 0, len = 1;
- char last[4];
-
-#define SAVE_LAST(c) \
- if (l < len && l < sizeof (last)) \
- last[l++] = c; \
- else \
- abort ();
+static const char *float_mem[] = {
+ /* d8 */
+ "fadd{s|}",
+ "fmul{s|}",
+ "fcom{s|}",
+ "fcomp{s|}",
+ "fsub{s|}",
+ "fsubr{s|}",
+ "fdiv{s|}",
+ "fdivr{s|}",
+ /* d9 */
+ "fld{s|}",
+ "(bad)",
+ "fst{s|}",
+ "fstp{s|}",
+ "fldenv{C|C}",
+ "fldcw",
+ "fNstenv{C|C}",
+ "fNstcw",
+ /* da */
+ "fiadd{l|}",
+ "fimul{l|}",
+ "ficom{l|}",
+ "ficomp{l|}",
+ "fisub{l|}",
+ "fisubr{l|}",
+ "fidiv{l|}",
+ "fidivr{l|}",
+ /* db */
+ "fild{l|}",
+ "fisttp{l|}",
+ "fist{l|}",
+ "fistp{l|}",
+ "(bad)",
+ "fld{t|}",
+ "(bad)",
+ "fstp{t|}",
+ /* dc */
+ "fadd{l|}",
+ "fmul{l|}",
+ "fcom{l|}",
+ "fcomp{l|}",
+ "fsub{l|}",
+ "fsubr{l|}",
+ "fdiv{l|}",
+ "fdivr{l|}",
+ /* dd */
+ "fld{l|}",
+ "fisttp{ll|}",
+ "fst{l||}",
+ "fstp{l|}",
+ "frstor{C|C}",
+ "(bad)",
+ "fNsave{C|C}",
+ "fNstsw",
+ /* de */
+ "fiadd{s|}",
+ "fimul{s|}",
+ "ficom{s|}",
+ "ficomp{s|}",
+ "fisub{s|}",
+ "fisubr{s|}",
+ "fidiv{s|}",
+ "fidivr{s|}",
+ /* df */
+ "fild{s|}",
+ "fisttp{s|}",
+ "fist{s|}",
+ "fistp{s|}",
+ "fbld",
+ "fild{ll|}",
+ "fbstp",
+ "fistp{ll|}",
+};
- for (p = in_template; *p; p++)
- {
- switch (*p)
- {
- default:
- *obufp++ = *p;
- break;
- case '%':
- len++;
- break;
- case '!':
- cond = 0;
- break;
- case '{':
- if (intel_syntax)
- {
- while (*++p != '|')
- if (*p == '}' || *p == '\0')
- abort ();
- }
- /* Fall through. */
- case 'I':
- alt = 1;
- continue;
- case '|':
- while (*++p != '}')
- {
- if (*p == '\0')
- abort ();
- }
- break;
- case '}':
- break;
- case 'A':
- if (intel_syntax)
- break;
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- *obufp++ = 'b';
- break;
- case 'B':
- if (l == 0 && len == 1)
- {
-case_B:
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'b';
- }
- else
- {
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
+static const unsigned char float_mem_mode[] = {
+ /* d8 */
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ /* d9 */
+ d_mode,
+ 0,
+ d_mode,
+ d_mode,
+ 0,
+ w_mode,
+ 0,
+ w_mode,
+ /* da */
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ /* db */
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ 0,
+ t_mode,
+ 0,
+ t_mode,
+ /* dc */
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ /* dd */
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ 0,
+ 0,
+ 0,
+ w_mode,
+ /* de */
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ /* df */
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ t_mode,
+ q_mode,
+ t_mode,
+ q_mode
+};
- if (address_mode == mode_64bit
- && !(prefixes & PREFIX_ADDR))
- {
- *obufp++ = 'a';
- *obufp++ = 'b';
- *obufp++ = 's';
- }
+#define ST { OP_ST, 0 }
+#define STi { OP_STi, 0 }
- goto case_B;
- }
- break;
- case 'C':
- if (intel_syntax && !alt)
- break;
- if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
- {
- if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = intel_syntax ? 'w' : 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case 'D':
- if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
- break;
- USED_REX (REX_W);
- if (modrm.mod == 3)
- {
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- }
- else
- *obufp++ = 'w';
- break;
- case 'E': /* For jcxz/jecxz */
- if (address_mode == mode_64bit)
- {
- if (sizeflag & AFLAG)
- *obufp++ = 'r';
- else
- *obufp++ = 'e';
- }
- else
- if (sizeflag & AFLAG)
- *obufp++ = 'e';
- used_prefixes |= (prefixes & PREFIX_ADDR);
- break;
- case 'F':
- if (intel_syntax)
- break;
- if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
- {
- if (sizeflag & AFLAG)
- *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
- else
- *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
- used_prefixes |= (prefixes & PREFIX_ADDR);
- }
- break;
- case 'G':
- if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
- break;
- if ((rex & REX_W) || (sizeflag & DFLAG))
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 'H':
- if (intel_syntax)
- break;
- if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
- || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
- {
- used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
- *obufp++ = ',';
- *obufp++ = 'p';
- if (prefixes & PREFIX_DS)
- *obufp++ = 't';
- else
- *obufp++ = 'n';
- }
- break;
- case 'J':
- if (intel_syntax)
- break;
- *obufp++ = 'l';
- break;
- case 'K':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- *obufp++ = 'd';
- break;
- case 'Z':
- if (l != 0 || len != 1)
- {
- if (l != 1 || len != 2 || last[0] != 'X')
- {
- SAVE_LAST (*p);
- break;
- }
- if (!need_vex || !vex.evex)
- abort ();
- if (intel_syntax
- || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
- break;
- switch (vex.length)
- {
- case 128:
- *obufp++ = 'x';
- break;
- case 256:
- *obufp++ = 'y';
- break;
- case 512:
- *obufp++ = 'z';
- break;
- default:
- abort ();
- }
- break;
- }
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- goto case_L;
- case 'L':
- if (l != 0 || len != 1)
- {
- SAVE_LAST (*p);
- break;
- }
-case_L:
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'l';
- break;
- case 'M':
- if (intel_mnemonic != cond)
- *obufp++ = 'r';
- break;
- case 'N':
- if ((prefixes & PREFIX_FWAIT) == 0)
- *obufp++ = 'n';
- else
- used_prefixes |= PREFIX_FWAIT;
- break;
- case 'O':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'o';
- else if (intel_syntax && (sizeflag & DFLAG))
- *obufp++ = 'q';
- else
- *obufp++ = 'd';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case '&':
- if (!intel_syntax
- && address_mode == mode_64bit
- && isa64 == intel64)
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- case 'T':
- if (!intel_syntax
- && address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- goto case_P;
- case 'P':
- if (l == 0 && len == 1)
- {
-case_P:
- if (intel_syntax)
- {
- if ((rex & REX_W) == 0
- && (prefixes & PREFIX_DATA))
- {
- if ((sizeflag & DFLAG) == 0)
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- }
- if ((prefixes & PREFIX_DATA)
- || (rex & REX_W)
- || (sizeflag & SUFFIX_ALWAYS))
- {
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- }
- }
- else
- {
- if (l != 1 || len != 2 || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
+#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
+#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
+#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
+#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
+#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
+#define FGRPda_5 NULL, { { NULL, 6 } }, 0
+#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
+#define FGRPde_3 NULL, { { NULL, 8 } }, 0
+#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
- if ((prefixes & PREFIX_DATA)
- || (rex & REX_W)
- || (sizeflag & SUFFIX_ALWAYS))
- {
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- }
- }
- break;
- case 'U':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
- {
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- goto case_Q;
- case 'Q':
- if (l == 0 && len == 1)
- {
-case_Q:
- if (intel_syntax && !alt)
- break;
- USED_REX (REX_W);
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- {
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- }
- }
- else
- {
- if (l != 1 || len != 2 || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
- if (intel_syntax
- || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
- break;
- if ((rex & REX_W))
- {
- USED_REX (REX_W);
- *obufp++ = 'q';
- }
- else
- *obufp++ = 'l';
- }
- break;
- case 'R':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else if (sizeflag & DFLAG)
- {
- if (intel_syntax)
- *obufp++ = 'd';
- else
- *obufp++ = 'l';
- }
- else
- *obufp++ = 'w';
- if (intel_syntax && !p[1]
- && ((rex & REX_W) || (sizeflag & DFLAG)))
- *obufp++ = 'e';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 'V':
- if (l == 0 && len == 1)
- {
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
- {
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'q';
- break;
- }
- }
- else
- {
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
+static const struct dis386 float_reg[][8] = {
+ /* d8 */
+ {
+ { "fadd", { ST, STi }, 0 },
+ { "fmul", { ST, STi }, 0 },
+ { "fcom", { STi }, 0 },
+ { "fcomp", { STi }, 0 },
+ { "fsub", { ST, STi }, 0 },
+ { "fsubr", { ST, STi }, 0 },
+ { "fdiv", { ST, STi }, 0 },
+ { "fdivr", { ST, STi }, 0 },
+ },
+ /* d9 */
+ {
+ { "fld", { STi }, 0 },
+ { "fxch", { STi }, 0 },
+ { FGRPd9_2 },
+ { Bad_Opcode },
+ { FGRPd9_4 },
+ { FGRPd9_5 },
+ { FGRPd9_6 },
+ { FGRPd9_7 },
+ },
+ /* da */
+ {
+ { "fcmovb", { ST, STi }, 0 },
+ { "fcmove", { ST, STi }, 0 },
+ { "fcmovbe",{ ST, STi }, 0 },
+ { "fcmovu", { ST, STi }, 0 },
+ { Bad_Opcode },
+ { FGRPda_5 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* db */
+ {
+ { "fcmovnb",{ ST, STi }, 0 },
+ { "fcmovne",{ ST, STi }, 0 },
+ { "fcmovnbe",{ ST, STi }, 0 },
+ { "fcmovnu",{ ST, STi }, 0 },
+ { FGRPdb_4 },
+ { "fucomi", { ST, STi }, 0 },
+ { "fcomi", { ST, STi }, 0 },
+ { Bad_Opcode },
+ },
+ /* dc */
+ {
+ { "fadd", { STi, ST }, 0 },
+ { "fmul", { STi, ST }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "fsub{!M|r}", { STi, ST }, 0 },
+ { "fsub{M|}", { STi, ST }, 0 },
+ { "fdiv{!M|r}", { STi, ST }, 0 },
+ { "fdiv{M|}", { STi, ST }, 0 },
+ },
+ /* dd */
+ {
+ { "ffree", { STi }, 0 },
+ { Bad_Opcode },
+ { "fst", { STi }, 0 },
+ { "fstp", { STi }, 0 },
+ { "fucom", { STi }, 0 },
+ { "fucomp", { STi }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* de */
+ {
+ { "faddp", { STi, ST }, 0 },
+ { "fmulp", { STi, ST }, 0 },
+ { Bad_Opcode },
+ { FGRPde_3 },
+ { "fsub{!M|r}p", { STi, ST }, 0 },
+ { "fsub{M|}p", { STi, ST }, 0 },
+ { "fdiv{!M|r}p", { STi, ST }, 0 },
+ { "fdiv{M|}p", { STi, ST }, 0 },
+ },
+ /* df */
+ {
+ { "ffreep", { STi }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { FGRPdf_4 },
+ { "fucomip", { ST, STi }, 0 },
+ { "fcomip", { ST, STi }, 0 },
+ { Bad_Opcode },
+ },
+};
- if (rex & REX_W)
- {
- *obufp++ = 'a';
- *obufp++ = 'b';
- *obufp++ = 's';
- }
- }
- /* Fall through. */
- goto case_S;
- case 'S':
- if (l == 0 && len == 1)
- {
-case_S:
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- {
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- }
- }
- else
- {
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
+static char *fgrps[][8] = {
+ /* Bad opcode 0 */
+ {
+ "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* d9_2 1 */
+ {
+ "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* d9_4 2 */
+ {
+ "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
+ },
+
+ /* d9_5 3 */
+ {
+ "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
+ },
+
+ /* d9_6 4 */
+ {
+ "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
+ },
+
+ /* d9_7 5 */
+ {
+ "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
+ },
- if (address_mode == mode_64bit
- && !(prefixes & PREFIX_ADDR))
- {
- *obufp++ = 'a';
- *obufp++ = 'b';
- *obufp++ = 's';
- }
+ /* da_5 6 */
+ {
+ "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
- goto case_S;
- }
- break;
- case 'X':
- if (l != 0 || len != 1)
- {
- SAVE_LAST (*p);
- break;
- }
- if (need_vex && vex.prefix)
- {
- if (vex.prefix == DATA_PREFIX_OPCODE)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
- }
- else
- {
- if (prefixes & PREFIX_DATA)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case 'Y':
- if (l == 0 && len == 1)
- abort ();
- else
- {
- if (l != 1 || len != 2 || last[0] != 'X')
- {
- SAVE_LAST (*p);
- break;
- }
- if (!need_vex)
- abort ();
- if (intel_syntax
- || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
- break;
- switch (vex.length)
- {
- case 128:
- *obufp++ = 'x';
- break;
- case 256:
- *obufp++ = 'y';
- break;
- case 512:
- if (!vex.evex)
- default:
- abort ();
- }
- }
- break;
- case 'W':
- if (l == 0 && len == 1)
- {
- /* operand size flag for cwtl, cbtw */
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- if (intel_syntax)
- *obufp++ = 'd';
- else
- *obufp++ = 'l';
- }
- else if (sizeflag & DFLAG)
- *obufp++ = 'w';
- else
- *obufp++ = 'b';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- else
- {
- if (l != 1
- || len != 2
- || (last[0] != 'X'
- && last[0] != 'L'))
- {
- SAVE_LAST (*p);
- break;
- }
- if (!need_vex)
- abort ();
- if (last[0] == 'X')
- *obufp++ = vex.w ? 'd': 's';
- else
- *obufp++ = vex.w ? 'q': 'd';
- }
- break;
- case '^':
- if (intel_syntax)
- break;
- if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case '@':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit
- && (isa64 == intel64
- || ((sizeflag & DFLAG) || (rex & REX_W))))
- *obufp++ = 'q';
- else if ((prefixes & PREFIX_DATA))
- {
- if (!(sizeflag & DFLAG))
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- }
- alt = 0;
- }
- *obufp = 0;
- mnemonicendp = obufp;
- return 0;
-}
+ /* db_4 7 */
+ {
+ "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
+ "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
+ },
-static void
-oappend (const char *s)
-{
- obufp = stpcpy (obufp, s);
-}
+ /* de_3 8 */
+ {
+ "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* df_4 9 */
+ {
+ "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+};
static void
-append_seg (void)
+swap_operand (void)
{
- /* Only print the active segment register. */
- if (!active_seg_prefix)
- return;
-
- used_prefixes |= active_seg_prefix;
- switch (active_seg_prefix)
- {
- case PREFIX_CS:
- oappend_maybe_intel ("%cs:");
- break;
- case PREFIX_DS:
- oappend_maybe_intel ("%ds:");
- break;
- case PREFIX_SS:
- oappend_maybe_intel ("%ss:");
- break;
- case PREFIX_ES:
- oappend_maybe_intel ("%es:");
- break;
- case PREFIX_FS:
- oappend_maybe_intel ("%fs:");
- break;
- case PREFIX_GS:
- oappend_maybe_intel ("%gs:");
- break;
- default:
- break;
- }
+ mnemonicendp[0] = '.';
+ mnemonicendp[1] = 's';
+ mnemonicendp += 2;
}
static void
-OP_indirE (int bytemode, int sizeflag)
+OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
{
- if (!intel_syntax)
- oappend ("*");
- OP_E (bytemode, sizeflag);
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
}
static void
-print_operand_value (char *buf, int hex, bfd_vma disp)
+dofloat (int sizeflag)
{
- if (address_mode == mode_64bit)
- {
- if (hex)
- {
- char tmp[30];
- int i;
- buf[0] = '0';
- buf[1] = 'x';
- sprintf_vma (tmp, disp);
- for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
- strcpy (buf + 2, tmp + i);
- }
- else
- {
- bfd_signed_vma v = disp;
- char tmp[30];
- int i;
- if (v < 0)
- {
- *(buf++) = '-';
- v = -disp;
- /* Check for possible overflow on 0x8000000000000000. */
- if (v < 0)
- {
- strcpy (buf, "9223372036854775808");
- return;
- }
- }
- if (!v)
- {
- strcpy (buf, "0");
- return;
- }
+ const struct dis386 *dp;
+ unsigned char floatop;
- i = 0;
- tmp[29] = 0;
- while (v)
- {
- tmp[28 - i] = (v % 10) + '0';
- v /= 10;
- i++;
- }
- strcpy (buf, tmp + 29 - i);
- }
- }
- else
- {
- if (hex)
- sprintf (buf, "0x%x", (unsigned int) disp);
- else
- sprintf (buf, "%d", (int) disp);
- }
-}
+ floatop = codep[-1];
-/* Put DISP in BUF as signed hex number. */
+ if (modrm.mod != 3)
+ {
+ int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
-static void
-print_displacement (char *buf, bfd_vma disp)
-{
- bfd_signed_vma val = disp;
- char tmp[30];
- int i, j = 0;
+ putop (float_mem[fp_indx], sizeflag);
+ obufp = op_out[0];
+ op_ad = 2;
+ OP_E (float_mem_mode[fp_indx], sizeflag);
+ return;
+ }
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
- if (val < 0)
+ dp = &float_reg[floatop - 0xd8][modrm.reg];
+ if (dp->name == NULL)
{
- buf[j++] = '-';
- val = -disp;
+ putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
- /* Check for possible overflow. */
- if (val < 0)
- {
- switch (address_mode)
- {
- case mode_64bit:
- strcpy (buf + j, "0x8000000000000000");
- break;
- case mode_32bit:
- strcpy (buf + j, "0x80000000");
- break;
- case mode_16bit:
- strcpy (buf + j, "0x8000");
- break;
- }
- return;
- }
+ /* Instruction fnstsw is only one with strange arg. */
+ if (floatop == 0xdf && codep[-1] == 0xe0)
+ strcpy (op_out[0], names16[0]);
}
+ else
+ {
+ putop (dp->name, sizeflag);
- buf[j++] = '0';
- buf[j++] = 'x';
+ obufp = op_out[0];
+ op_ad = 2;
+ if (dp->op[0].rtn)
+ (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
- sprintf_vma (tmp, (bfd_vma) val);
- for (i = 0; tmp[i] == '0'; i++)
- continue;
- if (tmp[i] == '\0')
- i--;
- strcpy (buf + j, tmp + i);
+ obufp = op_out[1];
+ op_ad = 1;
+ if (dp->op[1].rtn)
+ (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
+ }
}
+/* Like oappend (below), but S is a string starting with '%'.
+ In Intel syntax, the '%' is elided. */
static void
-intel_operand_size (int bytemode, int sizeflag)
+oappend_maybe_intel (const char *s)
{
- if (vex.evex
- && vex.b
- && (bytemode == x_mode
- || bytemode == evex_half_bcst_xmmq_mode))
- {
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- return;
- }
- switch (bytemode)
+ oappend (s + intel_syntax);
+}
+
+static void
+OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ oappend_maybe_intel ("%st");
+}
+
+static void
+OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ sprintf (scratchbuf, "%%st(%d)", modrm.rm);
+ oappend_maybe_intel (scratchbuf);
+}
+
+/* Capital letters in template are macros. */
+static int
+putop (const char *in_template, int sizeflag)
+{
+ const char *p;
+ int alt = 0;
+ int cond = 1;
+ unsigned int l = 0, len = 0;
+ char last[4];
+
+ for (p = in_template; *p; p++)
{
- case b_mode:
- case b_swap_mode:
- case dqb_mode:
- case db_mode:
- oappend ("BYTE PTR ");
- break;
- case w_mode:
- case dw_mode:
- case dqw_mode:
- oappend ("WORD PTR ");
- break;
- case indir_v_mode:
- if (address_mode == mode_64bit && isa64 == intel64)
+ if (len > l)
{
- oappend ("QWORD PTR ");
- break;
+ if (l >= sizeof (last) || !ISUPPER (*p))
+ abort ();
+ last[l++] = *p;
+ continue;
}
- /* Fall through. */
- case stack_v_mode:
- if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
+ switch (*p)
{
- oappend ("QWORD PTR ");
+ default:
+ *obufp++ = *p;
break;
- }
- /* Fall through. */
- case v_mode:
- case v_swap_mode:
- case dq_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend ("QWORD PTR ");
- else
- {
- if ((sizeflag & DFLAG) || bytemode == dq_mode)
- oappend ("DWORD PTR ");
+ case '%':
+ len++;
+ break;
+ case '!':
+ cond = 0;
+ break;
+ case '{':
+ if (intel_syntax)
+ {
+ while (*++p != '|')
+ if (*p == '}' || *p == '\0')
+ abort ();
+ alt = 1;
+ }
+ break;
+ case '|':
+ while (*++p != '}')
+ {
+ if (*p == '\0')
+ abort ();
+ }
+ break;
+ case '}':
+ alt = 0;
+ break;
+ case 'A':
+ if (intel_syntax)
+ break;
+ if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = 'b';
+ break;
+ case 'B':
+ if (l == 0)
+ {
+ case_B:
+ if (intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'b';
+ }
+ else if (l == 1 && last[0] == 'L')
+ {
+ if (address_mode == mode_64bit
+ && !(prefixes & PREFIX_ADDR))
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
+
+ goto case_B;
+ }
else
- oappend ("WORD PTR ");
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case z_mode:
- if ((rex & REX_W) || (sizeflag & DFLAG))
- *obufp++ = 'D';
- oappend ("WORD PTR ");
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case a_mode:
- if (sizeflag & DFLAG)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case d_mode:
- case d_scalar_mode:
- case d_scalar_swap_mode:
- case d_swap_mode:
- case dqd_mode:
- oappend ("DWORD PTR ");
- break;
- case q_mode:
- case q_scalar_mode:
- case q_scalar_swap_mode:
- case q_swap_mode:
- oappend ("QWORD PTR ");
- break;
- case dqa_mode:
- case m_mode:
- if (address_mode == mode_64bit)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- break;
- case f_mode:
- if (sizeflag & DFLAG)
- oappend ("FWORD PTR ");
- else
- oappend ("DWORD PTR ");
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case t_mode:
- oappend ("TBYTE PTR ");
- break;
- case x_mode:
- case x_swap_mode:
- case evex_x_gscat_mode:
- case evex_x_nobcst_mode:
- case b_scalar_mode:
- case w_scalar_mode:
- if (need_vex)
- {
- switch (vex.length)
+ abort ();
+ break;
+ case 'C':
+ if (intel_syntax && !alt)
+ break;
+ if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = intel_syntax ? 'w' : 's';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case 'D':
+ if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
+ break;
+ USED_REX (REX_W);
+ if (modrm.mod == 3)
+ {
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ else
+ *obufp++ = 'w';
+ break;
+ case 'E': /* For jcxz/jecxz */
+ if (address_mode == mode_64bit)
{
- case 128:
- oappend ("XMMWORD PTR ");
- break;
- case 256:
- oappend ("YMMWORD PTR ");
- break;
- case 512:
- oappend ("ZMMWORD PTR ");
- break;
- default:
- abort ();
+ if (sizeflag & AFLAG)
+ *obufp++ = 'r';
+ else
+ *obufp++ = 'e';
}
- }
- else
- oappend ("XMMWORD PTR ");
- break;
- case xmm_mode:
- oappend ("XMMWORD PTR ");
- break;
- case ymm_mode:
- oappend ("YMMWORD PTR ");
- break;
- case xmmq_mode:
- case evex_half_bcst_xmmq_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- oappend ("QWORD PTR ");
+ else
+ if (sizeflag & AFLAG)
+ *obufp++ = 'e';
+ used_prefixes |= (prefixes & PREFIX_ADDR);
break;
- case 256:
- oappend ("XMMWORD PTR ");
+ case 'F':
+ if (intel_syntax)
+ break;
+ if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & AFLAG)
+ *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
+ else
+ *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
+ used_prefixes |= (prefixes & PREFIX_ADDR);
+ }
break;
- case 512:
- oappend ("YMMWORD PTR ");
+ case 'G':
+ if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ if ((rex & REX_W) || (sizeflag & DFLAG))
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
break;
- default:
- abort ();
- }
- break;
- case xmm_mb_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("BYTE PTR ");
+ case 'H':
+ if (intel_syntax)
+ break;
+ if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
+ || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
+ {
+ used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
+ *obufp++ = ',';
+ *obufp++ = 'p';
+ if (prefixes & PREFIX_DS)
+ *obufp++ = 't';
+ else
+ *obufp++ = 'n';
+ }
break;
- default:
- abort ();
- }
- break;
- case xmm_mw_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("WORD PTR ");
+ case 'K':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ *obufp++ = 'd';
break;
- default:
- abort ();
- }
- break;
- case xmm_md_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("DWORD PTR ");
+ case 'Z':
+ if (l != 0)
+ {
+ if (l != 1 || last[0] != 'X')
+ abort ();
+ if (!need_vex || !vex.evex)
+ abort ();
+ if (intel_syntax
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ switch (vex.length)
+ {
+ case 128:
+ *obufp++ = 'x';
+ break;
+ case 256:
+ *obufp++ = 'y';
+ break;
+ case 512:
+ *obufp++ = 'z';
+ break;
+ default:
+ abort ();
+ }
+ break;
+ }
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ goto case_L;
+ case 'L':
+ if (l != 0)
+ abort ();
+ case_L:
+ if (intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'l';
break;
- default:
- abort ();
- }
- break;
- case xmm_mq_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("QWORD PTR ");
+ case 'M':
+ if (intel_mnemonic != cond)
+ *obufp++ = 'r';
break;
- default:
- abort ();
- }
- break;
- case xmmdw_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- oappend ("WORD PTR ");
+ case 'N':
+ if ((prefixes & PREFIX_FWAIT) == 0)
+ *obufp++ = 'n';
+ else
+ used_prefixes |= PREFIX_FWAIT;
+ break;
+ case 'O':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'o';
+ else if (intel_syntax && (sizeflag & DFLAG))
+ *obufp++ = 'q';
+ else
+ *obufp++ = 'd';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case '&':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && isa64 == intel64)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ case 'T':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ goto case_P;
+ case 'P':
+ if (l == 0)
+ {
+ case_P:
+ if (intel_syntax)
+ {
+ if ((rex & REX_W) == 0
+ && (prefixes & PREFIX_DATA))
+ {
+ if ((sizeflag & DFLAG) == 0)
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ }
+ if ((prefixes & PREFIX_DATA)
+ || (rex & REX_W)
+ || (sizeflag & SUFFIX_ALWAYS))
+ {
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else if (l == 1 && last[0] == 'L')
+ {
+ if ((prefixes & PREFIX_DATA)
+ || (rex & REX_W)
+ || (sizeflag & SUFFIX_ALWAYS))
+ {
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else
+ abort ();
break;
- case 256:
- oappend ("DWORD PTR ");
+ case 'U':
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ goto case_Q;
+ case 'Q':
+ if (l == 0)
+ {
+ case_Q:
+ if (intel_syntax && !alt)
+ break;
+ USED_REX (REX_W);
+ if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else if (l == 1 && last[0] == 'D')
+ *obufp++ = vex.w ? 'q' : 'd';
+ else if (l == 1 && last[0] == 'L')
+ {
+ if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
+ : address_mode != mode_64bit)
+ break;
+ if ((rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ }
+ else if((address_mode == mode_64bit && need_modrm && cond)
+ || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = intel_syntax? 'd' : 'l';
+ }
+ else
+ abort ();
break;
- case 512:
- oappend ("QWORD PTR ");
+ case 'R':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else if (sizeflag & DFLAG)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
+ }
+ else
+ *obufp++ = 'w';
+ if (intel_syntax && !p[1]
+ && ((rex & REX_W) || (sizeflag & DFLAG)))
+ *obufp++ = 'e';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
break;
- default:
- abort ();
- }
- break;
- case xmmqd_mode:
- if (!need_vex)
- abort ();
+ case 'V':
+ if (l == 0)
+ {
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'q';
+ break;
+ }
+ }
+ else if (l == 1 && last[0] == 'L')
+ {
+ if (rex & REX_W)
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
+ }
+ else
+ abort ();
+ /* Fall through. */
+ goto case_S;
+ case 'S':
+ if (l == 0)
+ {
+ case_S:
+ if (intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ {
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else if (l == 1 && last[0] == 'L')
+ {
+ if (address_mode == mode_64bit
+ && !(prefixes & PREFIX_ADDR))
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
- switch (vex.length)
- {
- case 128:
- oappend ("DWORD PTR ");
+ goto case_S;
+ }
+ else
+ abort ();
break;
- case 256:
- oappend ("QWORD PTR ");
+ case 'X':
+ if (l != 0)
+ abort ();
+ if (need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : prefixes & PREFIX_DATA)
+ {
+ *obufp++ = 'd';
+ used_prefixes |= PREFIX_DATA;
+ }
+ else
+ *obufp++ = 's';
break;
- case 512:
- oappend ("XMMWORD PTR ");
+ case 'Y':
+ if (l == 1 && last[0] == 'X')
+ {
+ if (!need_vex)
+ abort ();
+ if (intel_syntax
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ switch (vex.length)
+ {
+ case 128:
+ *obufp++ = 'x';
+ break;
+ case 256:
+ *obufp++ = 'y';
+ break;
+ case 512:
+ if (!vex.evex)
+ default:
+ abort ();
+ }
+ }
+ else
+ abort ();
break;
- default:
- abort ();
- }
- break;
- case ymmq_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- oappend ("QWORD PTR ");
+ case 'W':
+ if (l == 0)
+ {
+ /* operand size flag for cwtl, cbtw */
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
+ }
+ else if (sizeflag & DFLAG)
+ *obufp++ = 'w';
+ else
+ *obufp++ = 'b';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ else if (l == 1)
+ {
+ if (!need_vex)
+ abort ();
+ if (last[0] == 'X')
+ *obufp++ = vex.w ? 'd': 's';
+ else if (last[0] == 'B')
+ *obufp++ = vex.w ? 'w': 'b';
+ else
+ abort ();
+ }
+ else
+ abort ();
break;
- case 256:
- oappend ("YMMWORD PTR ");
+ case '^':
+ if (intel_syntax)
+ break;
+ if (isa64 == intel64 && (rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ break;
+ }
+ if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
break;
- case 512:
- oappend ("ZMMWORD PTR ");
+ case '@':
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && (isa64 == intel64
+ || ((sizeflag & DFLAG) || (rex & REX_W))))
+ *obufp++ = 'q';
+ else if ((prefixes & PREFIX_DATA))
+ {
+ if (!(sizeflag & DFLAG))
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
break;
- default:
- abort ();
}
- break;
- case ymmxmm_mode:
- if (!need_vex)
- abort ();
- switch (vex.length)
- {
- case 128:
- case 256:
- oappend ("XMMWORD PTR ");
- break;
- default:
- abort ();
- }
+ if (len == l)
+ len = l = 0;
+ }
+ *obufp = 0;
+ mnemonicendp = obufp;
+ return 0;
+}
+
+static void
+oappend (const char *s)
+{
+ obufp = stpcpy (obufp, s);
+}
+
+static void
+append_seg (void)
+{
+ /* Only print the active segment register. */
+ if (!active_seg_prefix)
+ return;
+
+ used_prefixes |= active_seg_prefix;
+ switch (active_seg_prefix)
+ {
+ case PREFIX_CS:
+ oappend_maybe_intel ("%cs:");
break;
- case o_mode:
- oappend ("OWORD PTR ");
+ case PREFIX_DS:
+ oappend_maybe_intel ("%ds:");
break;
- case xmm_mdq_mode:
- case vex_w_dq_mode:
- case vex_scalar_w_dq_mode:
- if (!need_vex)
- abort ();
-
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
+ case PREFIX_SS:
+ oappend_maybe_intel ("%ss:");
break;
- case vex_vsib_d_w_dq_mode:
- case vex_vsib_q_w_dq_mode:
- if (!need_vex)
- abort ();
+ case PREFIX_ES:
+ oappend_maybe_intel ("%es:");
+ break;
+ case PREFIX_FS:
+ oappend_maybe_intel ("%fs:");
+ break;
+ case PREFIX_GS:
+ oappend_maybe_intel ("%gs:");
+ break;
+ default:
+ break;
+ }
+}
- if (!vex.evex)
+static void
+OP_indirE (int bytemode, int sizeflag)
+{
+ if (!intel_syntax)
+ oappend ("*");
+ OP_E (bytemode, sizeflag);
+}
+
+static void
+print_operand_value (char *buf, int hex, bfd_vma disp)
+{
+ if (address_mode == mode_64bit)
+ {
+ if (hex)
{
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
+ char tmp[30];
+ int i;
+ buf[0] = '0';
+ buf[1] = 'x';
+ sprintf_vma (tmp, disp);
+ for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
+ strcpy (buf + 2, tmp + i);
}
else
{
- switch (vex.length)
+ bfd_signed_vma v = disp;
+ char tmp[30];
+ int i;
+ if (v < 0)
{
- case 128:
- oappend ("XMMWORD PTR ");
- break;
- case 256:
- oappend ("YMMWORD PTR ");
- break;
- case 512:
- oappend ("ZMMWORD PTR ");
- break;
- default:
- abort ();
+ *(buf++) = '-';
+ v = -disp;
+ /* Check for possible overflow on 0x8000000000000000. */
+ if (v < 0)
+ {
+ strcpy (buf, "9223372036854775808");
+ return;
+ }
+ }
+ if (!v)
+ {
+ strcpy (buf, "0");
+ return;
}
- }
- break;
- case vex_vsib_q_w_d_mode:
- case vex_vsib_d_w_d_mode:
- if (!need_vex || !vex.evex)
- abort ();
- switch (vex.length)
- {
- case 128:
- oappend ("QWORD PTR ");
- break;
- case 256:
- oappend ("XMMWORD PTR ");
- break;
- case 512:
- oappend ("YMMWORD PTR ");
- break;
- default:
- abort ();
+ i = 0;
+ tmp[29] = 0;
+ while (v)
+ {
+ tmp[28 - i] = (v % 10) + '0';
+ v /= 10;
+ i++;
+ }
+ strcpy (buf, tmp + 29 - i);
}
-
- break;
- case mask_bd_mode:
- if (!need_vex || vex.length != 128)
- abort ();
- if (vex.w)
- oappend ("DWORD PTR ");
- else
- oappend ("BYTE PTR ");
- break;
- case mask_mode:
- if (!need_vex)
- abort ();
- if (vex.w)
- oappend ("QWORD PTR ");
+ }
+ else
+ {
+ if (hex)
+ sprintf (buf, "0x%x", (unsigned int) disp);
else
- oappend ("WORD PTR ");
- break;
- case v_bnd_mode:
- case v_bndmk_mode:
- default:
- break;
+ sprintf (buf, "%d", (int) disp);
}
}
+/* Put DISP in BUF as signed hex number. */
+
static void
-OP_E_register (int bytemode, int sizeflag)
+print_displacement (char *buf, bfd_vma disp)
{
- int reg = modrm.rm;
- const char **names;
+ bfd_signed_vma val = disp;
+ char tmp[30];
+ int i, j = 0;
- USED_REX (REX_B);
- if ((rex & REX_B))
- reg += 8;
+ if (val < 0)
+ {
+ buf[j++] = '-';
+ val = -disp;
- if ((sizeflag & SUFFIX_ALWAYS)
- && (bytemode == b_swap_mode
- || bytemode == bnd_swap_mode
- || bytemode == v_swap_mode))
- swap_operand ();
+ /* Check for possible overflow. */
+ if (val < 0)
+ {
+ switch (address_mode)
+ {
+ case mode_64bit:
+ strcpy (buf + j, "0x8000000000000000");
+ break;
+ case mode_32bit:
+ strcpy (buf + j, "0x80000000");
+ break;
+ case mode_16bit:
+ strcpy (buf + j, "0x8000");
+ break;
+ }
+ return;
+ }
+ }
+
+ buf[j++] = '0';
+ buf[j++] = 'x';
+
+ sprintf_vma (tmp, (bfd_vma) val);
+ for (i = 0; tmp[i] == '0'; i++)
+ continue;
+ if (tmp[i] == '\0')
+ i--;
+ strcpy (buf + j, tmp + i);
+}
+static void
+intel_operand_size (int bytemode, int sizeflag)
+{
+ if (vex.evex
+ && vex.b
+ && (bytemode == x_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ {
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ return;
+ }
switch (bytemode)
{
case b_mode:
case b_swap_mode:
- USED_REX (0);
- if (rex)
- names = names8rex;
- else
- names = names8;
- break;
- case w_mode:
- names = names16;
- break;
- case d_mode:
- case dw_mode:
+ case dqb_mode:
case db_mode:
- names = names32;
- break;
- case q_mode:
- names = names64;
- break;
- case m_mode:
- case v_bnd_mode:
- names = address_mode == mode_64bit ? names64 : names32;
+ oappend ("BYTE PTR ");
break;
- case bnd_mode:
- case bnd_swap_mode:
- if (reg > 0x3)
- {
- oappend ("(bad)");
- return;
- }
- names = names_bnd;
+ case w_mode:
+ case dw_mode:
+ case dqw_mode:
+ oappend ("WORD PTR ");
break;
case indir_v_mode:
if (address_mode == mode_64bit && isa64 == intel64)
{
- names = names64;
+ oappend ("QWORD PTR ");
break;
}
/* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
- names = names64;
+ oappend ("QWORD PTR ");
break;
}
- bytemode = v_mode;
/* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
- case dqa_mode:
USED_REX (REX_W);
if (rex & REX_W)
- names = names64;
+ oappend ("QWORD PTR ");
else
{
- if ((sizeflag & DFLAG)
- || (bytemode != v_mode
- && bytemode != v_swap_mode))
- names = names32;
+ if ((sizeflag & DFLAG) || bytemode == dq_mode)
+ oappend ("DWORD PTR ");
else
- names = names16;
+ oappend ("WORD PTR ");
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
- case va_mode:
- names = (address_mode == mode_64bit
- ? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- names = (address_mode == mode_16bit
- ? names16 : names);
- else
- {
- /* Remove "addr16/addr32". */
- all_prefixes[last_addr_prefix] = 0;
- names = (address_mode != mode_32bit
- ? names32 : names16);
- used_prefixes |= PREFIX_ADDR;
- }
+ case z_mode:
+ if ((rex & REX_W) || (sizeflag & DFLAG))
+ *obufp++ = 'D';
+ oappend ("WORD PTR ");
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
break;
- case mask_bd_mode:
- case mask_mode:
- if (reg > 0x7)
- {
- oappend ("(bad)");
- return;
- }
- names = names_mask;
+ case a_mode:
+ if (sizeflag & DFLAG)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
break;
- case 0:
- return;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
- oappend (names[reg]);
-}
-
-static void
-OP_E_memory (int bytemode, int sizeflag)
-{
- bfd_vma disp = 0;
- int add = (rex & REX_B) ? 8 : 0;
- int riprel = 0;
- int shift;
-
- if (vex.evex)
- {
- /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
- if (vex.b
- && bytemode != x_mode
- && bytemode != xmmq_mode
- && bytemode != evex_half_bcst_xmmq_mode)
- {
- BadOp ();
- return;
- }
- switch (bytemode)
- {
- case dqw_mode:
- case dw_mode:
- shift = 1;
- break;
- case dqb_mode:
- case db_mode:
- shift = 0;
- break;
- case vex_vsib_d_w_dq_mode:
- case vex_vsib_d_w_d_mode:
- case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
- case evex_x_gscat_mode:
- case xmm_mdq_mode:
- shift = vex.w ? 3 : 2;
- break;
- case x_mode:
- case evex_half_bcst_xmmq_mode:
- case xmmq_mode:
- if (vex.b)
- {
- shift = vex.w ? 3 : 2;
- break;
- }
- /* Fall through. */
- case xmmqd_mode:
- case xmmdw_mode:
- case ymmq_mode:
- case evex_x_nobcst_mode:
- case x_swap_mode:
- switch (vex.length)
- {
- case 128:
- shift = 4;
- break;
- case 256:
- shift = 5;
- break;
- case 512:
- shift = 6;
- break;
- default:
- abort ();
- }
- break;
- case ymm_mode:
- shift = 5;
- break;
- case xmm_mode:
- shift = 4;
- break;
- case xmm_mq_mode:
- case q_mode:
- case q_scalar_mode:
- case q_swap_mode:
- case q_scalar_swap_mode:
- shift = 3;
- break;
- case dqd_mode:
- case xmm_md_mode:
- case d_mode:
- case d_scalar_mode:
- case d_swap_mode:
- case d_scalar_swap_mode:
- shift = 2;
- break;
- case w_scalar_mode:
- case xmm_mw_mode:
- shift = 1;
- break;
- case b_scalar_mode:
- case xmm_mb_mode:
- shift = 0;
- break;
- case dqa_mode:
- shift = address_mode == mode_64bit ? 3 : 2;
- break;
- default:
- abort ();
- }
- /* Make necessary corrections to shift for modes that need it.
- For these modes we currently have shift 4, 5 or 6 depending on
- vex.length (it corresponds to xmmword, ymmword or zmmword
- operand). We might want to make it 3, 4 or 5 (e.g. for
- xmmq_mode). In case of broadcast enabled the corrections
- aren't needed, as element size is always 32 or 64 bits. */
- if (!vex.b
- && (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode))
- shift -= 1;
- else if (bytemode == xmmqd_mode)
- shift -= 2;
- else if (bytemode == xmmdw_mode)
- shift -= 3;
- else if (bytemode == ymmq_mode && vex.length == 128)
- shift -= 1;
- }
- else
- shift = 0;
-
- USED_REX (REX_B);
- if (intel_syntax)
- intel_operand_size (bytemode, sizeflag);
- append_seg ();
-
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
- /* 32/64 bit address mode */
- int havedisp;
- int havesib;
- int havebase;
- int haveindex;
- int needindex;
- int needaddr32;
- int base, rbase;
- int vindex = 0;
- int scale = 0;
- int addr32flag = !((sizeflag & AFLAG)
- || bytemode == v_bnd_mode
- || bytemode == v_bndmk_mode
- || bytemode == bnd_mode
- || bytemode == bnd_swap_mode);
- const char **indexes64 = names64;
- const char **indexes32 = names32;
-
- havesib = 0;
- havebase = 1;
- haveindex = 0;
- base = modrm.rm;
-
- if (base == 4)
- {
- havesib = 1;
- vindex = sib.index;
- USED_REX (REX_X);
- if (rex & REX_X)
- vindex += 8;
- switch (bytemode)
- {
- case vex_vsib_d_w_dq_mode:
- case vex_vsib_d_w_d_mode:
- case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
- if (!need_vex)
- abort ();
- if (vex.evex)
- {
- if (!vex.v)
- vindex += 16;
- }
-
- haveindex = 1;
- switch (vex.length)
- {
- case 128:
- indexes64 = indexes32 = names_xmm;
- break;
- case 256:
- if (!vex.w
- || bytemode == vex_vsib_q_w_dq_mode
- || bytemode == vex_vsib_q_w_d_mode)
- indexes64 = indexes32 = names_ymm;
- else
- indexes64 = indexes32 = names_xmm;
- break;
- case 512:
- if (!vex.w
- || bytemode == vex_vsib_q_w_dq_mode
- || bytemode == vex_vsib_q_w_d_mode)
- indexes64 = indexes32 = names_zmm;
- else
- indexes64 = indexes32 = names_ymm;
- break;
- default:
- abort ();
- }
+ case movsxd_mode:
+ if (!(sizeflag & DFLAG) && isa64 == intel64)
+ oappend ("WORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case d_mode:
+ case d_swap_mode:
+ case dqd_mode:
+ oappend ("DWORD PTR ");
+ break;
+ case q_mode:
+ case q_swap_mode:
+ oappend ("QWORD PTR ");
+ break;
+ case m_mode:
+ if (address_mode == mode_64bit)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ break;
+ case f_mode:
+ if (sizeflag & DFLAG)
+ oappend ("FWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case t_mode:
+ oappend ("TBYTE PTR ");
+ break;
+ case x_mode:
+ case x_swap_mode:
+ case evex_x_gscat_mode:
+ case evex_x_nobcst_mode:
+ case bw_unit_mode:
+ if (need_vex)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("XMMWORD PTR ");
break;
- default:
- haveindex = vindex != 4;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
break;
+ default:
+ abort ();
}
- scale = sib.scale;
- base = sib.base;
- codep++;
}
- rbase = base + add;
+ else
+ oappend ("XMMWORD PTR ");
+ break;
+ case xmm_mode:
+ oappend ("XMMWORD PTR ");
+ break;
+ case ymm_mode:
+ oappend ("YMMWORD PTR ");
+ break;
+ case xmmq_mode:
+ case evex_half_bcst_xmmq_mode:
+ if (!need_vex)
+ abort ();
- switch (modrm.mod)
+ switch (vex.length)
{
- case 0:
- if (base == 5)
- {
- havebase = 0;
- if (address_mode == mode_64bit && !havesib)
- riprel = 1;
- disp = get32s ();
- if (riprel && bytemode == v_bndmk_mode)
- {
- oappend ("(bad)");
- return;
- }
- }
+ case 128:
+ oappend ("QWORD PTR ");
break;
- case 1:
- FETCH_DATA (the_info, codep + 1);
- disp = *codep++;
- if ((disp & 0x80) != 0)
- disp -= 0x100;
- if (vex.evex && shift > 0)
- disp <<= shift;
+ case 256:
+ oappend ("XMMWORD PTR ");
break;
- case 2:
- disp = get32s ();
+ case 512:
+ oappend ("YMMWORD PTR ");
break;
+ default:
+ abort ();
}
+ break;
+ case xmm_mb_mode:
+ if (!need_vex)
+ abort ();
- needindex = 0;
- needaddr32 = 0;
- if (havesib
- && !havebase
- && !haveindex
- && address_mode != mode_16bit)
+ switch (vex.length)
{
- if (address_mode == mode_64bit)
- {
- /* Display eiz instead of addr32. */
- needindex = addr32flag;
- needaddr32 = 1;
- }
- else
- {
- /* In 32-bit mode, we need index register to tell [offset]
- from [eiz*1 + offset]. */
- needindex = 1;
- }
+ case 128:
+ case 256:
+ case 512:
+ oappend ("BYTE PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mw_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("WORD PTR ");
+ break;
+ default:
+ abort ();
}
+ break;
+ case xmm_md_mode:
+ if (!need_vex)
+ abort ();
- havedisp = (havebase
- || needindex
- || (havesib && (haveindex || scale != 0)));
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("DWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mq_mode:
+ if (!need_vex)
+ abort ();
- if (!intel_syntax)
- if (modrm.mod != 0 || base == 5)
- {
- if (havedisp || riprel)
- print_displacement (scratchbuf, disp);
- else
- print_operand_value (scratchbuf, 1, disp);
- oappend (scratchbuf);
- if (riprel)
- {
- set_op (disp, 1);
- oappend (!addr32flag ? "(%rip)" : "(%eip)");
- }
- }
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("QWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmmdw_mode:
+ if (!need_vex)
+ abort ();
- if ((havebase || haveindex || needaddr32 || riprel)
- && (bytemode != v_bnd_mode)
- && (bytemode != v_bndmk_mode)
- && (bytemode != bnd_mode)
- && (bytemode != bnd_swap_mode))
- used_prefixes |= PREFIX_ADDR;
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("WORD PTR ");
+ break;
+ case 256:
+ oappend ("DWORD PTR ");
+ break;
+ case 512:
+ oappend ("QWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmmqd_mode:
+ if (!need_vex)
+ abort ();
- if (havedisp || (intel_syntax && riprel))
+ switch (vex.length)
{
- *obufp++ = open_char;
- if (intel_syntax && riprel)
- {
- set_op (disp, 1);
- oappend (!addr32flag ? "rip" : "eip");
- }
- *obufp = '\0';
- if (havebase)
- oappend (address_mode == mode_64bit && !addr32flag
- ? names64[rbase] : names32[rbase]);
- if (havesib)
- {
- /* ESP/RSP won't allow index. If base isn't ESP/RSP,
- print index to tell base + index from base. */
- if (scale != 0
- || needindex
- || haveindex
- || (havebase && base != ESP_REG_NUM))
- {
- if (!intel_syntax || havebase)
- {
- *obufp++ = separator_char;
- *obufp = '\0';
- }
- if (haveindex)
- oappend (address_mode == mode_64bit && !addr32flag
- ? indexes64[vindex] : indexes32[vindex]);
- else
- oappend (address_mode == mode_64bit && !addr32flag
- ? index64 : index32);
+ case 128:
+ oappend ("DWORD PTR ");
+ break;
+ case 256:
+ oappend ("QWORD PTR ");
+ break;
+ case 512:
+ oappend ("XMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymmq_mode:
+ if (!need_vex)
+ abort ();
- *obufp++ = scale_char;
- *obufp = '\0';
- sprintf (scratchbuf, "%d", 1 << scale);
- oappend (scratchbuf);
- }
- }
- if (intel_syntax
- && (disp || modrm.mod != 0 || base == 5))
- {
- if (!havedisp || (bfd_signed_vma) disp >= 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
- else if (modrm.mod != 1 && disp != -disp)
- {
- *obufp++ = '-';
- *obufp = '\0';
- disp = - (bfd_signed_vma) disp;
- }
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("QWORD PTR ");
+ break;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymmxmm_mode:
+ if (!need_vex)
+ abort ();
- if (havedisp)
- print_displacement (scratchbuf, disp);
- else
- print_operand_value (scratchbuf, 1, disp);
- oappend (scratchbuf);
- }
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case o_mode:
+ oappend ("OWORD PTR ");
+ break;
+ case vex_scalar_w_dq_mode:
+ if (!need_vex)
+ abort ();
- *obufp++ = close_char;
- *obufp = '\0';
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ break;
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_q_w_dq_mode:
+ if (!need_vex)
+ abort ();
+
+ if (!vex.evex)
+ {
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
}
- else if (intel_syntax)
+ else
{
- if (modrm.mod != 0 || base == 5)
+ switch (vex.length)
{
- if (!active_seg_prefix)
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- print_operand_value (scratchbuf, 1, disp);
- oappend (scratchbuf);
+ case 128:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
}
}
- }
- else
- {
- /* 16 bit address mode */
- used_prefixes |= prefixes & PREFIX_ADDR;
- switch (modrm.mod)
+ break;
+ case vex_vsib_q_w_d_mode:
+ case vex_vsib_d_w_d_mode:
+ if (!need_vex || !vex.evex)
+ abort ();
+
+ switch (vex.length)
{
- case 0:
- if (modrm.rm == 6)
- {
- disp = get16 ();
- if ((disp & 0x8000) != 0)
- disp -= 0x10000;
- }
+ case 128:
+ oappend ("QWORD PTR ");
break;
- case 1:
- FETCH_DATA (the_info, codep + 1);
- disp = *codep++;
- if ((disp & 0x80) != 0)
- disp -= 0x100;
- if (vex.evex && shift > 0)
- disp <<= shift;
+ case 256:
+ oappend ("XMMWORD PTR ");
break;
- case 2:
- disp = get16 ();
- if ((disp & 0x8000) != 0)
- disp -= 0x10000;
+ case 512:
+ oappend ("YMMWORD PTR ");
break;
+ default:
+ abort ();
}
- if (!intel_syntax)
- if (modrm.mod != 0 || modrm.rm == 6)
- {
- print_displacement (scratchbuf, disp);
- oappend (scratchbuf);
- }
+ break;
+ case mask_bd_mode:
+ if (!need_vex || vex.length != 128)
+ abort ();
+ if (vex.w)
+ oappend ("DWORD PTR ");
+ else
+ oappend ("BYTE PTR ");
+ break;
+ case mask_mode:
+ if (!need_vex)
+ abort ();
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("WORD PTR ");
+ break;
+ case v_bnd_mode:
+ case v_bndmk_mode:
+ default:
+ break;
+ }
+}
- if (modrm.mod != 0 || modrm.rm != 6)
+static void
+OP_E_register (int bytemode, int sizeflag)
+{
+ int reg = modrm.rm;
+ const char **names;
+
+ USED_REX (REX_B);
+ if ((rex & REX_B))
+ reg += 8;
+
+ if ((sizeflag & SUFFIX_ALWAYS)
+ && (bytemode == b_swap_mode
+ || bytemode == bnd_swap_mode
+ || bytemode == v_swap_mode))
+ swap_operand ();
+
+ switch (bytemode)
+ {
+ case b_mode:
+ case b_swap_mode:
+ if (reg & 4)
+ USED_REX (0);
+ if (rex)
+ names = names8rex;
+ else
+ names = names8;
+ break;
+ case w_mode:
+ names = names16;
+ break;
+ case d_mode:
+ case dw_mode:
+ case db_mode:
+ names = names32;
+ break;
+ case q_mode:
+ names = names64;
+ break;
+ case m_mode:
+ case v_bnd_mode:
+ names = address_mode == mode_64bit ? names64 : names32;
+ break;
+ case bnd_mode:
+ case bnd_swap_mode:
+ if (reg > 0x3)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_bnd;
+ break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ names = names64;
+ break;
+ }
+ /* Fall through. */
+ case stack_v_mode:
+ if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ names = names64;
+ break;
+ }
+ bytemode = v_mode;
+ /* Fall through. */
+ case v_mode:
+ case v_swap_mode:
+ case dq_mode:
+ case dqb_mode:
+ case dqd_mode:
+ case dqw_mode:
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ names = names64;
+ else
+ {
+ if ((sizeflag & DFLAG)
+ || (bytemode != v_mode
+ && bytemode != v_swap_mode))
+ names = names32;
+ else
+ names = names16;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case movsxd_mode:
+ if (!(sizeflag & DFLAG) && isa64 == intel64)
+ names = names16;
+ else
+ names = names32;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case va_mode:
+ names = (address_mode == mode_64bit
+ ? names64 : names32);
+ if (!(prefixes & PREFIX_ADDR))
+ names = (address_mode == mode_16bit
+ ? names16 : names);
+ else
{
- *obufp++ = open_char;
- *obufp = '\0';
- oappend (index16[modrm.rm]);
- if (intel_syntax
- && (disp || modrm.mod != 0 || modrm.rm == 6))
- {
- if ((bfd_signed_vma) disp >= 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
- else if (modrm.mod != 1)
- {
- *obufp++ = '-';
- *obufp = '\0';
- disp = - (bfd_signed_vma) disp;
- }
-
- print_displacement (scratchbuf, disp);
- oappend (scratchbuf);
- }
-
- *obufp++ = close_char;
- *obufp = '\0';
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
}
- else if (intel_syntax)
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if (reg > 0x7)
{
- if (!active_seg_prefix)
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- print_operand_value (scratchbuf, 1, disp & 0xffff);
- oappend (scratchbuf);
+ oappend ("(bad)");
+ return;
}
+ names = names_mask;
+ break;
+ case 0:
+ return;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ return;
}
- if (vex.evex && vex.b
- && (bytemode == x_mode
- || bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode))
+ oappend (names[reg]);
+}
+
+static void
+OP_E_memory (int bytemode, int sizeflag)
+{
+ bfd_vma disp = 0;
+ int add = (rex & REX_B) ? 8 : 0;
+ int riprel = 0;
+ int shift;
+
+ if (vex.evex)
{
- if (vex.w
- || bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode)
+ /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
+ if (vex.b
+ && bytemode != x_mode
+ && bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode)
{
- switch (vex.length)
+ BadOp ();
+ return;
+ }
+ switch (bytemode)
+ {
+ case dqw_mode:
+ case dw_mode:
+ case xmm_mw_mode:
+ shift = 1;
+ break;
+ case dqb_mode:
+ case db_mode:
+ case xmm_mb_mode:
+ shift = 0;
+ break;
+ case dq_mode:
+ if (address_mode != mode_64bit)
{
- case 128:
- oappend ("{1to2}");
- break;
- case 256:
- oappend ("{1to4}");
+ case dqd_mode:
+ case xmm_md_mode:
+ case d_mode:
+ case d_swap_mode:
+ shift = 2;
break;
- case 512:
- oappend ("{1to8}");
+ }
+ /* fall through */
+ case vex_scalar_w_dq_mode:
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_d_w_d_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ case evex_x_gscat_mode:
+ shift = vex.w ? 3 : 2;
+ break;
+ case x_mode:
+ case evex_half_bcst_xmmq_mode:
+ case xmmq_mode:
+ if (vex.b)
+ {
+ shift = vex.w ? 3 : 2;
break;
- default:
- abort ();
}
- }
- else
- {
+ /* Fall through. */
+ case xmmqd_mode:
+ case xmmdw_mode:
+ case ymmq_mode:
+ case evex_x_nobcst_mode:
+ case x_swap_mode:
switch (vex.length)
{
case 128:
- oappend ("{1to4}");
+ shift = 4;
break;
case 256:
- oappend ("{1to8}");
+ shift = 5;
break;
case 512:
- oappend ("{1to16}");
+ shift = 6;
break;
default:
abort ();
}
+ /* Make necessary corrections to shift for modes that need it. */
+ if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode
+ || (bytemode == ymmq_mode && vex.length == 128))
+ shift -= 1;
+ else if (bytemode == xmmqd_mode)
+ shift -= 2;
+ else if (bytemode == xmmdw_mode)
+ shift -= 3;
+ break;
+ case ymm_mode:
+ shift = 5;
+ break;
+ case xmm_mode:
+ shift = 4;
+ break;
+ case xmm_mq_mode:
+ case q_mode:
+ case q_swap_mode:
+ shift = 3;
+ break;
+ case bw_unit_mode:
+ shift = vex.w ? 1 : 0;
+ break;
+ default:
+ abort ();
}
}
-}
-
-static void
-OP_E (int bytemode, int sizeflag)
-{
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (modrm.mod == 3)
- OP_E_register (bytemode, sizeflag);
else
- OP_E_memory (bytemode, sizeflag);
-}
+ shift = 0;
-static void
-OP_G (int bytemode, int sizeflag)
-{
- int add = 0;
- const char **names;
- USED_REX (REX_R);
- if (rex & REX_R)
- add += 8;
- switch (bytemode)
+ USED_REX (REX_B);
+ if (intel_syntax)
+ intel_operand_size (bytemode, sizeflag);
+ append_seg ();
+
+ if ((sizeflag & AFLAG) || address_mode == mode_64bit)
{
- case b_mode:
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.reg + add]);
- else
- oappend (names8[modrm.reg + add]);
- break;
- case w_mode:
- oappend (names16[modrm.reg + add]);
- break;
- case d_mode:
- case db_mode:
- case dw_mode:
- oappend (names32[modrm.reg + add]);
- break;
- case q_mode:
- oappend (names64[modrm.reg + add]);
- break;
- case bnd_mode:
- if (modrm.reg > 0x3)
+ /* 32/64 bit address mode */
+ int havedisp;
+ int havesib;
+ int havebase;
+ int haveindex;
+ int needindex;
+ int needaddr32;
+ int base, rbase;
+ int vindex = 0;
+ int scale = 0;
+ int addr32flag = !((sizeflag & AFLAG)
+ || bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode);
+ const char **indexes64 = names64;
+ const char **indexes32 = names32;
+
+ havesib = 0;
+ havebase = 1;
+ haveindex = 0;
+ base = modrm.rm;
+
+ if (base == 4)
{
- oappend ("(bad)");
- return;
+ havesib = 1;
+ vindex = sib.index;
+ USED_REX (REX_X);
+ if (rex & REX_X)
+ vindex += 8;
+ switch (bytemode)
+ {
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_d_w_d_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ if (!need_vex)
+ abort ();
+ if (vex.evex)
+ {
+ if (!vex.v)
+ vindex += 16;
+ }
+
+ haveindex = 1;
+ switch (vex.length)
+ {
+ case 128:
+ indexes64 = indexes32 = names_xmm;
+ break;
+ case 256:
+ if (!vex.w
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_vsib_q_w_d_mode)
+ indexes64 = indexes32 = names_ymm;
+ else
+ indexes64 = indexes32 = names_xmm;
+ break;
+ case 512:
+ if (!vex.w
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_vsib_q_w_d_mode)
+ indexes64 = indexes32 = names_zmm;
+ else
+ indexes64 = indexes32 = names_ymm;
+ break;
+ default:
+ abort ();
+ }
+ break;
+ default:
+ haveindex = vindex != 4;
+ break;
+ }
+ scale = sib.scale;
+ base = sib.base;
+ codep++;
}
- oappend (names_bnd[modrm.reg]);
- break;
- case v_mode:
- case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.reg + add]);
else
{
- if ((sizeflag & DFLAG) || bytemode != v_mode)
- oappend (names32[modrm.reg + add]);
- else
- oappend (names16[modrm.reg + add]);
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case va_mode:
- names = (address_mode == mode_64bit
- ? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- {
- if (address_mode == mode_16bit)
- names = names16;
+ /* mandatory non-vector SIB must have sib */
+ if (bytemode == vex_sibmem_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
}
- else
+ rbase = base + add;
+
+ switch (modrm.mod)
{
- /* Remove "addr16/addr32". */
- all_prefixes[last_addr_prefix] = 0;
- names = (address_mode != mode_32bit
- ? names32 : names16);
- used_prefixes |= PREFIX_ADDR;
+ case 0:
+ if (base == 5)
+ {
+ havebase = 0;
+ if (address_mode == mode_64bit && !havesib)
+ riprel = 1;
+ disp = get32s ();
+ if (riprel && bytemode == v_bndmk_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ }
+ break;
+ case 1:
+ FETCH_DATA (the_info, codep + 1);
+ disp = *codep++;
+ if ((disp & 0x80) != 0)
+ disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
+ break;
+ case 2:
+ disp = get32s ();
+ break;
}
- oappend (names[modrm.reg + add]);
- break;
- case m_mode:
- if (address_mode == mode_64bit)
- oappend (names64[modrm.reg + add]);
- else
- oappend (names32[modrm.reg + add]);
- break;
- case mask_bd_mode:
- case mask_mode:
- if ((modrm.reg + add) > 0x7)
+
+ needindex = 0;
+ needaddr32 = 0;
+ if (havesib
+ && !havebase
+ && !haveindex
+ && address_mode != mode_16bit)
{
- oappend ("(bad)");
- return;
+ if (address_mode == mode_64bit)
+ {
+ /* Display eiz instead of addr32. */
+ needindex = addr32flag;
+ needaddr32 = 1;
+ }
+ else
+ {
+ /* In 32-bit mode, we need index register to tell [offset]
+ from [eiz*1 + offset]. */
+ needindex = 1;
+ }
}
- oappend (names_mask[modrm.reg + add]);
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
-}
-
-static bfd_vma
-get64 (void)
-{
- bfd_vma x;
-#ifdef BFD64
- unsigned int a;
- unsigned int b;
-
- FETCH_DATA (the_info, codep + 8);
- a = *codep++ & 0xff;
- a |= (*codep++ & 0xff) << 8;
- a |= (*codep++ & 0xff) << 16;
- a |= (*codep++ & 0xffu) << 24;
- b = *codep++ & 0xff;
- b |= (*codep++ & 0xff) << 8;
- b |= (*codep++ & 0xff) << 16;
- b |= (*codep++ & 0xffu) << 24;
- x = a + ((bfd_vma) b << 32);
-#else
- abort ();
- x = 0;
-#endif
- return x;
-}
-
-static bfd_signed_vma
-get32 (void)
-{
- bfd_signed_vma x = 0;
-
- FETCH_DATA (the_info, codep + 4);
- x = *codep++ & (bfd_signed_vma) 0xff;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
- return x;
-}
-
-static bfd_signed_vma
-get32s (void)
-{
- bfd_signed_vma x = 0;
-
- FETCH_DATA (the_info, codep + 4);
- x = *codep++ & (bfd_signed_vma) 0xff;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
- x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
+ havedisp = (havebase
+ || needindex
+ || (havesib && (haveindex || scale != 0)));
- return x;
-}
+ if (!intel_syntax)
+ if (modrm.mod != 0 || base == 5)
+ {
+ if (havedisp || riprel)
+ print_displacement (scratchbuf, disp);
+ else
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
+ if (riprel)
+ {
+ set_op (disp, 1);
+ oappend (!addr32flag ? "(%rip)" : "(%eip)");
+ }
+ }
-static int
-get16 (void)
-{
- int x = 0;
+ if ((havebase || haveindex || needindex || needaddr32 || riprel)
+ && (address_mode != mode_64bit
+ || ((bytemode != v_bnd_mode)
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))))
+ used_prefixes |= PREFIX_ADDR;
- FETCH_DATA (the_info, codep + 2);
- x = *codep++ & 0xff;
- x |= (*codep++ & 0xff) << 8;
- return x;
-}
+ if (havedisp || (intel_syntax && riprel))
+ {
+ *obufp++ = open_char;
+ if (intel_syntax && riprel)
+ {
+ set_op (disp, 1);
+ oappend (!addr32flag ? "rip" : "eip");
+ }
+ *obufp = '\0';
+ if (havebase)
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? names64[rbase] : names32[rbase]);
+ if (havesib)
+ {
+ /* ESP/RSP won't allow index. If base isn't ESP/RSP,
+ print index to tell base + index from base. */
+ if (scale != 0
+ || needindex
+ || haveindex
+ || (havebase && base != ESP_REG_NUM))
+ {
+ if (!intel_syntax || havebase)
+ {
+ *obufp++ = separator_char;
+ *obufp = '\0';
+ }
+ if (haveindex)
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? indexes64[vindex] : indexes32[vindex]);
+ else
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? index64 : index32);
-static void
-set_op (bfd_vma op, int riprel)
-{
- op_index[op_ad] = op_ad;
- if (address_mode == mode_64bit)
- {
- op_address[op_ad] = op;
- op_riprel[op_ad] = riprel;
- }
- else
- {
- /* Mask to get a 32-bit address. */
- op_address[op_ad] = op & 0xffffffff;
- op_riprel[op_ad] = riprel & 0xffffffff;
- }
-}
+ *obufp++ = scale_char;
+ *obufp = '\0';
+ sprintf (scratchbuf, "%d", 1 << scale);
+ oappend (scratchbuf);
+ }
+ }
+ if (intel_syntax
+ && (disp || modrm.mod != 0 || base == 5))
+ {
+ if (!havedisp || (bfd_signed_vma) disp >= 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (modrm.mod != 1 && disp != -disp)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
-static void
-OP_REG (int code, int sizeflag)
-{
- const char *s;
- int add;
+ if (havedisp)
+ print_displacement (scratchbuf, disp);
+ else
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
+ }
- switch (code)
+ *obufp++ = close_char;
+ *obufp = '\0';
+ }
+ else if (intel_syntax)
+ {
+ if (modrm.mod != 0 || base == 5)
+ {
+ if (!active_seg_prefix)
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
+ }
+ }
+ }
+ else if (bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode)
{
- case es_reg: case ss_reg: case cs_reg:
- case ds_reg: case fs_reg: case gs_reg:
- oappend (names_seg[code - es_reg]);
+ oappend ("(bad)");
return;
}
-
- USED_REX (REX_B);
- if (rex & REX_B)
- add = 8;
else
- add = 0;
-
- switch (code)
{
- case ax_reg: case cx_reg: case dx_reg: case bx_reg:
- case sp_reg: case bp_reg: case si_reg: case di_reg:
- s = names16[code - ax_reg + add];
- break;
- case al_reg: case ah_reg: case cl_reg: case ch_reg:
- case dl_reg: case dh_reg: case bl_reg: case bh_reg:
- USED_REX (0);
- if (rex)
- s = names8rex[code - al_reg + add];
- else
- s = names8[code - al_reg];
- break;
- case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
- case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
- if (address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
+ /* 16 bit address mode */
+ used_prefixes |= prefixes & PREFIX_ADDR;
+ switch (modrm.mod)
{
- s = names64[code - rAX_reg + add];
+ case 0:
+ if (modrm.rm == 6)
+ {
+ disp = get16 ();
+ if ((disp & 0x8000) != 0)
+ disp -= 0x10000;
+ }
+ break;
+ case 1:
+ FETCH_DATA (the_info, codep + 1);
+ disp = *codep++;
+ if ((disp & 0x80) != 0)
+ disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
+ break;
+ case 2:
+ disp = get16 ();
+ if ((disp & 0x8000) != 0)
+ disp -= 0x10000;
break;
}
- code += eAX_reg - rAX_reg;
- /* Fall through. */
- case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
- case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
- USED_REX (REX_W);
- if (rex & REX_W)
- s = names64[code - eAX_reg + add];
- else
+
+ if (!intel_syntax)
+ if (modrm.mod != 0 || modrm.rm == 6)
+ {
+ print_displacement (scratchbuf, disp);
+ oappend (scratchbuf);
+ }
+
+ if (modrm.mod != 0 || modrm.rm != 6)
{
- if (sizeflag & DFLAG)
- s = names32[code - eAX_reg + add];
- else
- s = names16[code - eAX_reg + add];
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- default:
- s = INTERNAL_DISASSEMBLER_ERROR;
- break;
- }
- oappend (s);
-}
+ *obufp++ = open_char;
+ *obufp = '\0';
+ oappend (index16[modrm.rm]);
+ if (intel_syntax
+ && (disp || modrm.mod != 0 || modrm.rm == 6))
+ {
+ if ((bfd_signed_vma) disp >= 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (modrm.mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
-static void
-OP_IMREG (int code, int sizeflag)
-{
- const char *s;
+ print_displacement (scratchbuf, disp);
+ oappend (scratchbuf);
+ }
- switch (code)
- {
- case indir_dx_reg:
- if (intel_syntax)
- s = "dx";
- else
- s = "(%dx)";
- break;
- case ax_reg: case cx_reg: case dx_reg: case bx_reg:
- case sp_reg: case bp_reg: case si_reg: case di_reg:
- s = names16[code - ax_reg];
- break;
- case es_reg: case ss_reg: case cs_reg:
- case ds_reg: case fs_reg: case gs_reg:
- s = names_seg[code - es_reg];
- break;
- case al_reg: case ah_reg: case cl_reg: case ch_reg:
- case dl_reg: case dh_reg: case bl_reg: case bh_reg:
- USED_REX (0);
- if (rex)
- s = names8rex[code - al_reg];
- else
- s = names8[code - al_reg];
- break;
- case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
- case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
- USED_REX (REX_W);
- if (rex & REX_W)
- s = names64[code - eAX_reg];
- else
+ *obufp++ = close_char;
+ *obufp = '\0';
+ }
+ else if (intel_syntax)
{
- if (sizeflag & DFLAG)
- s = names32[code - eAX_reg];
- else
- s = names16[code - eAX_reg];
- used_prefixes |= (prefixes & PREFIX_DATA);
+ if (!active_seg_prefix)
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp & 0xffff);
+ oappend (scratchbuf);
}
- break;
- case z_mode_ax_reg:
- if ((rex & REX_W) || (sizeflag & DFLAG))
- s = *names32;
- else
- s = *names16;
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- default:
- s = INTERNAL_DISASSEMBLER_ERROR;
- break;
}
- oappend (s);
-}
-
-static void
-OP_I (int bytemode, int sizeflag)
-{
- bfd_signed_vma op;
- bfd_signed_vma mask = -1;
-
- switch (bytemode)
+ if (vex.evex && vex.b
+ && (bytemode == x_mode
+ || bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
{
- case b_mode:
- FETCH_DATA (the_info, codep + 1);
- op = *codep++;
- mask = 0xff;
- break;
- case q_mode:
- if (address_mode == mode_64bit)
+ if (vex.w
+ || bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
{
- op = get32s ();
- break;
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to2}");
+ break;
+ case 256:
+ oappend ("{1to4}");
+ break;
+ case 512:
+ oappend ("{1to8}");
+ break;
+ default:
+ abort ();
+ }
}
- /* Fall through. */
- case v_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- op = get32s ();
else
{
- if (sizeflag & DFLAG)
- {
- op = get32 ();
- mask = 0xffffffff;
- }
- else
+ switch (vex.length)
{
- op = get16 ();
- mask = 0xfffff;
+ case 128:
+ oappend ("{1to4}");
+ break;
+ case 256:
+ oappend ("{1to8}");
+ break;
+ case 512:
+ oappend ("{1to16}");
+ break;
+ default:
+ abort ();
}
- used_prefixes |= (prefixes & PREFIX_DATA);
}
- break;
- case w_mode:
- mask = 0xfffff;
- op = get16 ();
- break;
- case const_1_mode:
- if (intel_syntax)
- oappend ("1");
- return;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
}
-
- op &= mask;
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, op);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
}
static void
-OP_I64 (int bytemode, int sizeflag)
+OP_E (int bytemode, int sizeflag)
{
- bfd_signed_vma op;
- bfd_signed_vma mask = -1;
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
- if (address_mode != mode_64bit)
- {
- OP_I (bytemode, sizeflag);
- return;
- }
+ if (modrm.mod == 3)
+ OP_E_register (bytemode, sizeflag);
+ else
+ OP_E_memory (bytemode, sizeflag);
+}
+static void
+OP_G (int bytemode, int sizeflag)
+{
+ int add = 0;
+ const char **names;
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ add += 8;
switch (bytemode)
{
case b_mode:
- FETCH_DATA (the_info, codep + 1);
- op = *codep++;
- mask = 0xff;
+ if (modrm.reg & 4)
+ USED_REX (0);
+ if (rex)
+ oappend (names8rex[modrm.reg + add]);
+ else
+ oappend (names8[modrm.reg + add]);
+ break;
+ case w_mode:
+ oappend (names16[modrm.reg + add]);
+ break;
+ case d_mode:
+ case db_mode:
+ case dw_mode:
+ oappend (names32[modrm.reg + add]);
+ break;
+ case q_mode:
+ oappend (names64[modrm.reg + add]);
+ break;
+ case bnd_mode:
+ if (modrm.reg > 0x3)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ oappend (names_bnd[modrm.reg]);
break;
case v_mode:
+ case dq_mode:
+ case dqb_mode:
+ case dqd_mode:
+ case dqw_mode:
+ case movsxd_mode:
USED_REX (REX_W);
if (rex & REX_W)
- op = get64 ();
+ oappend (names64[modrm.reg + add]);
else
{
- if (sizeflag & DFLAG)
- {
- op = get32 ();
- mask = 0xffffffff;
- }
+ if ((sizeflag & DFLAG)
+ || (bytemode != v_mode && bytemode != movsxd_mode))
+ oappend (names32[modrm.reg + add]);
else
- {
- op = get16 ();
- mask = 0xfffff;
- }
+ oappend (names16[modrm.reg + add]);
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
- case w_mode:
- mask = 0xfffff;
- op = get16 ();
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
-
- op &= mask;
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, op);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
-}
-
-static void
-OP_sI (int bytemode, int sizeflag)
-{
- bfd_signed_vma op;
-
- switch (bytemode)
- {
- case b_mode:
- case b_T_mode:
- FETCH_DATA (the_info, codep + 1);
- op = *codep++;
- if ((op & 0x80) != 0)
- op -= 0x100;
- if (bytemode == b_T_mode)
+ case va_mode:
+ names = (address_mode == mode_64bit
+ ? names64 : names32);
+ if (!(prefixes & PREFIX_ADDR))
{
- if (address_mode != mode_64bit
- || !((sizeflag & DFLAG) || (rex & REX_W)))
- {
- /* The operand-size prefix is overridden by a REX prefix. */
- if ((sizeflag & DFLAG) || (rex & REX_W))
- op &= 0xffffffff;
- else
- op &= 0xffff;
- }
+ if (address_mode == mode_16bit)
+ names = names16;
}
else
{
- if (!(rex & REX_W))
- {
- if (sizeflag & DFLAG)
- op &= 0xffffffff;
- else
- op &= 0xffff;
- }
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
}
+ oappend (names[modrm.reg + add]);
break;
- case v_mode:
- /* The operand-size prefix is overridden by a REX prefix. */
- if ((sizeflag & DFLAG) || (rex & REX_W))
- op = get32s ();
+ case m_mode:
+ if (address_mode == mode_64bit)
+ oappend (names64[modrm.reg + add]);
else
- op = get16 ();
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
-
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, op);
- oappend_maybe_intel (scratchbuf);
-}
-
-static void
-OP_J (int bytemode, int sizeflag)
-{
- bfd_vma disp;
- bfd_vma mask = -1;
- bfd_vma segment = 0;
-
- switch (bytemode)
- {
- case b_mode:
- FETCH_DATA (the_info, codep + 1);
- disp = *codep++;
- if ((disp & 0x80) != 0)
- disp -= 0x100;
+ oappend (names32[modrm.reg + add]);
break;
- case v_mode:
- if (isa64 == amd64)
- USED_REX (REX_W);
- if ((sizeflag & DFLAG)
- || (address_mode == mode_64bit
- && (isa64 != amd64 || (rex & REX_W))))
- disp = get32s ();
- else
+ case mask_bd_mode:
+ case mask_mode:
+ if ((modrm.reg + add) > 0x7)
{
- disp = get16 ();
- if ((disp & 0x8000) != 0)
- disp -= 0x10000;
- /* In 16bit mode, address is wrapped around at 64k within
- the same segment. Otherwise, a data16 prefix on a jump
- instruction means that the pc is masked to 16 bits after
- the displacement is added! */
- mask = 0xffff;
- if ((prefixes & PREFIX_DATA) == 0)
- segment = ((start_pc + (codep - start_codep))
- & ~((bfd_vma) 0xffff));
+ oappend ("(bad)");
+ return;
}
- if (address_mode != mode_64bit
- || (isa64 == amd64 && !(rex & REX_W)))
- used_prefixes |= (prefixes & PREFIX_DATA);
+ oappend (names_mask[modrm.reg + add]);
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
+ break;
}
- disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
- set_op (disp, 0);
- print_operand_value (scratchbuf, 1, disp);
- oappend (scratchbuf);
-}
-
-static void
-OP_SEG (int bytemode, int sizeflag)
-{
- if (bytemode == w_mode)
- oappend (names_seg[modrm.reg]);
- else
- OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
}
-static void
-OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
+static bfd_vma
+get64 (void)
{
- int seg, offset;
+ bfd_vma x;
+#ifdef BFD64
+ unsigned int a;
+ unsigned int b;
- if (sizeflag & DFLAG)
- {
- offset = get32 ();
- seg = get16 ();
- }
- else
- {
- offset = get16 ();
- seg = get16 ();
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (intel_syntax)
- sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
- else
- sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
- oappend (scratchbuf);
+ FETCH_DATA (the_info, codep + 8);
+ a = *codep++ & 0xff;
+ a |= (*codep++ & 0xff) << 8;
+ a |= (*codep++ & 0xff) << 16;
+ a |= (*codep++ & 0xffu) << 24;
+ b = *codep++ & 0xff;
+ b |= (*codep++ & 0xff) << 8;
+ b |= (*codep++ & 0xff) << 16;
+ b |= (*codep++ & 0xffu) << 24;
+ x = a + ((bfd_vma) b << 32);
+#else
+ abort ();
+ x = 0;
+#endif
+ return x;
}
-static void
-OP_OFF (int bytemode, int sizeflag)
+static bfd_signed_vma
+get32 (void)
{
- bfd_vma off;
-
- if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
- intel_operand_size (bytemode, sizeflag);
- append_seg ();
-
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- off = get32 ();
- else
- off = get16 ();
+ bfd_signed_vma x = 0;
- if (intel_syntax)
- {
- if (!active_seg_prefix)
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- }
- print_operand_value (scratchbuf, 1, off);
- oappend (scratchbuf);
+ FETCH_DATA (the_info, codep + 4);
+ x = *codep++ & (bfd_signed_vma) 0xff;
+ x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
+ x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
+ x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
+ return x;
}
-static void
-OP_OFF64 (int bytemode, int sizeflag)
+static bfd_signed_vma
+get32s (void)
{
- bfd_vma off;
-
- if (address_mode != mode_64bit
- || (prefixes & PREFIX_ADDR))
- {
- OP_OFF (bytemode, sizeflag);
- return;
- }
+ bfd_signed_vma x = 0;
- if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
- intel_operand_size (bytemode, sizeflag);
- append_seg ();
+ FETCH_DATA (the_info, codep + 4);
+ x = *codep++ & (bfd_signed_vma) 0xff;
+ x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
+ x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
+ x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
- off = get64 ();
+ x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
- if (intel_syntax)
- {
- if (!active_seg_prefix)
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- }
- print_operand_value (scratchbuf, 1, off);
- oappend (scratchbuf);
+ return x;
}
-static void
-ptr_reg (int code, int sizeflag)
+static int
+get16 (void)
{
- const char *s;
+ int x = 0;
- *obufp++ = open_char;
- used_prefixes |= (prefixes & PREFIX_ADDR);
- if (address_mode == mode_64bit)
- {
- if (!(sizeflag & AFLAG))
- s = names32[code - eAX_reg];
- else
- s = names64[code - eAX_reg];
- }
- else if (sizeflag & AFLAG)
- s = names32[code - eAX_reg];
- else
- s = names16[code - eAX_reg];
- oappend (s);
- *obufp++ = close_char;
- *obufp = 0;
+ FETCH_DATA (the_info, codep + 2);
+ x = *codep++ & 0xff;
+ x |= (*codep++ & 0xff) << 8;
+ return x;
}
static void
-OP_ESreg (int code, int sizeflag)
+set_op (bfd_vma op, int riprel)
{
- if (intel_syntax)
+ op_index[op_ad] = op_ad;
+ if (address_mode == mode_64bit)
{
- switch (codep[-1])
- {
- case 0x6d: /* insw/insl */
- intel_operand_size (z_mode, sizeflag);
- break;
- case 0xa5: /* movsw/movsl/movsq */
- case 0xa7: /* cmpsw/cmpsl/cmpsq */
- case 0xab: /* stosw/stosl */
- case 0xaf: /* scasw/scasl */
- intel_operand_size (v_mode, sizeflag);
- break;
- default:
- intel_operand_size (b_mode, sizeflag);
- }
+ op_address[op_ad] = op;
+ op_riprel[op_ad] = riprel;
}
- oappend_maybe_intel ("%es:");
- ptr_reg (code, sizeflag);
-}
-
-static void
-OP_DSreg (int code, int sizeflag)
-{
- if (intel_syntax)
+ else
{
- switch (codep[-1])
- {
- case 0x6f: /* outsw/outsl */
- intel_operand_size (z_mode, sizeflag);
- break;
- case 0xa5: /* movsw/movsl/movsq */
- case 0xa7: /* cmpsw/cmpsl/cmpsq */
- case 0xad: /* lodsw/lodsl/lodsq */
- intel_operand_size (v_mode, sizeflag);
- break;
- default:
- intel_operand_size (b_mode, sizeflag);
- }
+ /* Mask to get a 32-bit address. */
+ op_address[op_ad] = op & 0xffffffff;
+ op_riprel[op_ad] = riprel & 0xffffffff;
}
- /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
- default segment register DS is printed. */
- if (!active_seg_prefix)
- active_seg_prefix = PREFIX_DS;
- append_seg ();
- ptr_reg (code, sizeflag);
}
static void
-OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+OP_REG (int code, int sizeflag)
{
+ const char *s;
int add;
- if (rex & REX_R)
- {
- USED_REX (REX_R);
- add = 8;
- }
- else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
+
+ switch (code)
{
- all_prefixes[last_lock_prefix] = 0;
- used_prefixes |= PREFIX_LOCK;
- add = 8;
+ case es_reg: case ss_reg: case cs_reg:
+ case ds_reg: case fs_reg: case gs_reg:
+ oappend (names_seg[code - es_reg]);
+ return;
}
- else
- add = 0;
- sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
- oappend_maybe_intel (scratchbuf);
-}
-static void
-OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int add;
- USED_REX (REX_R);
- if (rex & REX_R)
+ USED_REX (REX_B);
+ if (rex & REX_B)
add = 8;
else
add = 0;
- if (intel_syntax)
- sprintf (scratchbuf, "db%d", modrm.reg + add);
- else
- sprintf (scratchbuf, "%%db%d", modrm.reg + add);
- oappend (scratchbuf);
-}
-
-static void
-OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- sprintf (scratchbuf, "%%tr%d", modrm.reg);
- oappend_maybe_intel (scratchbuf);
-}
-
-static void
-OP_R (int bytemode, int sizeflag)
-{
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- OP_E_register (bytemode, sizeflag);
-}
-
-static void
-OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int reg = modrm.reg;
- const char **names;
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
+ switch (code)
{
- names = names_xmm;
- USED_REX (REX_R);
- if (rex & REX_R)
- reg += 8;
+ case ax_reg: case cx_reg: case dx_reg: case bx_reg:
+ case sp_reg: case bp_reg: case si_reg: case di_reg:
+ s = names16[code - ax_reg + add];
+ break;
+ case ah_reg: case ch_reg: case dh_reg: case bh_reg:
+ USED_REX (0);
+ /* Fall through. */
+ case al_reg: case cl_reg: case dl_reg: case bl_reg:
+ if (rex)
+ s = names8rex[code - al_reg + add];
+ else
+ s = names8[code - al_reg];
+ break;
+ case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
+ case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ s = names64[code - rAX_reg + add];
+ break;
+ }
+ code += eAX_reg - rAX_reg;
+ /* Fall through. */
+ case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
+ case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ s = names64[code - eAX_reg + add];
+ else
+ {
+ if (sizeflag & DFLAG)
+ s = names32[code - eAX_reg + add];
+ else
+ s = names16[code - eAX_reg + add];
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ default:
+ s = INTERNAL_DISASSEMBLER_ERROR;
+ break;
}
- else
- names = names_mm;
- oappend (names[reg]);
+ oappend (s);
}
static void
-OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+OP_IMREG (int code, int sizeflag)
{
- int reg = modrm.reg;
- const char **names;
-
- USED_REX (REX_R);
- if (rex & REX_R)
- reg += 8;
- if (vex.evex)
- {
- if (!vex.r)
- reg += 16;
- }
+ const char *s;
- if (need_vex
- && bytemode != xmm_mode
- && bytemode != xmmq_mode
- && bytemode != evex_half_bcst_xmmq_mode
- && bytemode != ymm_mode
- && bytemode != scalar_mode)
- {
- switch (vex.length)
- {
- case 128:
- names = names_xmm;
- break;
- case 256:
- if (vex.w
- || (bytemode != vex_vsib_q_w_dq_mode
- && bytemode != vex_vsib_q_w_d_mode))
- names = names_ymm;
- else
- names = names_xmm;
- break;
- case 512:
- names = names_zmm;
- break;
- default:
- abort ();
- }
- }
- else if (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode)
+ switch (code)
{
- switch (vex.length)
+ case indir_dx_reg:
+ if (intel_syntax)
+ s = "dx";
+ else
+ s = "(%dx)";
+ break;
+ case al_reg: case cl_reg:
+ s = names8[code - al_reg];
+ break;
+ case eAX_reg:
+ USED_REX (REX_W);
+ if (rex & REX_W)
{
- case 128:
- case 256:
- names = names_xmm;
+ s = *names64;
break;
- case 512:
- names = names_ymm;
- break;
- default:
- abort ();
}
+ /* Fall through. */
+ case z_mode_ax_reg:
+ if ((rex & REX_W) || (sizeflag & DFLAG))
+ s = *names32;
+ else
+ s = *names16;
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ default:
+ s = INTERNAL_DISASSEMBLER_ERROR;
+ break;
}
- else if (bytemode == ymm_mode)
- names = names_ymm;
- else
- names = names_xmm;
- oappend (names[reg]);
+ oappend (s);
}
static void
-OP_EM (int bytemode, int sizeflag)
+OP_I (int bytemode, int sizeflag)
{
- int reg;
- const char **names;
+ bfd_signed_vma op;
+ bfd_signed_vma mask = -1;
- if (modrm.mod != 3)
+ switch (bytemode)
{
- if (intel_syntax
- && (bytemode == v_mode || bytemode == v_swap_mode))
+ case b_mode:
+ FETCH_DATA (the_info, codep + 1);
+ op = *codep++;
+ mask = 0xff;
+ break;
+ case v_mode:
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ op = get32s ();
+ else
{
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
+ if (sizeflag & DFLAG)
+ {
+ op = get32 ();
+ mask = 0xffffffff;
+ }
+ else
+ {
+ op = get16 ();
+ mask = 0xfffff;
+ }
used_prefixes |= (prefixes & PREFIX_DATA);
}
- OP_E (bytemode, sizeflag);
+ break;
+ case d_mode:
+ mask = 0xffffffff;
+ op = get32 ();
+ break;
+ case w_mode:
+ mask = 0xfffff;
+ op = get16 ();
+ break;
+ case const_1_mode:
+ if (intel_syntax)
+ oappend ("1");
+ return;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
return;
}
- if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
- swap_operand ();
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- used_prefixes |= (prefixes & PREFIX_DATA);
- reg = modrm.rm;
- if (prefixes & PREFIX_DATA)
- {
- names = names_xmm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- }
- else
- names = names_mm;
- oappend (names[reg]);
+ op &= mask;
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, op);
+ oappend_maybe_intel (scratchbuf);
+ scratchbuf[0] = '\0';
}
-/* cvt* are the only instructions in sse2 which have
- both SSE and MMX operands and also have 0x66 prefix
- in their opcode. 0x66 was originally used to differentiate
- between SSE and MMX instruction(operands). So we have to handle the
- cvt* separately using OP_EMC and OP_MXC */
static void
-OP_EMC (int bytemode, int sizeflag)
+OP_I64 (int bytemode, int sizeflag)
{
- if (modrm.mod != 3)
+ if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
{
- if (intel_syntax && bytemode == v_mode)
- {
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- OP_E (bytemode, sizeflag);
+ OP_I (bytemode, sizeflag);
return;
}
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- used_prefixes |= (prefixes & PREFIX_DATA);
- oappend (names_mm[modrm.rm]);
-}
+ USED_REX (REX_W);
-static void
-OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- used_prefixes |= (prefixes & PREFIX_DATA);
- oappend (names_mm[modrm.reg]);
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, get64 ());
+ oappend_maybe_intel (scratchbuf);
+ scratchbuf[0] = '\0';
}
static void
-OP_EX (int bytemode, int sizeflag)
+OP_sI (int bytemode, int sizeflag)
{
- int reg;
- const char **names;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (modrm.mod != 3)
- {
- OP_E_memory (bytemode, sizeflag);
- return;
- }
-
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- if (vex.evex)
- {
- USED_REX (REX_X);
- if ((rex & REX_X))
- reg += 16;
- }
-
- if ((sizeflag & SUFFIX_ALWAYS)
- && (bytemode == x_swap_mode
- || bytemode == d_swap_mode
- || bytemode == d_scalar_swap_mode
- || bytemode == q_swap_mode
- || bytemode == q_scalar_swap_mode))
- swap_operand ();
+ bfd_signed_vma op;
- if (need_vex
- && bytemode != xmm_mode
- && bytemode != xmmdw_mode
- && bytemode != xmmqd_mode
- && bytemode != xmm_mb_mode
- && bytemode != xmm_mw_mode
- && bytemode != xmm_md_mode
- && bytemode != xmm_mq_mode
- && bytemode != xmm_mdq_mode
- && bytemode != xmmq_mode
- && bytemode != evex_half_bcst_xmmq_mode
- && bytemode != ymm_mode
- && bytemode != d_scalar_mode
- && bytemode != d_scalar_swap_mode
- && bytemode != q_scalar_mode
- && bytemode != q_scalar_swap_mode
- && bytemode != vex_scalar_w_dq_mode)
+ switch (bytemode)
{
- switch (vex.length)
+ case b_mode:
+ case b_T_mode:
+ FETCH_DATA (the_info, codep + 1);
+ op = *codep++;
+ if ((op & 0x80) != 0)
+ op -= 0x100;
+ if (bytemode == b_T_mode)
{
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- case 512:
- names = names_zmm;
- break;
- default:
- abort ();
+ if (address_mode != mode_64bit
+ || !((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ /* The operand-size prefix is overridden by a REX prefix. */
+ if ((sizeflag & DFLAG) || (rex & REX_W))
+ op &= 0xffffffff;
+ else
+ op &= 0xffff;
+ }
}
- }
- else if (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode)
- {
- switch (vex.length)
+ else
{
- case 128:
- case 256:
- names = names_xmm;
- break;
- case 512:
- names = names_ymm;
- break;
- default:
- abort ();
+ if (!(rex & REX_W))
+ {
+ if (sizeflag & DFLAG)
+ op &= 0xffffffff;
+ else
+ op &= 0xffff;
+ }
}
+ break;
+ case v_mode:
+ /* The operand-size prefix is overridden by a REX prefix. */
+ if ((sizeflag & DFLAG) || (rex & REX_W))
+ op = get32s ();
+ else
+ op = get16 ();
+ break;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ return;
}
- else if (bytemode == ymm_mode)
- names = names_ymm;
- else
- names = names_xmm;
- oappend (names[reg]);
+
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, op);
+ oappend_maybe_intel (scratchbuf);
}
static void
-OP_MS (int bytemode, int sizeflag)
+OP_J (int bytemode, int sizeflag)
{
- if (modrm.mod == 3)
- OP_EM (bytemode, sizeflag);
- else
- BadOp ();
+ bfd_vma disp;
+ bfd_vma mask = -1;
+ bfd_vma segment = 0;
+
+ switch (bytemode)
+ {
+ case b_mode:
+ FETCH_DATA (the_info, codep + 1);
+ disp = *codep++;
+ if ((disp & 0x80) != 0)
+ disp -= 0x100;
+ break;
+ case v_mode:
+ if (isa64 != intel64)
+ case dqw_mode:
+ USED_REX (REX_W);
+ if ((sizeflag & DFLAG)
+ || (address_mode == mode_64bit
+ && ((isa64 == intel64 && bytemode != dqw_mode)
+ || (rex & REX_W))))
+ disp = get32s ();
+ else
+ {
+ disp = get16 ();
+ if ((disp & 0x8000) != 0)
+ disp -= 0x10000;
+ /* In 16bit mode, address is wrapped around at 64k within
+ the same segment. Otherwise, a data16 prefix on a jump
+ instruction means that the pc is masked to 16 bits after
+ the displacement is added! */
+ mask = 0xffff;
+ if ((prefixes & PREFIX_DATA) == 0)
+ segment = ((start_pc + (codep - start_codep))
+ & ~((bfd_vma) 0xffff));
+ }
+ if (address_mode != mode_64bit
+ || (isa64 != intel64 && !(rex & REX_W)))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ return;
+ }
+ disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
+ set_op (disp, 0);
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
}
static void
-OP_XS (int bytemode, int sizeflag)
+OP_SEG (int bytemode, int sizeflag)
{
- if (modrm.mod == 3)
- OP_EX (bytemode, sizeflag);
+ if (bytemode == w_mode)
+ oappend (names_seg[modrm.reg]);
else
- BadOp ();
+ OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
}
static void
-OP_M (int bytemode, int sizeflag)
+OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
{
- if (modrm.mod == 3)
- /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
- BadOp ();
+ int seg, offset;
+
+ if (sizeflag & DFLAG)
+ {
+ offset = get32 ();
+ seg = get16 ();
+ }
else
- OP_E (bytemode, sizeflag);
+ {
+ offset = get16 ();
+ seg = get16 ();
+ }
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ if (intel_syntax)
+ sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
+ else
+ sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
+ oappend (scratchbuf);
}
static void
-OP_0f07 (int bytemode, int sizeflag)
+OP_OFF (int bytemode, int sizeflag)
{
- if (modrm.mod != 3 || modrm.rm != 0)
- BadOp ();
- else
- OP_E (bytemode, sizeflag);
-}
+ bfd_vma off;
-/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
- 32bit mode and "xchg %rax,%rax" in 64bit mode. */
+ if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
+ intel_operand_size (bytemode, sizeflag);
+ append_seg ();
-static void
-NOP_Fixup1 (int bytemode, int sizeflag)
-{
- if ((prefixes & PREFIX_DATA) != 0
- || (rex != 0
- && rex != 0x48
- && address_mode == mode_64bit))
- OP_REG (bytemode, sizeflag);
+ if ((sizeflag & AFLAG) || address_mode == mode_64bit)
+ off = get32 ();
else
- strcpy (obuf, "nop");
-}
+ off = get16 ();
-static void
-NOP_Fixup2 (int bytemode, int sizeflag)
-{
- if ((prefixes & PREFIX_DATA) != 0
- || (rex != 0
- && rex != 0x48
- && address_mode == mode_64bit))
- OP_IMREG (bytemode, sizeflag);
+ if (intel_syntax)
+ {
+ if (!active_seg_prefix)
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ }
+ print_operand_value (scratchbuf, 1, off);
+ oappend (scratchbuf);
}
-static const char *const Suffix3DNow[] = {
-/* 00 */ NULL, NULL, NULL, NULL,
-/* 04 */ NULL, NULL, NULL, NULL,
-/* 08 */ NULL, NULL, NULL, NULL,
-/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
-/* 10 */ NULL, NULL, NULL, NULL,
-/* 14 */ NULL, NULL, NULL, NULL,
-/* 18 */ NULL, NULL, NULL, NULL,
-/* 1C */ "pf2iw", "pf2id", NULL, NULL,
-/* 20 */ NULL, NULL, NULL, NULL,
-/* 24 */ NULL, NULL, NULL, NULL,
-/* 28 */ NULL, NULL, NULL, NULL,
-/* 2C */ NULL, NULL, NULL, NULL,
-/* 30 */ NULL, NULL, NULL, NULL,
-/* 34 */ NULL, NULL, NULL, NULL,
-/* 38 */ NULL, NULL, NULL, NULL,
-/* 3C */ NULL, NULL, NULL, NULL,
-/* 40 */ NULL, NULL, NULL, NULL,
-/* 44 */ NULL, NULL, NULL, NULL,
-/* 48 */ NULL, NULL, NULL, NULL,
-/* 4C */ NULL, NULL, NULL, NULL,
-/* 50 */ NULL, NULL, NULL, NULL,
-/* 54 */ NULL, NULL, NULL, NULL,
-/* 58 */ NULL, NULL, NULL, NULL,
-/* 5C */ NULL, NULL, NULL, NULL,
-/* 60 */ NULL, NULL, NULL, NULL,
-/* 64 */ NULL, NULL, NULL, NULL,
-/* 68 */ NULL, NULL, NULL, NULL,
-/* 6C */ NULL, NULL, NULL, NULL,
-/* 70 */ NULL, NULL, NULL, NULL,
-/* 74 */ NULL, NULL, NULL, NULL,
-/* 78 */ NULL, NULL, NULL, NULL,
-/* 7C */ NULL, NULL, NULL, NULL,
-/* 80 */ NULL, NULL, NULL, NULL,
-/* 84 */ NULL, NULL, NULL, NULL,
-/* 88 */ NULL, NULL, "pfnacc", NULL,
-/* 8C */ NULL, NULL, "pfpnacc", NULL,
-/* 90 */ "pfcmpge", NULL, NULL, NULL,
-/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
-/* 98 */ NULL, NULL, "pfsub", NULL,
-/* 9C */ NULL, NULL, "pfadd", NULL,
-/* A0 */ "pfcmpgt", NULL, NULL, NULL,
-/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
-/* A8 */ NULL, NULL, "pfsubr", NULL,
-/* AC */ NULL, NULL, "pfacc", NULL,
-/* B0 */ "pfcmpeq", NULL, NULL, NULL,
-/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
-/* B8 */ NULL, NULL, NULL, "pswapd",
-/* BC */ NULL, NULL, NULL, "pavgusb",
-/* C0 */ NULL, NULL, NULL, NULL,
-/* C4 */ NULL, NULL, NULL, NULL,
-/* C8 */ NULL, NULL, NULL, NULL,
-/* CC */ NULL, NULL, NULL, NULL,
-/* D0 */ NULL, NULL, NULL, NULL,
-/* D4 */ NULL, NULL, NULL, NULL,
-/* D8 */ NULL, NULL, NULL, NULL,
-/* DC */ NULL, NULL, NULL, NULL,
-/* E0 */ NULL, NULL, NULL, NULL,
-/* E4 */ NULL, NULL, NULL, NULL,
-/* E8 */ NULL, NULL, NULL, NULL,
-/* EC */ NULL, NULL, NULL, NULL,
-/* F0 */ NULL, NULL, NULL, NULL,
-/* F4 */ NULL, NULL, NULL, NULL,
-/* F8 */ NULL, NULL, NULL, NULL,
-/* FC */ NULL, NULL, NULL, NULL,
-};
-
static void
-OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+OP_OFF64 (int bytemode, int sizeflag)
{
- const char *mnemonic;
+ bfd_vma off;
- FETCH_DATA (the_info, codep + 1);
- /* AMD 3DNow! instructions are specified by an opcode suffix in the
- place where an 8-bit immediate would normally go. ie. the last
- byte of the instruction. */
- obufp = mnemonicendp;
- mnemonic = Suffix3DNow[*codep++ & 0xff];
- if (mnemonic)
- oappend (mnemonic);
- else
+ if (address_mode != mode_64bit
+ || (prefixes & PREFIX_ADDR))
+ {
+ OP_OFF (bytemode, sizeflag);
+ return;
+ }
+
+ if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
+ intel_operand_size (bytemode, sizeflag);
+ append_seg ();
+
+ off = get64 ();
+
+ if (intel_syntax)
{
- /* Since a variable sized modrm/sib chunk is between the start
- of the opcode (0x0f0f) and the opcode suffix, we need to do
- all the modrm processing first, and don't know until now that
- we have a bad opcode. This necessitates some cleaning up. */
- op_out[0][0] = '\0';
- op_out[1][0] = '\0';
- BadOp ();
+ if (!active_seg_prefix)
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
}
- mnemonicendp = obufp;
+ print_operand_value (scratchbuf, 1, off);
+ oappend (scratchbuf);
}
-static struct op simd_cmp_op[] =
-{
- { STRING_COMMA_LEN ("eq") },
- { STRING_COMMA_LEN ("lt") },
- { STRING_COMMA_LEN ("le") },
- { STRING_COMMA_LEN ("unord") },
- { STRING_COMMA_LEN ("neq") },
- { STRING_COMMA_LEN ("nlt") },
- { STRING_COMMA_LEN ("nle") },
- { STRING_COMMA_LEN ("ord") }
-};
-
static void
-CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+ptr_reg (int code, int sizeflag)
{
- unsigned int cmp_type;
+ const char *s;
- FETCH_DATA (the_info, codep + 1);
- cmp_type = *codep++ & 0xff;
- if (cmp_type < ARRAY_SIZE (simd_cmp_op))
+ *obufp++ = open_char;
+ used_prefixes |= (prefixes & PREFIX_ADDR);
+ if (address_mode == mode_64bit)
{
- char suffix [3];
- char *p = mnemonicendp - 2;
- suffix[0] = p[0];
- suffix[1] = p[1];
- suffix[2] = '\0';
- sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
- mnemonicendp += simd_cmp_op[cmp_type].len;
+ if (!(sizeflag & AFLAG))
+ s = names32[code - eAX_reg];
+ else
+ s = names64[code - eAX_reg];
}
+ else if (sizeflag & AFLAG)
+ s = names32[code - eAX_reg];
else
+ s = names16[code - eAX_reg];
+ oappend (s);
+ *obufp++ = close_char;
+ *obufp = 0;
+}
+
+static void
+OP_ESreg (int code, int sizeflag)
+{
+ if (intel_syntax)
{
- /* We have a reserved extension byte. Output it directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, cmp_type);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
+ switch (codep[-1])
+ {
+ case 0x6d: /* insw/insl */
+ intel_operand_size (z_mode, sizeflag);
+ break;
+ case 0xa5: /* movsw/movsl/movsq */
+ case 0xa7: /* cmpsw/cmpsl/cmpsq */
+ case 0xab: /* stosw/stosl */
+ case 0xaf: /* scasw/scasl */
+ intel_operand_size (v_mode, sizeflag);
+ break;
+ default:
+ intel_operand_size (b_mode, sizeflag);
+ }
}
+ oappend_maybe_intel ("%es:");
+ ptr_reg (code, sizeflag);
}
static void
-OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
+OP_DSreg (int code, int sizeflag)
{
- /* mwaitx %eax,%ecx,%ebx */
- if (!intel_syntax)
+ if (intel_syntax)
{
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[3]);
- two_source_ops = 1;
+ switch (codep[-1])
+ {
+ case 0x6f: /* outsw/outsl */
+ intel_operand_size (z_mode, sizeflag);
+ break;
+ case 0xa5: /* movsw/movsl/movsq */
+ case 0xa7: /* cmpsw/cmpsl/cmpsq */
+ case 0xad: /* lodsw/lodsl/lodsq */
+ intel_operand_size (v_mode, sizeflag);
+ break;
+ default:
+ intel_operand_size (b_mode, sizeflag);
+ }
}
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
+ /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
+ default segment register DS is printed. */
+ if (!active_seg_prefix)
+ active_seg_prefix = PREFIX_DS;
+ append_seg ();
+ ptr_reg (code, sizeflag);
}
static void
-OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
+OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- /* mwait %eax,%ecx */
- if (!intel_syntax)
+ int add;
+ if (rex & REX_R)
{
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
- two_source_ops = 1;
+ USED_REX (REX_R);
+ add = 8;
}
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
+ else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
+ {
+ all_prefixes[last_lock_prefix] = 0;
+ used_prefixes |= PREFIX_LOCK;
+ add = 8;
+ }
+ else
+ add = 0;
+ sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
+ oappend_maybe_intel (scratchbuf);
}
static void
-OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
+OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- /* monitor %eax,%ecx,%edx" */
- if (!intel_syntax)
- {
- const char **op1_names;
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
+ int add;
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ add = 8;
+ else
+ add = 0;
+ if (intel_syntax)
+ sprintf (scratchbuf, "db%d", modrm.reg + add);
+ else
+ sprintf (scratchbuf, "%%db%d", modrm.reg + add);
+ oappend (scratchbuf);
+}
- if (!(prefixes & PREFIX_ADDR))
- op1_names = (address_mode == mode_16bit
- ? names16 : names);
- else
- {
- /* Remove "addr16/addr32". */
- all_prefixes[last_addr_prefix] = 0;
- op1_names = (address_mode != mode_32bit
- ? names32 : names16);
- used_prefixes |= PREFIX_ADDR;
- }
- strcpy (op_out[0], op1_names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[2]);
- two_source_ops = 1;
- }
+static void
+OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ sprintf (scratchbuf, "%%tr%d", modrm.reg);
+ oappend_maybe_intel (scratchbuf);
+}
+
+static void
+OP_R (int bytemode, int sizeflag)
+{
/* Skip mod/rm byte. */
MODRM_CHECK;
codep++;
+ OP_E_register (bytemode, sizeflag);
}
static void
-BadOp (void)
+OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- /* Throw away prefixes and 1st. opcode byte. */
- codep = insn_codep + 1;
- oappend ("(bad)");
+ int reg = modrm.reg;
+ const char **names;
+
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ if (prefixes & PREFIX_DATA)
+ {
+ names = names_xmm;
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ reg += 8;
+ }
+ else
+ names = names_mm;
+ oappend (names[reg]);
}
static void
-REP_Fixup (int bytemode, int sizeflag)
+OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
- lods and stos. */
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = REP_PREFIX;
+ int reg = modrm.reg;
+ const char **names;
- switch (bytemode)
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ reg += 8;
+ if (vex.evex)
+ {
+ if (!vex.r)
+ reg += 16;
+ }
+
+ if (need_vex
+ && bytemode != xmm_mode
+ && bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode
+ && bytemode != ymm_mode
+ && bytemode != tmm_mode
+ && bytemode != scalar_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ names = names_xmm;
+ break;
+ case 256:
+ if (vex.w
+ || (bytemode != vex_vsib_q_w_dq_mode
+ && bytemode != vex_vsib_q_w_d_mode))
+ names = names_ymm;
+ else
+ names = names_xmm;
+ break;
+ case 512:
+ names = names_zmm;
+ break;
+ default:
+ abort ();
+ }
+ }
+ else if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ names = names_xmm;
+ break;
+ case 512:
+ names = names_ymm;
+ break;
+ default:
+ abort ();
+ }
+ }
+ else if (bytemode == tmm_mode)
{
- case al_reg:
- case eAX_reg:
- case indir_dx_reg:
- OP_IMREG (bytemode, sizeflag);
- break;
- case eDI_reg:
- OP_ESreg (bytemode, sizeflag);
- break;
- case eSI_reg:
- OP_DSreg (bytemode, sizeflag);
- break;
- default:
- abort ();
- break;
+ modrm.reg = reg;
+ if (reg >= 8)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_tmm;
}
+ else if (bytemode == ymm_mode)
+ names = names_ymm;
+ else
+ names = names_xmm;
+ oappend (names[reg]);
}
-/* For BND-prefixed instructions 0xF2 prefix should be displayed as
- "bnd". */
-
static void
-BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+OP_EM (int bytemode, int sizeflag)
{
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = BND_PREFIX;
-}
-
-/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
- "notrack". */
+ int reg;
+ const char **names;
-static void
-NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- if (active_seg_prefix == PREFIX_DS
- && (address_mode != mode_64bit || last_data_prefix < 0))
+ if (modrm.mod != 3)
{
- /* NOTRACK prefix is only valid on indirect branch instructions.
- NB: DATA prefix is unsupported for Intel64. */
- active_seg_prefix = 0;
- all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
+ if (intel_syntax
+ && (bytemode == v_mode || bytemode == v_swap_mode))
+ {
+ bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ OP_E (bytemode, sizeflag);
+ return;
}
-}
-/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
- "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
- */
+ if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
+ swap_operand ();
-static void
-HLE_Fixup1 (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3
- && (prefixes & PREFIX_LOCK) != 0)
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ reg = modrm.rm;
+ if (prefixes & PREFIX_DATA)
{
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ names = names_xmm;
+ USED_REX (REX_B);
+ if (rex & REX_B)
+ reg += 8;
}
-
- OP_E (bytemode, sizeflag);
+ else
+ names = names_mm;
+ oappend (names[reg]);
}
-/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
- "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
- */
-
+/* cvt* are the only instructions in sse2 which have
+ both SSE and MMX operands and also have 0x66 prefix
+ in their opcode. 0x66 was originally used to differentiate
+ between SSE and MMX instruction(operands). So we have to handle the
+ cvt* separately using OP_EMC and OP_MXC */
static void
-HLE_Fixup2 (int bytemode, int sizeflag)
+OP_EMC (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
{
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ if (intel_syntax && bytemode == v_mode)
+ {
+ bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ OP_E (bytemode, sizeflag);
+ return;
}
- OP_E (bytemode, sizeflag);
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ oappend (names_mm[modrm.rm]);
}
-/* Similar to OP_E. But the 0xf3 prefixes should be displayed as
- "xrelease" for memory operand. No check for LOCK prefix. */
-
static void
-HLE_Fixup3 (int bytemode, int sizeflag)
+OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- if (modrm.mod != 3
- && last_repz_prefix > last_repnz_prefix
- && (prefixes & PREFIX_REPZ) != 0)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
-
- OP_E (bytemode, sizeflag);
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ oappend (names_mm[modrm.reg]);
}
static void
-CMPXCHG8B_Fixup (int bytemode, int sizeflag)
+OP_EX (int bytemode, int sizeflag)
{
- USED_REX (REX_W);
- if (rex & REX_W)
+ int reg;
+ const char **names;
+
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+
+ if (modrm.mod != 3)
{
- /* Change cmpxchg8b to cmpxchg16b. */
- char *p = mnemonicendp - 2;
- mnemonicendp = stpcpy (p, "16b");
- bytemode = o_mode;
+ OP_E_memory (bytemode, sizeflag);
+ return;
}
- else if ((prefixes & PREFIX_LOCK) != 0)
+
+ reg = modrm.rm;
+ USED_REX (REX_B);
+ if (rex & REX_B)
+ reg += 8;
+ if (vex.evex)
{
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ USED_REX (REX_X);
+ if ((rex & REX_X))
+ reg += 16;
}
- OP_M (bytemode, sizeflag);
-}
-
-static void
-XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
-{
- const char **names;
+ if ((sizeflag & SUFFIX_ALWAYS)
+ && (bytemode == x_swap_mode
+ || bytemode == d_swap_mode
+ || bytemode == q_swap_mode))
+ swap_operand ();
- if (need_vex)
+ if (need_vex
+ && bytemode != xmm_mode
+ && bytemode != xmmdw_mode
+ && bytemode != xmmqd_mode
+ && bytemode != xmm_mb_mode
+ && bytemode != xmm_mw_mode
+ && bytemode != xmm_md_mode
+ && bytemode != xmm_mq_mode
+ && bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode
+ && bytemode != ymm_mode
+ && bytemode != tmm_mode
+ && bytemode != vex_scalar_w_dq_mode)
{
switch (vex.length)
{
case 256:
names = names_ymm;
break;
+ case 512:
+ names = names_zmm;
+ break;
default:
abort ();
}
}
- else
- names = names_xmm;
- oappend (names[reg]);
-}
-
-static void
-CRC32_Fixup (int bytemode, int sizeflag)
-{
- /* Add proper suffix to "crc32". */
- char *p = mnemonicendp;
-
- switch (bytemode)
+ else if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
{
- case b_mode:
- if (intel_syntax)
- goto skip;
-
- *p++ = 'b';
- break;
- case v_mode:
- if (intel_syntax)
- goto skip;
-
- USED_REX (REX_W);
- if (rex & REX_W)
- *p++ = 'q';
- else
+ switch (vex.length)
{
- if (sizeflag & DFLAG)
- *p++ = 'l';
- else
- *p++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
+ case 128:
+ case 256:
+ names = names_xmm;
+ break;
+ case 512:
+ names = names_ymm;
+ break;
+ default:
+ abort ();
}
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
}
- mnemonicendp = p;
- *p = '\0';
-
-skip:
- if (modrm.mod == 3)
+ else if (bytemode == tmm_mode)
{
- int add;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- USED_REX (REX_B);
- add = (rex & REX_B) ? 8 : 0;
- if (bytemode == b_mode)
- {
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.rm + add]);
- else
- oappend (names8[modrm.rm + add]);
- }
- else
+ modrm.rm = reg;
+ if (reg >= 8)
{
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.rm + add]);
- else if ((prefixes & PREFIX_DATA))
- oappend (names16[modrm.rm + add]);
- else
- oappend (names32[modrm.rm + add]);
+ oappend ("(bad)");
+ return;
}
+ names = names_tmm;
}
+ else if (bytemode == ymm_mode)
+ names = names_ymm;
+ else
+ names = names_xmm;
+ oappend (names[reg]);
+}
+
+static void
+OP_MS (int bytemode, int sizeflag)
+{
+ if (modrm.mod == 3)
+ OP_EM (bytemode, sizeflag);
else
- OP_E (bytemode, sizeflag);
+ BadOp ();
}
static void
-FXSAVE_Fixup (int bytemode, int sizeflag)
+OP_XS (int bytemode, int sizeflag)
{
- /* Add proper suffix to "fxsave" and "fxrstor". */
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- char *p = mnemonicendp;
- *p++ = '6';
- *p++ = '4';
- *p = '\0';
- mnemonicendp = p;
- }
- OP_M (bytemode, sizeflag);
+ if (modrm.mod == 3)
+ OP_EX (bytemode, sizeflag);
+ else
+ BadOp ();
}
static void
-PCMPESTR_Fixup (int bytemode, int sizeflag)
+OP_M (int bytemode, int sizeflag)
{
- /* Add proper suffix to "{,v}pcmpestr{i,m}". */
- if (!intel_syntax)
- {
- char *p = mnemonicendp;
-
- USED_REX (REX_W);
- if (rex & REX_W)
- *p++ = 'q';
- else if (sizeflag & SUFFIX_ALWAYS)
- *p++ = 'l';
-
- *p = '\0';
- mnemonicendp = p;
- }
+ if (modrm.mod == 3)
+ /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
+ BadOp ();
+ else
+ OP_E (bytemode, sizeflag);
+}
- OP_EX (bytemode, sizeflag);
+static void
+OP_0f07 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3 || modrm.rm != 0)
+ BadOp ();
+ else
+ OP_E (bytemode, sizeflag);
}
-/* Display the destination register operand for instructions with
- VEX. */
+/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
+ 32bit mode and "xchg %rax,%rax" in 64bit mode. */
static void
-OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+NOP_Fixup1 (int bytemode, int sizeflag)
{
- int reg;
- const char **names;
-
- if (!need_vex)
- abort ();
+ if ((prefixes & PREFIX_DATA) != 0
+ || (rex != 0
+ && rex != 0x48
+ && address_mode == mode_64bit))
+ OP_REG (bytemode, sizeflag);
+ else
+ strcpy (obuf, "nop");
+}
- if (!need_vex_reg)
- return;
+static void
+NOP_Fixup2 (int bytemode, int sizeflag)
+{
+ if ((prefixes & PREFIX_DATA) != 0
+ || (rex != 0
+ && rex != 0x48
+ && address_mode == mode_64bit))
+ OP_IMREG (bytemode, sizeflag);
+}
- reg = vex.register_specifier;
- if (address_mode != mode_64bit)
- reg &= 7;
- else if (vex.evex && !vex.v)
- reg += 16;
+static const char *const Suffix3DNow[] = {
+/* 00 */ NULL, NULL, NULL, NULL,
+/* 04 */ NULL, NULL, NULL, NULL,
+/* 08 */ NULL, NULL, NULL, NULL,
+/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
+/* 10 */ NULL, NULL, NULL, NULL,
+/* 14 */ NULL, NULL, NULL, NULL,
+/* 18 */ NULL, NULL, NULL, NULL,
+/* 1C */ "pf2iw", "pf2id", NULL, NULL,
+/* 20 */ NULL, NULL, NULL, NULL,
+/* 24 */ NULL, NULL, NULL, NULL,
+/* 28 */ NULL, NULL, NULL, NULL,
+/* 2C */ NULL, NULL, NULL, NULL,
+/* 30 */ NULL, NULL, NULL, NULL,
+/* 34 */ NULL, NULL, NULL, NULL,
+/* 38 */ NULL, NULL, NULL, NULL,
+/* 3C */ NULL, NULL, NULL, NULL,
+/* 40 */ NULL, NULL, NULL, NULL,
+/* 44 */ NULL, NULL, NULL, NULL,
+/* 48 */ NULL, NULL, NULL, NULL,
+/* 4C */ NULL, NULL, NULL, NULL,
+/* 50 */ NULL, NULL, NULL, NULL,
+/* 54 */ NULL, NULL, NULL, NULL,
+/* 58 */ NULL, NULL, NULL, NULL,
+/* 5C */ NULL, NULL, NULL, NULL,
+/* 60 */ NULL, NULL, NULL, NULL,
+/* 64 */ NULL, NULL, NULL, NULL,
+/* 68 */ NULL, NULL, NULL, NULL,
+/* 6C */ NULL, NULL, NULL, NULL,
+/* 70 */ NULL, NULL, NULL, NULL,
+/* 74 */ NULL, NULL, NULL, NULL,
+/* 78 */ NULL, NULL, NULL, NULL,
+/* 7C */ NULL, NULL, NULL, NULL,
+/* 80 */ NULL, NULL, NULL, NULL,
+/* 84 */ NULL, NULL, NULL, NULL,
+/* 88 */ NULL, NULL, "pfnacc", NULL,
+/* 8C */ NULL, NULL, "pfpnacc", NULL,
+/* 90 */ "pfcmpge", NULL, NULL, NULL,
+/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
+/* 98 */ NULL, NULL, "pfsub", NULL,
+/* 9C */ NULL, NULL, "pfadd", NULL,
+/* A0 */ "pfcmpgt", NULL, NULL, NULL,
+/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
+/* A8 */ NULL, NULL, "pfsubr", NULL,
+/* AC */ NULL, NULL, "pfacc", NULL,
+/* B0 */ "pfcmpeq", NULL, NULL, NULL,
+/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
+/* B8 */ NULL, NULL, NULL, "pswapd",
+/* BC */ NULL, NULL, NULL, "pavgusb",
+/* C0 */ NULL, NULL, NULL, NULL,
+/* C4 */ NULL, NULL, NULL, NULL,
+/* C8 */ NULL, NULL, NULL, NULL,
+/* CC */ NULL, NULL, NULL, NULL,
+/* D0 */ NULL, NULL, NULL, NULL,
+/* D4 */ NULL, NULL, NULL, NULL,
+/* D8 */ NULL, NULL, NULL, NULL,
+/* DC */ NULL, NULL, NULL, NULL,
+/* E0 */ NULL, NULL, NULL, NULL,
+/* E4 */ NULL, NULL, NULL, NULL,
+/* E8 */ NULL, NULL, NULL, NULL,
+/* EC */ NULL, NULL, NULL, NULL,
+/* F0 */ NULL, NULL, NULL, NULL,
+/* F4 */ NULL, NULL, NULL, NULL,
+/* F8 */ NULL, NULL, NULL, NULL,
+/* FC */ NULL, NULL, NULL, NULL,
+};
- if (bytemode == vex_scalar_mode)
- {
- oappend (names_xmm[reg]);
- return;
- }
+static void
+OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ const char *mnemonic;
- switch (vex.length)
+ FETCH_DATA (the_info, codep + 1);
+ /* AMD 3DNow! instructions are specified by an opcode suffix in the
+ place where an 8-bit immediate would normally go. ie. the last
+ byte of the instruction. */
+ obufp = mnemonicendp;
+ mnemonic = Suffix3DNow[*codep++ & 0xff];
+ if (mnemonic)
+ oappend (mnemonic);
+ else
{
- case 128:
- switch (bytemode)
- {
- case vex_mode:
- case vex128_mode:
- case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
- names = names_xmm;
- break;
- case dq_mode:
- if (rex & REX_W)
- names = names64;
- else
- names = names32;
- break;
- case mask_bd_mode:
- case mask_mode:
- if (reg > 0x7)
- {
- oappend ("(bad)");
- return;
- }
- names = names_mask;
- break;
- default:
- abort ();
- return;
- }
- break;
- case 256:
- switch (bytemode)
- {
- case vex_mode:
- case vex256_mode:
- names = names_ymm;
- break;
- case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
- names = vex.w ? names_ymm : names_xmm;
- break;
- case mask_bd_mode:
- case mask_mode:
- if (reg > 0x7)
- {
- oappend ("(bad)");
- return;
- }
- names = names_mask;
- break;
- default:
- /* See PR binutils/20893 for a reproducer. */
- oappend ("(bad)");
- return;
- }
- break;
- case 512:
- names = names_zmm;
- break;
- default:
- abort ();
- break;
+ /* Since a variable sized modrm/sib chunk is between the start
+ of the opcode (0x0f0f) and the opcode suffix, we need to do
+ all the modrm processing first, and don't know until now that
+ we have a bad opcode. This necessitates some cleaning up. */
+ op_out[0][0] = '\0';
+ op_out[1][0] = '\0';
+ BadOp ();
}
- oappend (names[reg]);
+ mnemonicendp = obufp;
}
-/* Get the VEX immediate byte without moving codep. */
+static const struct op simd_cmp_op[] =
+{
+ { STRING_COMMA_LEN ("eq") },
+ { STRING_COMMA_LEN ("lt") },
+ { STRING_COMMA_LEN ("le") },
+ { STRING_COMMA_LEN ("unord") },
+ { STRING_COMMA_LEN ("neq") },
+ { STRING_COMMA_LEN ("nlt") },
+ { STRING_COMMA_LEN ("nle") },
+ { STRING_COMMA_LEN ("ord") }
+};
+
+static const struct op vex_cmp_op[] =
+{
+ { STRING_COMMA_LEN ("eq_uq") },
+ { STRING_COMMA_LEN ("nge") },
+ { STRING_COMMA_LEN ("ngt") },
+ { STRING_COMMA_LEN ("false") },
+ { STRING_COMMA_LEN ("neq_oq") },
+ { STRING_COMMA_LEN ("ge") },
+ { STRING_COMMA_LEN ("gt") },
+ { STRING_COMMA_LEN ("true") },
+ { STRING_COMMA_LEN ("eq_os") },
+ { STRING_COMMA_LEN ("lt_oq") },
+ { STRING_COMMA_LEN ("le_oq") },
+ { STRING_COMMA_LEN ("unord_s") },
+ { STRING_COMMA_LEN ("neq_us") },
+ { STRING_COMMA_LEN ("nlt_uq") },
+ { STRING_COMMA_LEN ("nle_uq") },
+ { STRING_COMMA_LEN ("ord_s") },
+ { STRING_COMMA_LEN ("eq_us") },
+ { STRING_COMMA_LEN ("nge_uq") },
+ { STRING_COMMA_LEN ("ngt_uq") },
+ { STRING_COMMA_LEN ("false_os") },
+ { STRING_COMMA_LEN ("neq_os") },
+ { STRING_COMMA_LEN ("ge_oq") },
+ { STRING_COMMA_LEN ("gt_oq") },
+ { STRING_COMMA_LEN ("true_us") },
+};
-static unsigned char
-get_vex_imm8 (int sizeflag, int opnum)
+static void
+CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- int bytes_before_imm = 0;
+ unsigned int cmp_type;
- if (modrm.mod != 3)
+ FETCH_DATA (the_info, codep + 1);
+ cmp_type = *codep++ & 0xff;
+ if (cmp_type < ARRAY_SIZE (simd_cmp_op))
{
- /* There are SIB/displacement bytes. */
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
- /* 32/64 bit address mode */
- int base = modrm.rm;
-
- /* Check SIB byte. */
- if (base == 4)
- {
- FETCH_DATA (the_info, codep + 1);
- base = *codep & 7;
- /* When decoding the third source, don't increase
- bytes_before_imm as this has already been incremented
- by one in OP_E_memory while decoding the second
- source operand. */
- if (opnum == 0)
- bytes_before_imm++;
- }
-
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 5 or modrm.rm == 4 and base in
- SIB == 5, there is a 4 byte displacement. */
- if (base != 5)
- /* No displacement. */
- break;
- /* Fall through. */
- case 2:
- /* 4 byte displacement. */
- bytes_before_imm += 4;
- break;
- case 1:
- /* 1 byte displacement. */
- bytes_before_imm++;
- break;
- }
- }
- }
- else
- {
- /* 16 bit address mode */
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 6, there is a 2 byte displacement. */
- if (modrm.rm != 6)
- /* No displacement. */
- break;
- /* Fall through. */
- case 2:
- /* 2 byte displacement. */
- bytes_before_imm += 2;
- break;
- case 1:
- /* 1 byte displacement: when decoding the third source,
- don't increase bytes_before_imm as this has already
- been incremented by one in OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- bytes_before_imm++;
-
- break;
- }
- }
- }
+ char suffix [3];
+ char *p = mnemonicendp - 2;
+ suffix[0] = p[0];
+ suffix[1] = p[1];
+ suffix[2] = '\0';
+ sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
+ mnemonicendp += simd_cmp_op[cmp_type].len;
+ }
+ else if (need_vex
+ && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
+ {
+ char suffix [3];
+ char *p = mnemonicendp - 2;
+ suffix[0] = p[0];
+ suffix[1] = p[1];
+ suffix[2] = '\0';
+ cmp_type -= ARRAY_SIZE (simd_cmp_op);
+ sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
+ mnemonicendp += vex_cmp_op[cmp_type].len;
+ }
+ else
+ {
+ /* We have a reserved extension byte. Output it directly. */
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, cmp_type);
+ oappend_maybe_intel (scratchbuf);
+ scratchbuf[0] = '\0';
}
-
- FETCH_DATA (the_info, codep + bytes_before_imm + 1);
- return codep [bytes_before_imm];
}
static void
-OP_EX_VexReg (int bytemode, int sizeflag, int reg)
+OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- const char **names;
-
- if (reg == -1 && modrm.mod != 3)
+ /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
+ if (!intel_syntax)
{
- OP_E_memory (bytemode, sizeflag);
- return;
+ strcpy (op_out[0], names32[0]);
+ strcpy (op_out[1], names32[1]);
+ if (bytemode == eBX_reg)
+ strcpy (op_out[2], names32[3]);
+ two_source_ops = 1;
}
- else
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+}
+
+static void
+OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ /* monitor %{e,r,}ax,%ecx,%edx" */
+ if (!intel_syntax)
{
- if (reg == -1)
+ const char **names = (address_mode == mode_64bit
+ ? names64 : names32);
+
+ if (prefixes & PREFIX_ADDR)
{
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
}
- if (address_mode != mode_64bit)
- reg &= 7;
+ else if (address_mode == mode_16bit)
+ names = names16;
+ strcpy (op_out[0], names[0]);
+ strcpy (op_out[1], names32[1]);
+ strcpy (op_out[2], names32[2]);
+ two_source_ops = 1;
}
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+}
- switch (vex.length)
+static void
+BadOp (void)
+{
+ /* Throw away prefixes and 1st. opcode byte. */
+ codep = insn_codep + 1;
+ oappend ("(bad)");
+}
+
+static void
+REP_Fixup (int bytemode, int sizeflag)
+{
+ /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
+ lods and stos. */
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = REP_PREFIX;
+
+ switch (bytemode)
{
- case 128:
- names = names_xmm;
+ case al_reg:
+ case eAX_reg:
+ case indir_dx_reg:
+ OP_IMREG (bytemode, sizeflag);
break;
- case 256:
- names = names_ymm;
+ case eDI_reg:
+ OP_ESreg (bytemode, sizeflag);
+ break;
+ case eSI_reg:
+ OP_DSreg (bytemode, sizeflag);
break;
default:
abort ();
+ break;
}
- oappend (names[reg]);
}
static void
-OP_EX_VexImmW (int bytemode, int sizeflag)
+SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- int reg = -1;
- static unsigned char vex_imm8;
+ if ( isa64 != amd64 )
+ return;
- if (vex_w_done == 0)
- {
- vex_w_done = 1;
+ obufp = obuf;
+ BadOp ();
+ mnemonicendp = obufp;
+ ++codep;
+}
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
+/* For BND-prefixed instructions 0xF2 prefix should be displayed as
+ "bnd". */
- vex_imm8 = get_vex_imm8 (sizeflag, 0);
+static void
+BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = BND_PREFIX;
+}
- if (vex.w)
- reg = vex_imm8 >> 4;
+/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
+ "notrack". */
- OP_EX_VexReg (bytemode, sizeflag, reg);
- }
- else if (vex_w_done == 1)
+static void
+NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (active_seg_prefix == PREFIX_DS
+ && (address_mode != mode_64bit || last_data_prefix < 0))
{
- vex_w_done = 2;
+ /* NOTRACK prefix is only valid on indirect branch instructions.
+ NB: DATA prefix is unsupported for Intel64. */
+ active_seg_prefix = 0;
+ all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
+ }
+}
- if (!vex.w)
- reg = vex_imm8 >> 4;
+/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
+ "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
+ */
- OP_EX_VexReg (bytemode, sizeflag, reg);
- }
- else
+static void
+HLE_Fixup1 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3
+ && (prefixes & PREFIX_LOCK) != 0)
{
- /* Output the imm8 directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
- codep++;
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
}
+
+ OP_E (bytemode, sizeflag);
}
+/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
+ "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
+ */
+
static void
-OP_Vex_2src (int bytemode, int sizeflag)
+HLE_Fixup2 (int bytemode, int sizeflag)
{
- if (modrm.mod == 3)
- {
- int reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- oappend (names_xmm[reg]);
- }
- else
+ if (modrm.mod != 3)
{
- if (intel_syntax
- && (bytemode == v_mode || bytemode == v_swap_mode))
- {
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- OP_E (bytemode, sizeflag);
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
}
+
+ OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E. But the 0xf3 prefixes should be displayed as
+ "xrelease" for memory operand. No check for LOCK prefix. */
+
+static void
+HLE_Fixup3 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3
+ && last_repz_prefix > last_repnz_prefix
+ && (prefixes & PREFIX_REPZ) != 0)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+
+ OP_E (bytemode, sizeflag);
}
static void
-OP_Vex_2src_1 (int bytemode, int sizeflag)
+CMPXCHG8B_Fixup (int bytemode, int sizeflag)
{
- if (modrm.mod == 3)
+ USED_REX (REX_W);
+ if (rex & REX_W)
{
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
+ /* Change cmpxchg8b to cmpxchg16b. */
+ char *p = mnemonicendp - 2;
+ mnemonicendp = stpcpy (p, "16b");
+ bytemode = o_mode;
}
-
- if (vex.w)
+ else if ((prefixes & PREFIX_LOCK) != 0)
{
- unsigned int reg = vex.register_specifier;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names_xmm[reg]);
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
}
- else
- OP_Vex_2src (bytemode, sizeflag);
+
+ OP_M (bytemode, sizeflag);
}
static void
-OP_Vex_2src_2 (int bytemode, int sizeflag)
+XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
{
- if (vex.w)
- OP_Vex_2src (bytemode, sizeflag);
- else
- {
- unsigned int reg = vex.register_specifier;
+ const char **names;
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names_xmm[reg]);
+ if (need_vex)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ names = names_xmm;
+ break;
+ case 256:
+ names = names_ymm;
+ break;
+ default:
+ abort ();
+ }
}
+ else
+ names = names_xmm;
+ oappend (names[reg]);
}
static void
-OP_EX_VexW (int bytemode, int sizeflag)
+FXSAVE_Fixup (int bytemode, int sizeflag)
{
- int reg = -1;
-
- if (!vex_w_done)
- {
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (vex.w)
- reg = get_vex_imm8 (sizeflag, 0) >> 4;
- }
- else
+ /* Add proper suffix to "fxsave" and "fxrstor". */
+ USED_REX (REX_W);
+ if (rex & REX_W)
{
- if (!vex.w)
- reg = get_vex_imm8 (sizeflag, 1) >> 4;
+ char *p = mnemonicendp;
+ *p++ = '6';
+ *p++ = '4';
+ *p = '\0';
+ mnemonicendp = p;
}
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
-
- if (vex_w_done)
- codep++;
- vex_w_done = 1;
+ OP_M (bytemode, sizeflag);
}
+/* Display the destination register operand for instructions with
+ VEX. */
+
static void
-OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
int reg;
const char **names;
- FETCH_DATA (the_info, codep + 1);
- reg = *codep++;
-
- if (bytemode != x_mode)
+ if (!need_vex)
abort ();
- reg >>= 4;
+ reg = vex.register_specifier;
+ vex.register_specifier = 0;
if (address_mode != mode_64bit)
reg &= 7;
+ else if (vex.evex && !vex.v)
+ reg += 16;
+
+ if (bytemode == vex_scalar_mode)
+ {
+ oappend (names_xmm[reg]);
+ return;
+ }
+
+ if (bytemode == tmm_mode)
+ {
+ /* All 3 TMM registers must be distinct. */
+ if (reg >= 8)
+ oappend ("(bad)");
+ else
+ {
+ /* This must be the 3rd operand. */
+ if (obufp != op_out[2])
+ abort ();
+ oappend (names_tmm[reg]);
+ if (reg == modrm.reg || reg == modrm.rm)
+ strcpy (obufp, "/(bad)");
+ }
+
+ if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
+ {
+ if (modrm.reg <= 8
+ && (modrm.reg == modrm.rm || modrm.reg == reg))
+ strcat (op_out[0], "/(bad)");
+ if (modrm.rm <= 8
+ && (modrm.rm == modrm.reg || modrm.rm == reg))
+ strcat (op_out[1], "/(bad)");
+ }
+
+ return;
+ }
switch (vex.length)
{
case 128:
- names = names_xmm;
+ switch (bytemode)
+ {
+ case vex_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ names = names_xmm;
+ break;
+ case dq_mode:
+ if (rex & REX_W)
+ names = names64;
+ else
+ names = names32;
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_mask;
+ break;
+ default:
+ abort ();
+ return;
+ }
break;
case 256:
- names = names_ymm;
+ switch (bytemode)
+ {
+ case vex_mode:
+ names = names_ymm;
+ break;
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ names = vex.w ? names_ymm : names_xmm;
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_mask;
+ break;
+ default:
+ /* See PR binutils/20893 for a reproducer. */
+ oappend ("(bad)");
+ return;
+ }
+ break;
+ case 512:
+ names = names_zmm;
break;
default:
abort ();
+ break;
}
oappend (names[reg]);
}
static void
-OP_XMM_VexW (int bytemode, int sizeflag)
+OP_VexR (int bytemode, int sizeflag)
{
- /* Turn off the REX.W bit since it is used for swapping operands
- now. */
- rex &= ~REX_W;
- OP_XMM (bytemode, sizeflag);
+ if (modrm.mod == 3)
+ OP_VEX (bytemode, sizeflag);
}
static void
-OP_EX_Vex (int bytemode, int sizeflag)
+OP_VexW (int bytemode, int sizeflag)
{
- if (modrm.mod != 3)
- {
- if (vex.register_specifier != 0)
- BadOp ();
- need_vex_reg = 0;
- }
- OP_EX (bytemode, sizeflag);
-}
+ OP_VEX (bytemode, sizeflag);
-static void
-OP_XMM_Vex (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3)
+ if (vex.w)
{
- if (vex.register_specifier != 0)
- BadOp ();
- need_vex_reg = 0;
+ /* Swap 2nd and 3rd operands. */
+ strcpy (scratchbuf, op_out[2]);
+ strcpy (op_out[2], op_out[1]);
+ strcpy (op_out[1], scratchbuf);
}
- OP_XMM (bytemode, sizeflag);
}
static void
-VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- switch (vex.length)
+ int reg;
+ const char **names = names_xmm;
+
+ FETCH_DATA (the_info, codep + 1);
+ reg = *codep++;
+
+ if (bytemode != x_mode && bytemode != scalar_mode)
+ abort ();
+
+ reg >>= 4;
+ if (address_mode != mode_64bit)
+ reg &= 7;
+
+ if (bytemode == x_mode && vex.length == 256)
+ names = names_ymm;
+
+ oappend (names[reg]);
+
+ if (vex.w)
{
- case 128:
- mnemonicendp = stpcpy (obuf, "vzeroupper");
- break;
- case 256:
- mnemonicendp = stpcpy (obuf, "vzeroall");
- break;
- default:
- abort ();
+ /* Swap 3rd and 4th operands. */
+ strcpy (scratchbuf, op_out[3]);
+ strcpy (op_out[3], op_out[2]);
+ strcpy (op_out[2], scratchbuf);
}
}
-static struct op vex_cmp_op[] =
-{
- { STRING_COMMA_LEN ("eq") },
- { STRING_COMMA_LEN ("lt") },
- { STRING_COMMA_LEN ("le") },
- { STRING_COMMA_LEN ("unord") },
- { STRING_COMMA_LEN ("neq") },
- { STRING_COMMA_LEN ("nlt") },
- { STRING_COMMA_LEN ("nle") },
- { STRING_COMMA_LEN ("ord") },
- { STRING_COMMA_LEN ("eq_uq") },
- { STRING_COMMA_LEN ("nge") },
- { STRING_COMMA_LEN ("ngt") },
- { STRING_COMMA_LEN ("false") },
- { STRING_COMMA_LEN ("neq_oq") },
- { STRING_COMMA_LEN ("ge") },
- { STRING_COMMA_LEN ("gt") },
- { STRING_COMMA_LEN ("true") },
- { STRING_COMMA_LEN ("eq_os") },
- { STRING_COMMA_LEN ("lt_oq") },
- { STRING_COMMA_LEN ("le_oq") },
- { STRING_COMMA_LEN ("unord_s") },
- { STRING_COMMA_LEN ("neq_us") },
- { STRING_COMMA_LEN ("nlt_uq") },
- { STRING_COMMA_LEN ("nle_uq") },
- { STRING_COMMA_LEN ("ord_s") },
- { STRING_COMMA_LEN ("eq_us") },
- { STRING_COMMA_LEN ("nge_uq") },
- { STRING_COMMA_LEN ("ngt_uq") },
- { STRING_COMMA_LEN ("false_os") },
- { STRING_COMMA_LEN ("neq_os") },
- { STRING_COMMA_LEN ("ge_oq") },
- { STRING_COMMA_LEN ("gt_oq") },
- { STRING_COMMA_LEN ("true_us") },
-};
-
static void
-VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
{
- unsigned int cmp_type;
-
- FETCH_DATA (the_info, codep + 1);
- cmp_type = *codep++ & 0xff;
- if (cmp_type < ARRAY_SIZE (vex_cmp_op))
- {
- char suffix [3];
- char *p = mnemonicendp - 2;
- suffix[0] = p[0];
- suffix[1] = p[1];
- suffix[2] = '\0';
- sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
- mnemonicendp += vex_cmp_op[cmp_type].len;
- }
- else
- {
- /* We have a reserved extension byte. Output it directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, cmp_type);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
- }
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
+ oappend_maybe_intel (scratchbuf);
}
static void
}
static void
-MOVBE_Fixup (int bytemode, int sizeflag)
+MOVSXD_Fixup (int bytemode, int sizeflag)
{
- /* Add proper suffix to "movbe". */
+ /* Add proper suffix to "movsxd". */
char *p = mnemonicendp;
switch (bytemode)
{
- case v_mode:
+ case movsxd_mode:
if (intel_syntax)
- goto skip;
+ {
+ *p++ = 'x';
+ *p++ = 'd';
+ goto skip;
+ }
USED_REX (REX_W);
- if (sizeflag & SUFFIX_ALWAYS)
+ if (rex & REX_W)
{
- if (rex & REX_W)
- *p++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *p++ = 'l';
- else
- *p++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ *p++ = 'l';
+ *p++ = 'q';
+ }
+ else
+ {
+ *p++ = 'x';
+ *p++ = 'd';
}
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
break;
}
+
+ skip:
mnemonicendp = p;
*p = '\0';
-
-skip:
- OP_M (bytemode, sizeflag);
-}
-
-static void
-OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int reg;
- const char **names;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (rex & REX_W)
- names = names64;
- else
- names = names32;
-
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
-
- oappend (names[reg]);
-}
-
-static void
-OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- const char **names;
- unsigned int reg = vex.register_specifier;
-
- if (rex & REX_W)
- names = names64;
- else
- names = names32;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names[reg]);
+ OP_E (bytemode, sizeflag);
}
static void
static void
OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- if (!vex.evex
- || (bytemode != evex_rounding_mode
- && bytemode != evex_rounding_64_mode
- && bytemode != evex_sae_mode))
- abort ();
if (modrm.mod == 3 && vex.b)
switch (bytemode)
{
oappend ("{sae}");
break;
default:
+ abort ();
break;
}
}
projects / deliverable / binutils-gdb.git / blobdiff