static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
static void ckprefix PARAMS ((void));
static const char *prefix_name PARAMS ((int, int));
-static int print_insn_i386 PARAMS ((bfd_vma, disassemble_info *));
+static int print_insn PARAMS ((bfd_vma, disassemble_info *));
static void dofloat PARAMS ((int));
static void OP_ST PARAMS ((int, int));
static void OP_STi PARAMS ((int, int));
bfd_byte *max_fetched;
bfd_byte the_buffer[MAXLEN];
bfd_vma insn_start;
+ int orig_sizeflag;
jmp_buf bailout;
};
#define loop_jcxz_flag NULL, loop_jcxz_mode
/* bits in sizeflag */
-#if 0 /* Leave undefined until someone adds the extra flag to objdump. */
#define SUFFIX_ALWAYS 4
-#endif
#define AFLAG 2
#define DFLAG 1
'N' => print 'n' if instruction has no wait "prefix"
'O' => print 'd', or 'o'
'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
- or suffix_always is true
- print 'q' if rex prefix is present.
- 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always is true
+ . or suffix_always is true. print 'q' if rex prefix is present.
+ 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
+ . is true
'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
'S' => print 'w', 'l' or 'q' if suffix_always is true
'T' => print 'q' in 64bit mode and behave as 'P' otherwise
{ "(bad)", Eb, XX, XX },
{ "notA", Eb, XX, XX },
{ "negA", Eb, XX, XX },
- { "mulB", AL, Eb, XX },
- { "imulB", AL, Eb, XX },
- { "divB", AL, Eb, XX },
- { "idivB", AL, Eb, XX }
+ { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */
+ { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */
+ { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */
+ { "idivA", Eb, XX, XX } /* and idiv for consistency. */
},
/* GRP3S */
{
{ "(bad)", XX, XX, XX },
{ "notQ", Ev, XX, XX },
{ "negQ", Ev, XX, XX },
- { "mulS", eAX, Ev, XX },
- { "imulS", eAX, Ev, XX },
- { "divS", eAX, Ev, XX },
- { "idivS", eAX, Ev, XX },
+ { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */
+ { "imulQ", Ev, XX, XX },
+ { "divQ", Ev, XX, XX },
+ { "idivQ", Ev, XX, XX },
},
/* GRP4 */
{
},
/* GRP6 */
{
- { "sldt", Ew, XX, XX },
- { "str", Ew, XX, XX },
+ { "sldtQ", Ev, XX, XX },
+ { "strQ", Ev, XX, XX },
{ "lldt", Ew, XX, XX },
{ "ltr", Ew, XX, XX },
{ "verr", Ew, XX, XX },
{ "sidtQ", M, XX, XX },
{ "lgdtQ", M, XX, XX },
{ "lidtQ", M, XX, XX },
- { "smsw", Ew, XX, XX },
+ { "smswQ", Ev, XX, XX },
{ "(bad)", XX, XX, XX },
{ "lmsw", Ew, XX, XX },
{ "invlpg", Ew, XX, XX },
case 0x66:
return (sizeflag & DFLAG) ? "data16" : "data32";
case 0x67:
- return (sizeflag & AFLAG) ? "addr16" : "addr32";
+ if (mode_64bit)
+ return (sizeflag & AFLAG) ? "addr32" : "addr64";
+ else
+ return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32";
case FWAIT_OPCODE:
return "fwait";
default:
static char separator_char;
static char scale_char;
+/* Here for backwards compatibility. When gdb stops using
+ print_insn_i386_att and print_insn_i386_intel these functions can
+ disappear, and print_insn_i386 be merged into print_insn. */
int
print_insn_i386_att (pc, info)
bfd_vma pc;
disassemble_info *info;
{
intel_syntax = 0;
- names64 = att_names64;
- names32 = att_names32;
- names16 = att_names16;
- names8 = att_names8;
- names8rex = att_names8rex;
- names_seg = att_names_seg;
- index16 = att_index16;
- open_char = '(';
- close_char = ')';
- separator_char = ',';
- scale_char = ',';
-
- return print_insn_i386 (pc, info);
+
+ return print_insn (pc, info);
}
int
disassemble_info *info;
{
intel_syntax = 1;
- names64 = intel_names64;
- names32 = intel_names32;
- names16 = intel_names16;
- names8 = intel_names8;
- names8rex = intel_names8rex;
- names_seg = intel_names_seg;
- index16 = intel_index16;
- open_char = '[';
- close_char = ']';
- separator_char = '+';
- scale_char = '*';
-
- return print_insn_i386 (pc, info);
+
+ return print_insn (pc, info);
}
-static int
+int
print_insn_i386 (pc, info)
bfd_vma pc;
disassemble_info *info;
+{
+ intel_syntax = -1;
+
+ return print_insn (pc, info);
+}
+
+static int
+print_insn (pc, info)
+ bfd_vma pc;
+ disassemble_info *info;
{
const struct dis386 *dp;
int i;
char *first, *second, *third;
int needcomma;
unsigned char uses_SSE_prefix;
- VOLATILE int sizeflag;
- VOLATILE int orig_sizeflag;
-
+ int sizeflag;
+ const char *p;
struct dis_private priv;
- bfd_byte *inbuf = priv.the_buffer;
mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax
|| info->mach == bfd_mach_x86_64);
+ if (intel_syntax == -1)
+ intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
+ || info->mach == bfd_mach_x86_64_intel_syntax);
+
if (info->mach == bfd_mach_i386_i386
|| info->mach == bfd_mach_x86_64
|| info->mach == bfd_mach_i386_i386_intel_syntax
|| info->mach == bfd_mach_x86_64_intel_syntax)
- sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag = AFLAG | DFLAG;
else if (info->mach == bfd_mach_i386_i8086)
- sizeflag = 0;
+ priv.orig_sizeflag = 0;
else
abort ();
- orig_sizeflag = sizeflag;
+
+ for (p = info->disassembler_options; p != NULL; )
+ {
+ if (strncmp (p, "x86-64", 6) == 0)
+ {
+ mode_64bit = 1;
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ }
+ else if (strncmp (p, "i386", 4) == 0)
+ {
+ mode_64bit = 0;
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ }
+ else if (strncmp (p, "i8086", 5) == 0)
+ {
+ mode_64bit = 0;
+ priv.orig_sizeflag = 0;
+ }
+ else if (strncmp (p, "intel", 5) == 0)
+ {
+ intel_syntax = 1;
+ }
+ else if (strncmp (p, "att", 3) == 0)
+ {
+ intel_syntax = 0;
+ }
+ else if (strncmp (p, "addr", 4) == 0)
+ {
+ if (p[4] == '1' && p[5] == '6')
+ priv.orig_sizeflag &= ~AFLAG;
+ else if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag |= AFLAG;
+ }
+ else if (strncmp (p, "data", 4) == 0)
+ {
+ if (p[4] == '1' && p[5] == '6')
+ priv.orig_sizeflag &= ~DFLAG;
+ else if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag |= DFLAG;
+ }
+ else if (strncmp (p, "suffix", 6) == 0)
+ priv.orig_sizeflag |= SUFFIX_ALWAYS;
+
+ p = strchr (p, ',');
+ if (p != NULL)
+ p++;
+ }
+
+ if (intel_syntax)
+ {
+ names64 = intel_names64;
+ names32 = intel_names32;
+ names16 = intel_names16;
+ names8 = intel_names8;
+ names8rex = intel_names8rex;
+ names_seg = intel_names_seg;
+ index16 = intel_index16;
+ open_char = '[';
+ close_char = ']';
+ separator_char = '+';
+ scale_char = '*';
+ }
+ else
+ {
+ names64 = att_names64;
+ names32 = att_names32;
+ names16 = att_names16;
+ names8 = att_names8;
+ names8rex = att_names8rex;
+ names_seg = att_names_seg;
+ index16 = att_index16;
+ open_char = '(';
+ close_char = ')';
+ separator_char = ',';
+ scale_char = ',';
+ }
/* The output looks better if we put 7 bytes on a line, since that
puts most long word instructions on a single line. */
the_info = info;
start_pc = pc;
- start_codep = inbuf;
- codep = inbuf;
+ start_codep = priv.the_buffer;
+ codep = priv.the_buffer;
if (setjmp (priv.bailout) != 0)
{
const char *name;
/* Getting here means we tried for data but didn't get it. That
- means we have an incomplete instruction of some sort. Just
- print the first byte as a prefix or a .byte pseudo-op. */
- if (codep > inbuf)
+ means we have an incomplete instruction of some sort. Just
+ print the first byte as a prefix or a .byte pseudo-op. */
+ if (codep > priv.the_buffer)
{
- name = prefix_name (inbuf[0], orig_sizeflag);
+ name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
if (name != NULL)
(*info->fprintf_func) (info->stream, "%s", name);
else
{
/* Just print the first byte as a .byte instruction. */
(*info->fprintf_func) (info->stream, ".byte 0x%x",
- (unsigned int) inbuf[0]);
+ (unsigned int) priv.the_buffer[0]);
}
return 1;
ckprefix ();
insn_codep = codep;
+ sizeflag = priv.orig_sizeflag;
FETCH_DATA (info, codep + 1);
two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
/* fwait not followed by floating point instruction. Print the
first prefix, which is probably fwait itself. */
- name = prefix_name (inbuf[0], orig_sizeflag);
+ name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
if (name == NULL)
name = INTERNAL_DISASSEMBLER_ERROR;
(*info->fprintf_func) (info->stream, "%s", name);
sizeflag ^= AFLAG;
if (dp->bytemode3 != loop_jcxz_mode || intel_syntax)
{
- if (sizeflag & AFLAG)
+ if ((sizeflag & AFLAG) || mode_64bit)
oappend ("addr32 ");
else
oappend ("addr16 ");
{
const char *name;
- name = prefix_name (inbuf[0], orig_sizeflag);
+ name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
if (name == NULL)
name = INTERNAL_DISASSEMBLER_ERROR;
(*info->fprintf_func) (info->stream, "%s", name);
if (rex & ~rex_used)
{
const char *name;
- name = prefix_name (rex | 0x40, orig_sizeflag);
+ name = prefix_name (rex | 0x40, priv.orig_sizeflag);
if (name == NULL)
name = INTERNAL_DISASSEMBLER_ERROR;
(*info->fprintf_func) (info->stream, "%s ", name);
(*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
+ op_address[op_index[i]]), info);
}
- return codep - inbuf;
+ return codep - priv.the_buffer;
}
static const char *float_mem[] = {
case 'A':
if (intel_syntax)
break;
- if (mod != 3
-#ifdef SUFFIX_ALWAYS
- || (sizeflag & SUFFIX_ALWAYS)
-#endif
- )
+ if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
*obufp++ = 'b';
break;
case 'B':
if (intel_syntax)
break;
-#ifdef SUFFIX_ALWAYS
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'b';
-#endif
break;
case 'E': /* For jcxz/jecxz */
- if (sizeflag & AFLAG)
- *obufp++ = 'e';
+ if (mode_64bit)
+ {
+ if (sizeflag & AFLAG)
+ *obufp++ = 'r';
+ else
+ *obufp++ = 'e';
+ }
+ else
+ if (sizeflag & AFLAG)
+ *obufp++ = 'e';
used_prefixes |= (prefixes & PREFIX_ADDR);
break;
case 'F':
if (intel_syntax)
break;
- if ((prefixes & PREFIX_ADDR)
-#ifdef SUFFIX_ALWAYS
- || (sizeflag & SUFFIX_ALWAYS)
-#endif
- )
+ if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & AFLAG)
- *obufp++ = 'l';
+ *obufp++ = mode_64bit ? 'q' : 'l';
else
- *obufp++ = 'w';
+ *obufp++ = mode_64bit ? 'l' : 'w';
used_prefixes |= (prefixes & PREFIX_ADDR);
}
break;
case 'L':
if (intel_syntax)
break;
-#ifdef SUFFIX_ALWAYS
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'l';
-#endif
break;
case 'N':
if ((prefixes & PREFIX_FWAIT) == 0)
break;
if ((prefixes & PREFIX_DATA)
|| (rex & REX_MODE64)
-#ifdef SUFFIX_ALWAYS
- || (sizeflag & SUFFIX_ALWAYS)
-#endif
- )
+ || (sizeflag & SUFFIX_ALWAYS))
{
USED_REX (REX_MODE64);
if (rex & REX_MODE64)
if (intel_syntax)
break;
USED_REX (REX_MODE64);
- if (mod != 3
-#ifdef SUFFIX_ALWAYS
- || (sizeflag & SUFFIX_ALWAYS)
-#endif
- )
+ if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
{
if (rex & REX_MODE64)
*obufp++ = 'q';
case 'S':
if (intel_syntax)
break;
-#ifdef SUFFIX_ALWAYS
if (sizeflag & SUFFIX_ALWAYS)
{
if (rex & REX_MODE64)
used_prefixes |= (prefixes & PREFIX_DATA);
}
}
-#endif
break;
case 'X':
if (prefixes & PREFIX_DATA)
disp = 0;
append_seg ();
- if (sizeflag & AFLAG) /* 32 bit address mode */
+ if ((sizeflag & AFLAG) || mode_64bit) /* 32 bit address mode */
{
int havesib;
int havebase;
if ((base & 7) == 5)
{
havebase = 0;
- if (mode_64bit && !havesib)
+ if (mode_64bit && !havesib && (sizeflag & AFLAG))
riprel = 1;
disp = get32s ();
}
if (!havesib && (rex & REX_EXTZ))
base += 8;
if (havebase)
- oappend (mode_64bit ? names64[base] : names32[base]);
+ oappend (mode_64bit && (sizeflag & AFLAG)
+ ? names64[base] : names32[base]);
if (havesib)
{
if (index != 4)
*obufp = '\0';
}
sprintf (scratchbuf, "%s",
- mode_64bit ? names64[index] : names32[index]);
+ mode_64bit && (sizeflag & AFLAG)
+ ? names64[index] : names32[index]);
}
else
sprintf (scratchbuf, ",%s",
- mode_64bit ? names64[index] : names32[index]);
+ mode_64bit && (sizeflag & AFLAG)
+ ? names64[index] : names32[index]);
oappend (scratchbuf);
}
if (!intel_syntax
append_seg ();
- if (sizeflag & AFLAG)
+ if ((sizeflag & AFLAG) || mode_64bit)
off = get32 ();
else
off = get16 ();
USED_REX (REX_MODE64);
if (rex & REX_MODE64)
- s = names64[code - eAX_reg];
+ {
+ if (!(sizeflag & AFLAG))
+ s = names32[code - eAX_reg];
+ else
+ s = names64[code - eAX_reg];
+ }
else if (sizeflag & AFLAG)
s = names32[code - eAX_reg];
else
BadOp ();
}
-static const char *Suffix3DNow[] = {
+static const char *const Suffix3DNow[] = {
/* 00 */ NULL, NULL, NULL, NULL,
/* 04 */ NULL, NULL, NULL, NULL,
/* 08 */ NULL, NULL, NULL, NULL,
projects / deliverable / binutils-gdb.git / blobdiff