#define MaskVex { OP_VEX, mask_mode }
#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
-#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
-#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
#define MVexSIBMEM { OP_M, vex_sibmem_mode }
/* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
- /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
- vex_vsib_d_w_d_mode,
/* Operand size depends on the VEX.W bit, with VSIB qword indices. */
vex_vsib_q_w_dq_mode,
- /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
- vex_vsib_q_w_d_mode,
/* mandatory non-vector SIB. */
vex_sibmem_mode,
REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
REG_VEX_0F38F3_L_0,
- REG_0FXOP_09_01_L_0,
- REG_0FXOP_09_02_L_0,
- REG_0FXOP_09_12_M_1_L_0,
- REG_0FXOP_0A_12_L_0,
+ REG_XOP_09_01_L_0,
+ REG_XOP_09_02_L_0,
+ REG_XOP_09_12_M_1_L_0,
+ REG_XOP_0A_12_L_0,
REG_EVEX_0F71,
REG_EVEX_0F72,
REG_EVEX_0F73,
- REG_EVEX_0F38C6,
- REG_EVEX_0F38C7
+ REG_EVEX_0F38C6_M_0_L_2,
+ REG_EVEX_0F38C7_M_0_L_2
};
enum
{
- MOD_8D = 0,
+ MOD_62_32BIT = 0,
+ MOD_8D,
+ MOD_C4_32BIT,
+ MOD_C5_32BIT,
MOD_C6_REG_7,
MOD_C7_REG_7,
MOD_FF_REG_3,
MOD_0F38FA_PREFIX_1,
MOD_0F38FB_PREFIX_1,
MOD_0F3A0F_PREFIX_1,
- MOD_62_32BIT,
- MOD_C4_32BIT,
- MOD_C5_32BIT,
+
MOD_VEX_0F12_PREFIX_0,
MOD_VEX_0F12_PREFIX_2,
MOD_VEX_0F13,
MOD_VEX_0F3A32_L_0,
MOD_VEX_0F3A33_L_0,
- MOD_VEX_0FXOP_09_12,
+ MOD_XOP_09_12,
MOD_EVEX_0F12_PREFIX_0,
MOD_EVEX_0F12_PREFIX_2,
MOD_EVEX_0F16_PREFIX_2,
MOD_EVEX_0F17,
MOD_EVEX_0F2B,
- MOD_EVEX_0F381A_W_0,
- MOD_EVEX_0F381A_W_1,
- MOD_EVEX_0F381B_W_0,
- MOD_EVEX_0F381B_W_1,
+ MOD_EVEX_0F381A,
+ MOD_EVEX_0F381B,
MOD_EVEX_0F3828_P_1,
MOD_EVEX_0F382A_P_1_W_1,
MOD_EVEX_0F3838_P_1,
MOD_EVEX_0F383A_P_1_W_0,
- MOD_EVEX_0F385A_W_0,
- MOD_EVEX_0F385A_W_1,
- MOD_EVEX_0F385B_W_0,
- MOD_EVEX_0F385B_W_1,
+ MOD_EVEX_0F385A,
+ MOD_EVEX_0F385B,
MOD_EVEX_0F387A_W_0,
MOD_EVEX_0F387B_W_0,
MOD_EVEX_0F387C,
- MOD_EVEX_0F38C6_REG_1,
- MOD_EVEX_0F38C6_REG_2,
- MOD_EVEX_0F38C6_REG_5,
- MOD_EVEX_0F38C6_REG_6,
- MOD_EVEX_0F38C7_REG_1,
- MOD_EVEX_0F38C7_REG_2,
- MOD_EVEX_0F38C7_REG_5,
- MOD_EVEX_0F38C7_REG_6
+ MOD_EVEX_0F38C6,
+ MOD_EVEX_0F38C7
};
enum
RM_0F01_REG_5_MOD_3,
RM_0F01_REG_7_MOD_3,
RM_0F1E_P_1_MOD_3_REG_7,
- RM_0F3A0F_P_1_MOD_3_REG_0,
RM_0FAE_REG_6_MOD_3_P_0,
RM_0FAE_REG_7_MOD_3,
+ RM_0F3A0F_P_1_MOD_3_REG_0,
+
RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
};
X86_64_0F01_REG_1_RM_7_PREFIX_2,
X86_64_0F01_REG_2,
X86_64_0F01_REG_3,
- X86_64_0F24,
- X86_64_0F26,
- X86_64_VEX_0F3849,
- X86_64_VEX_0F384B,
- X86_64_VEX_0F385C,
- X86_64_VEX_0F385E,
X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
- X86_64_0FC7_REG_6_MOD_3_PREFIX_1
+ X86_64_0F24,
+ X86_64_0F26,
+ X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
+
+ X86_64_VEX_0F3849,
+ X86_64_VEX_0F384B,
+ X86_64_VEX_0F385C,
+ X86_64_VEX_0F385E
};
enum
enum
{
- EVEX_LEN_0F6E = 0,
- EVEX_LEN_0F7E_P_1,
- EVEX_LEN_0F7E_P_2,
- EVEX_LEN_0FC4,
- EVEX_LEN_0FC5,
- EVEX_LEN_0FD6,
- EVEX_LEN_0F3816,
- EVEX_LEN_0F3819_W_0,
- EVEX_LEN_0F3819_W_1,
- EVEX_LEN_0F381A_W_0_M_0,
- EVEX_LEN_0F381A_W_1_M_0,
- EVEX_LEN_0F381B_W_0_M_0,
- EVEX_LEN_0F381B_W_1_M_0,
+ EVEX_LEN_0F3816 = 0,
+ EVEX_LEN_0F3819,
+ EVEX_LEN_0F381A_M_0,
+ EVEX_LEN_0F381B_M_0,
EVEX_LEN_0F3836,
- EVEX_LEN_0F385A_W_0_M_0,
- EVEX_LEN_0F385A_W_1_M_0,
- EVEX_LEN_0F385B_W_0_M_0,
- EVEX_LEN_0F385B_W_1_M_0,
- EVEX_LEN_0F38C6_R_1_M_0,
- EVEX_LEN_0F38C6_R_2_M_0,
- EVEX_LEN_0F38C6_R_5_M_0,
- EVEX_LEN_0F38C6_R_6_M_0,
- EVEX_LEN_0F38C7_R_1_M_0_W_0,
- EVEX_LEN_0F38C7_R_1_M_0_W_1,
- EVEX_LEN_0F38C7_R_2_M_0_W_0,
- EVEX_LEN_0F38C7_R_2_M_0_W_1,
- EVEX_LEN_0F38C7_R_5_M_0_W_0,
- EVEX_LEN_0F38C7_R_5_M_0_W_1,
- EVEX_LEN_0F38C7_R_6_M_0_W_0,
- EVEX_LEN_0F38C7_R_6_M_0_W_1,
- EVEX_LEN_0F3A00_W_1,
- EVEX_LEN_0F3A01_W_1,
- EVEX_LEN_0F3A14,
- EVEX_LEN_0F3A15,
- EVEX_LEN_0F3A16,
- EVEX_LEN_0F3A17,
- EVEX_LEN_0F3A18_W_0,
- EVEX_LEN_0F3A18_W_1,
- EVEX_LEN_0F3A19_W_0,
- EVEX_LEN_0F3A19_W_1,
- EVEX_LEN_0F3A1A_W_0,
- EVEX_LEN_0F3A1A_W_1,
- EVEX_LEN_0F3A1B_W_0,
- EVEX_LEN_0F3A1B_W_1,
- EVEX_LEN_0F3A20,
- EVEX_LEN_0F3A21_W_0,
- EVEX_LEN_0F3A22,
- EVEX_LEN_0F3A23_W_0,
- EVEX_LEN_0F3A23_W_1,
- EVEX_LEN_0F3A38_W_0,
- EVEX_LEN_0F3A38_W_1,
- EVEX_LEN_0F3A39_W_0,
- EVEX_LEN_0F3A39_W_1,
- EVEX_LEN_0F3A3A_W_0,
- EVEX_LEN_0F3A3A_W_1,
- EVEX_LEN_0F3A3B_W_0,
- EVEX_LEN_0F3A3B_W_1,
- EVEX_LEN_0F3A43_W_0,
- EVEX_LEN_0F3A43_W_1
+ EVEX_LEN_0F385A_M_0,
+ EVEX_LEN_0F385B_M_0,
+ EVEX_LEN_0F38C6_M_0,
+ EVEX_LEN_0F38C7_M_0,
+ EVEX_LEN_0F3A00,
+ EVEX_LEN_0F3A01,
+ EVEX_LEN_0F3A18,
+ EVEX_LEN_0F3A19,
+ EVEX_LEN_0F3A1A,
+ EVEX_LEN_0F3A1B,
+ EVEX_LEN_0F3A23,
+ EVEX_LEN_0F3A38,
+ EVEX_LEN_0F3A39,
+ EVEX_LEN_0F3A3A,
+ EVEX_LEN_0F3A3B,
+ EVEX_LEN_0F3A43
};
enum
EVEX_W_0FD2,
EVEX_W_0FD3,
EVEX_W_0FD4,
- EVEX_W_0FD6_L_0,
+ EVEX_W_0FD6,
EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2,
EVEX_W_0FE6_P_3,
EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
- EVEX_W_0F3819,
- EVEX_W_0F381A,
- EVEX_W_0F381B,
+ EVEX_W_0F3819_L_n,
+ EVEX_W_0F381A_M_0_L_n,
+ EVEX_W_0F381B_M_0_L_2,
EVEX_W_0F381E,
EVEX_W_0F381F,
EVEX_W_0F3820_P_1,
EVEX_W_0F383A_P_1,
EVEX_W_0F3852_P_1,
EVEX_W_0F3859,
- EVEX_W_0F385A,
- EVEX_W_0F385B,
+ EVEX_W_0F385A_M_0_L_n,
+ EVEX_W_0F385B_M_0_L_2,
EVEX_W_0F3870,
EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
EVEX_W_0F387A,
EVEX_W_0F387B,
EVEX_W_0F3883,
- EVEX_W_0F3891,
- EVEX_W_0F3893,
- EVEX_W_0F38A1,
- EVEX_W_0F38A3,
- EVEX_W_0F38C7_R_1_M_0,
- EVEX_W_0F38C7_R_2_M_0,
- EVEX_W_0F38C7_R_5_M_0,
- EVEX_W_0F38C7_R_6_M_0,
-
- EVEX_W_0F3A00,
- EVEX_W_0F3A01,
+
EVEX_W_0F3A05,
EVEX_W_0F3A08,
EVEX_W_0F3A09,
EVEX_W_0F3A0A,
EVEX_W_0F3A0B,
- EVEX_W_0F3A18,
- EVEX_W_0F3A19,
- EVEX_W_0F3A1A,
- EVEX_W_0F3A1B,
+ EVEX_W_0F3A18_L_n,
+ EVEX_W_0F3A19_L_n,
+ EVEX_W_0F3A1A_L_2,
+ EVEX_W_0F3A1B_L_2,
EVEX_W_0F3A21,
- EVEX_W_0F3A23,
- EVEX_W_0F3A38,
- EVEX_W_0F3A39,
- EVEX_W_0F3A3A,
- EVEX_W_0F3A3B,
+ EVEX_W_0F3A23_L_n,
+ EVEX_W_0F3A38_L_n,
+ EVEX_W_0F3A39_L_n,
+ EVEX_W_0F3A3A_L_2,
+ EVEX_W_0F3A3B_L_2,
EVEX_W_0F3A42,
- EVEX_W_0F3A43,
+ EVEX_W_0F3A43_L_n,
EVEX_W_0F3A70,
EVEX_W_0F3A72,
};
{ "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
{ "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
},
- /* REG_0FXOP_09_01_L_0 */
+ /* REG_XOP_09_01_L_0 */
{
{ Bad_Opcode },
{ "blcfill", { VexGdq, Edq }, 0 },
{ "blsic", { VexGdq, Edq }, 0 },
{ "t1mskc", { VexGdq, Edq }, 0 },
},
- /* REG_0FXOP_09_02_L_0 */
+ /* REG_XOP_09_02_L_0 */
{
{ Bad_Opcode },
{ "blcmsk", { VexGdq, Edq }, 0 },
{ Bad_Opcode },
{ "blci", { VexGdq, Edq }, 0 },
},
- /* REG_0FXOP_09_12_M_1_L_0 */
+ /* REG_XOP_09_12_M_1_L_0 */
{
{ "llwpcb", { Edq }, 0 },
{ "slwpcb", { Edq }, 0 },
},
- /* REG_0FXOP_0A_12_L_0 */
+ /* REG_XOP_0A_12_L_0 */
{
{ "lwpins", { VexGdq, Ed, Id }, 0 },
{ "lwpval", { VexGdq, Ed, Id }, 0 },
{ "lidt", { M }, 0 },
},
+ /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
{
- /* X86_64_0F24 */
- { "movZ", { Em, Td }, 0 },
+ { Bad_Opcode },
+ { "uiret", { Skip_MODRM }, 0 },
},
+ /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
{
- /* X86_64_0F26 */
- { "movZ", { Td, Em }, 0 },
+ { Bad_Opcode },
+ { "testui", { Skip_MODRM }, 0 },
},
- /* X86_64_VEX_0F3849 */
+ /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
{
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
+ { "clui", { Skip_MODRM }, 0 },
},
- /* X86_64_VEX_0F384B */
+ /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
{
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
+ { "stui", { Skip_MODRM }, 0 },
},
- /* X86_64_VEX_0F385C */
+ /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
{
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
+ { "rmpadjust", { Skip_MODRM }, 0 },
},
- /* X86_64_VEX_0F385E */
+ /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
{
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
+ { "rmpupdate", { Skip_MODRM }, 0 },
},
- /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
+ /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
{
{ Bad_Opcode },
- { "uiret", { Skip_MODRM }, 0 },
+ { "psmash", { Skip_MODRM }, 0 },
},
- /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
{
- { Bad_Opcode },
- { "testui", { Skip_MODRM }, 0 },
+ /* X86_64_0F24 */
+ { "movZ", { Em, Td }, 0 },
},
- /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
{
- { Bad_Opcode },
- { "clui", { Skip_MODRM }, 0 },
+ /* X86_64_0F26 */
+ { "movZ", { Td, Em }, 0 },
},
- /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
+ /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
{
{ Bad_Opcode },
- { "stui", { Skip_MODRM }, 0 },
+ { "senduipi", { Eq }, 0 },
},
- /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
+ /* X86_64_VEX_0F3849 */
{
{ Bad_Opcode },
- { "rmpadjust", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
},
- /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
+ /* X86_64_VEX_0F384B */
{
{ Bad_Opcode },
- { "rmpupdate", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
},
- /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
+ /* X86_64_VEX_0F385C */
{
{ Bad_Opcode },
- { "psmash", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
},
- /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
+ /* X86_64_VEX_0F385E */
{
{ Bad_Opcode },
- { "senduipi", { Eq }, 0 },
+ { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
},
};
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
+ { MOD_TABLE (MOD_XOP_09_12) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* VEX_LEN_0FXOP_09_01 */
{
- { REG_TABLE (REG_0FXOP_09_01_L_0) },
+ { REG_TABLE (REG_XOP_09_01_L_0) },
},
/* VEX_LEN_0FXOP_09_02 */
{
- { REG_TABLE (REG_0FXOP_09_02_L_0) },
+ { REG_TABLE (REG_XOP_09_02_L_0) },
},
/* VEX_LEN_0FXOP_09_12_M_1 */
{
- { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
+ { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
},
/* VEX_LEN_0FXOP_09_82_W_0 */
/* VEX_LEN_0FXOP_0A_12 */
{
- { REG_TABLE (REG_0FXOP_0A_12_L_0) },
+ { REG_TABLE (REG_XOP_0A_12_L_0) },
},
};
};
static const struct dis386 mod_table[][2] = {
+ {
+ /* MOD_62_32BIT */
+ { "bound{S|}", { Gv, Ma }, 0 },
+ { EVEX_TABLE (EVEX_0F) },
+ },
{
/* MOD_8D */
{ "leaS", { Gv, M }, 0 },
},
+ {
+ /* MOD_C4_32BIT */
+ { "lesS", { Gv, Mp }, 0 },
+ { VEX_C4_TABLE (VEX_0F) },
+ },
+ {
+ /* MOD_C5_32BIT */
+ { "ldsS", { Gv, Mp }, 0 },
+ { VEX_C5_TABLE (VEX_0F) },
+ },
{
/* MOD_C6_REG_7 */
{ Bad_Opcode },
{ Bad_Opcode },
{ REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
},
- {
- /* MOD_62_32BIT */
- { "bound{S|}", { Gv, Ma }, 0 },
- { EVEX_TABLE (EVEX_0F) },
- },
- {
- /* MOD_C4_32BIT */
- { "lesS", { Gv, Mp }, 0 },
- { VEX_C4_TABLE (VEX_0F) },
- },
- {
- /* MOD_C5_32BIT */
- { "ldsS", { Gv, Mp }, 0 },
- { VEX_C5_TABLE (VEX_0F) },
- },
{
/* MOD_VEX_0F12_PREFIX_0 */
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
{ "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
},
{
- /* MOD_VEX_0FXOP_09_12 */
+ /* MOD_XOP_09_12 */
{ Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
},
{ "nopQ", { Ev }, PREFIX_IGNORED },
{ "nopQ", { Ev }, PREFIX_IGNORED },
},
- {
- /* RM_0F3A0F_P_1_MOD_3_REG_0 */
- { "hreset", { Skip_MODRM, Ib }, 0 },
- },
{
/* RM_0FAE_REG_6_MOD_3 */
{ "mfence", { Skip_MODRM }, 0 },
{
/* RM_0FAE_REG_7_MOD_3 */
{ "sfence", { Skip_MODRM }, 0 },
-
+ },
+ {
+ /* RM_0F3A0F_P_1_MOD_3_REG_0 */
+ { "hreset", { Skip_MODRM, Ib }, 0 },
},
{
/* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
case 128:
vindex = 0;
break;
+ case 512:
+ /* This allows re-using in particular table entries where only
+ 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
+ if (vex.evex)
+ {
case 256:
- vindex = 1;
- break;
+ vindex = 1;
+ break;
+ }
+ /* Fall through. */
default:
abort ();
break;
for (p = info->disassembler_options; p != NULL; )
{
- if (CONST_STRNEQ (p, "amd64"))
+ if (startswith (p, "amd64"))
isa64 = amd64;
- else if (CONST_STRNEQ (p, "intel64"))
+ else if (startswith (p, "intel64"))
isa64 = intel64;
- else if (CONST_STRNEQ (p, "x86-64"))
+ else if (startswith (p, "x86-64"))
{
address_mode = mode_64bit;
priv.orig_sizeflag |= AFLAG | DFLAG;
}
- else if (CONST_STRNEQ (p, "i386"))
+ else if (startswith (p, "i386"))
{
address_mode = mode_32bit;
priv.orig_sizeflag |= AFLAG | DFLAG;
}
- else if (CONST_STRNEQ (p, "i8086"))
+ else if (startswith (p, "i8086"))
{
address_mode = mode_16bit;
priv.orig_sizeflag &= ~(AFLAG | DFLAG);
}
- else if (CONST_STRNEQ (p, "intel"))
+ else if (startswith (p, "intel"))
{
intel_syntax = 1;
- if (CONST_STRNEQ (p + 5, "-mnemonic"))
+ if (startswith (p + 5, "-mnemonic"))
intel_mnemonic = 1;
}
- else if (CONST_STRNEQ (p, "att"))
+ else if (startswith (p, "att"))
{
intel_syntax = 0;
- if (CONST_STRNEQ (p + 3, "-mnemonic"))
+ if (startswith (p + 3, "-mnemonic"))
intel_mnemonic = 0;
}
- else if (CONST_STRNEQ (p, "addr"))
+ else if (startswith (p, "addr"))
{
if (address_mode == mode_64bit)
{
priv.orig_sizeflag |= AFLAG;
}
}
- else if (CONST_STRNEQ (p, "data"))
+ else if (startswith (p, "data"))
{
if (p[4] == '1' && p[5] == '6')
priv.orig_sizeflag &= ~DFLAG;
else if (p[4] == '3' && p[5] == '2')
priv.orig_sizeflag |= DFLAG;
}
- else if (CONST_STRNEQ (p, "suffix"))
+ else if (startswith (p, "suffix"))
priv.orig_sizeflag |= SUFFIX_ALWAYS;
p = strchr (p, ',');
origins in all_prefixes. */
used_prefixes &= ~PREFIX_OPCODE;
if (last_data_prefix >= 0)
- all_prefixes[last_repz_prefix] = 0x66;
+ all_prefixes[last_data_prefix] = 0x66;
if (last_repz_prefix >= 0)
all_prefixes[last_repz_prefix] = 0xf3;
if (last_repnz_prefix >= 0)
}
else if (l == 1 && last[0] == 'X')
{
- if (!need_vex || !vex.evex)
+ if (!vex.evex)
abort ();
if (intel_syntax
|| ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
static void
intel_operand_size (int bytemode, int sizeflag)
{
- if (vex.evex
- && vex.b
+ if (vex.b
&& (bytemode == x_mode
|| bytemode == evex_half_bcst_xmmq_mode))
{
if (!need_vex)
abort ();
- if (!vex.evex)
- {
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- }
+ if (vex.w)
+ oappend ("QWORD PTR ");
else
- {
- switch (vex.length)
- {
- case 128:
- oappend ("XMMWORD PTR ");
- break;
- case 256:
- oappend ("YMMWORD PTR ");
- break;
- case 512:
- oappend ("ZMMWORD PTR ");
- break;
- default:
- abort ();
- }
- }
- break;
- case vex_vsib_q_w_d_mode:
- case vex_vsib_d_w_d_mode:
- if (!need_vex || !vex.evex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- oappend ("QWORD PTR ");
- break;
- case 256:
- oappend ("XMMWORD PTR ");
- break;
- case 512:
- oappend ("YMMWORD PTR ");
- break;
- default:
- abort ();
- }
-
+ oappend ("DWORD PTR ");
break;
case mask_bd_mode:
if (!need_vex || vex.length != 128)
/* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
if (vex.b
&& bytemode != x_mode
- && bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode)
{
BadOp ();
/* fall through */
case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
- case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
case evex_x_gscat_mode:
shift = vex.w ? 3 : 2;
break;
case x_mode:
case evex_half_bcst_xmmq_mode:
- case xmmq_mode:
if (vex.b)
{
shift = vex.w ? 3 : 2;
/* Fall through. */
case xmmqd_mode:
case xmmdw_mode:
+ case xmmq_mode:
case ymmq_mode:
case evex_x_nobcst_mode:
case x_swap_mode:
switch (bytemode)
{
case vex_vsib_d_w_dq_mode:
- case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
if (!need_vex)
abort ();
if (vex.evex)
break;
case 256:
if (!vex.w
- || bytemode == vex_vsib_q_w_dq_mode
- || bytemode == vex_vsib_q_w_d_mode)
+ || bytemode == vex_vsib_q_w_dq_mode)
indexes64 = indexes32 = names_ymm;
else
indexes64 = indexes32 = names_xmm;
break;
case 512:
if (!vex.w
- || bytemode == vex_vsib_q_w_dq_mode
- || bytemode == vex_vsib_q_w_d_mode)
+ || bytemode == vex_vsib_q_w_dq_mode)
indexes64 = indexes32 = names_zmm;
else
indexes64 = indexes32 = names_ymm;
oappend (scratchbuf);
}
}
- if (vex.evex && vex.b
+ if (vex.b
&& (bytemode == x_mode
- || bytemode == xmmq_mode
|| bytemode == evex_half_bcst_xmmq_mode))
{
if (vex.w
- || bytemode == xmmq_mode
|| bytemode == evex_half_bcst_xmmq_mode)
{
switch (vex.length)
reg += 16;
}
- if (need_vex
- && bytemode != xmm_mode
- && bytemode != xmmq_mode
- && bytemode != evex_half_bcst_xmmq_mode
- && bytemode != ymm_mode
- && bytemode != tmm_mode
- && bytemode != scalar_mode)
- {
- switch (vex.length)
- {
- case 128:
- names = names_xmm;
- break;
- case 256:
- if (vex.w
- || (bytemode != vex_vsib_q_w_dq_mode
- && bytemode != vex_vsib_q_w_d_mode))
- names = names_ymm;
- else
- names = names_xmm;
- break;
- case 512:
- names = names_zmm;
- break;
- default:
- abort ();
- }
- }
- else if (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode)
+ if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
{
switch (vex.length)
{
abort ();
}
}
+ else if (bytemode == ymm_mode)
+ names = names_ymm;
else if (bytemode == tmm_mode)
{
modrm.reg = reg;
}
names = names_tmm;
}
- else if (bytemode == ymm_mode)
- names = names_ymm;
+ else if (need_vex
+ && bytemode != xmm_mode
+ && bytemode != scalar_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ names = names_xmm;
+ break;
+ case 256:
+ if (vex.w
+ || bytemode != vex_vsib_q_w_dq_mode)
+ names = names_ymm;
+ else
+ names = names_xmm;
+ break;
+ case 512:
+ if (vex.w
+ || bytemode != vex_vsib_q_w_dq_mode)
+ names = names_zmm;
+ else
+ names = names_ymm;
+ break;
+ default:
+ abort ();
+ }
+ }
else
names = names_xmm;
oappend (names[reg]);
{
case vex_mode:
case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
names = names_xmm;
break;
case dq_mode:
names = names_ymm;
break;
case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
names = vex.w ? names_ymm : names_xmm;
break;
case mask_bd_mode:
projects / deliverable / binutils-gdb.git / blobdiff