-/* Copyright 2007 Free Software Foundation, Inc.
+/* Copyright 2007, 2008 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
{ "CPU_GENERIC32_FLAGS",
"Cpu186|Cpu286|Cpu386" },
{ "CPU_GENERIC64_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuLM" },
{ "CPU_NONE_FLAGS",
"0" },
{ "CPU_I186_FLAGS",
{ "CPU_P2_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX" },
{ "CPU_P3_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE" },
{ "CPU_P4_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2" },
{ "CPU_NOCONA_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" },
{ "CPU_CORE_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" },
{ "CPU_CORE2_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" },
{ "CPU_K6_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX" },
{ "CPU_K6_2_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow" },
{ "CPU_ATHLON_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuMMX|Cpu3dnow|Cpu3dnowA" },
{ "CPU_K8_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
{ "CPU_AMDFAM10_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
+ "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
{ "CPU_MMX_FLAGS",
"CpuMMX" },
{ "CPU_SSE_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE" },
+ "CpuMMX|CpuSSE" },
{ "CPU_SSE2_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2" },
+ "CpuMMX|CpuSSE|CpuSSE2" },
{ "CPU_SSE3_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3" },
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" },
{ "CPU_SSSE3_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" },
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" },
{ "CPU_SSE4_1_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_1_Or_5" },
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" },
{ "CPU_SSE4_2_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5" },
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" },
+ { "CPU_VMX_FLAGS",
+ "CpuVMX" },
+ { "CPU_SMX_FLAGS",
+ "CpuSMX" },
+ { "CPU_XSAVE_FLAGS",
+ "CpuXsave" },
+ { "CPU_AES_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
+ { "CPU_PCLMUL_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
+ { "CPU_FMA_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
+ { "CPU_MOVBE_FLAGS",
+ "CpuMovbe" },
+ { "CPU_EPT_FLAGS",
+ "CpuEPT" },
{ "CPU_3DNOW_FLAGS",
"CpuMMX|Cpu3dnow" },
{ "CPU_3DNOWA_FLAGS",
- "CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA" },
+ "CpuMMX|Cpu3dnow|Cpu3dnowA" },
{ "CPU_PADLOCK_FLAGS",
"CpuPadLock" },
{ "CPU_SVME_FLAGS",
"CpuSVME" },
{ "CPU_SSE4A_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
{ "CPU_ABM_FLAGS",
"CpuABM" },
{ "CPU_SSE5_FLAGS",
- "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5"},
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5"},
+ { "CPU_AVX_FLAGS",
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" },
};
static initializer operand_type_init [] =
"RegMMX" },
{ "OPERAND_TYPE_REGXMM",
"RegXMM" },
+ { "OPERAND_TYPE_REGYMM",
+ "RegYMM" },
{ "OPERAND_TYPE_ESSEG",
"EsSeg" },
{ "OPERAND_TYPE_ACC32",
- "Reg32|Acc" },
+ "Reg32|Acc|Dword" },
{ "OPERAND_TYPE_ACC64",
- "Reg64|Acc" },
+ "Reg64|Acc|Qword" },
+ { "OPERAND_TYPE_INOUTPORTREG",
+ "InOutPortReg" },
{ "OPERAND_TYPE_REG16_INOUTPORTREG",
"Reg16|InOutPortReg" },
{ "OPERAND_TYPE_DISP16_32",
"Imm32|Imm32S|Imm64|Disp32" },
{ "OPERAND_TYPE_IMM32_32S_64_DISP32_64",
"Imm32|Imm32S|Imm64|Disp32|Disp64" },
+ { "OPERAND_TYPE_VEX_IMM4",
+ "VEX_Imm4" },
};
typedef struct bitfield
BITFIELD (CpuK6),
BITFIELD (CpuK8),
BITFIELD (CpuMMX),
- BITFIELD (CpuMMX2),
BITFIELD (CpuSSE),
BITFIELD (CpuSSE2),
BITFIELD (CpuSSE3),
BITFIELD (CpuSSSE3),
BITFIELD (CpuSSE4_1),
BITFIELD (CpuSSE4_2),
+ BITFIELD (CpuAVX),
BITFIELD (CpuSSE4a),
BITFIELD (CpuSSE5),
- BITFIELD (CpuSSE4_1_Or_5),
BITFIELD (Cpu3dnow),
BITFIELD (Cpu3dnowA),
BITFIELD (CpuPadLock),
BITFIELD (CpuVMX),
BITFIELD (CpuSMX),
BITFIELD (CpuABM),
+ BITFIELD (CpuXsave),
+ BITFIELD (CpuAES),
+ BITFIELD (CpuPCLMUL),
+ BITFIELD (CpuFMA),
BITFIELD (CpuLM),
+ BITFIELD (CpuMovbe),
+ BITFIELD (CpuEPT),
BITFIELD (Cpu64),
BITFIELD (CpuNo64),
#ifdef CpuUnused
BITFIELD (No_sSuf),
BITFIELD (No_qSuf),
BITFIELD (No_ldSuf),
- BITFIELD (No_xSuf),
- BITFIELD (CheckSize),
- BITFIELD (Byte),
- BITFIELD (Word),
- BITFIELD (Dword),
- BITFIELD (QWord),
- BITFIELD (Xmmword),
BITFIELD (FWait),
BITFIELD (IsString),
BITFIELD (RegKludge),
BITFIELD (FirstXmm0),
+ BITFIELD (Implicit1stXmm0),
BITFIELD (ByteOkIntel),
BITFIELD (ToDword),
BITFIELD (ToQword),
BITFIELD (Drex),
BITFIELD (Drexv),
BITFIELD (Drexc),
+ BITFIELD (Vex),
+ BITFIELD (Vex256),
+ BITFIELD (VexNDD),
+ BITFIELD (VexNDS),
+ BITFIELD (VexW0),
+ BITFIELD (VexW1),
+ BITFIELD (Vex0F),
+ BITFIELD (Vex0F38),
+ BITFIELD (Vex0F3A),
+ BITFIELD (Vex3Sources),
+ BITFIELD (VexImmExt),
+ BITFIELD (SSE2AVX),
+ BITFIELD (NoAVX),
BITFIELD (OldGcc),
BITFIELD (ATTMnemonic),
- BITFIELD (IntelMnemonic),
+ BITFIELD (ATTSyntax),
+ BITFIELD (IntelSyntax),
};
static bitfield operand_types[] =
BITFIELD (FloatReg),
BITFIELD (RegMMX),
BITFIELD (RegXMM),
+ BITFIELD (RegYMM),
BITFIELD (Imm8),
BITFIELD (Imm8S),
BITFIELD (Imm16),
BITFIELD (JumpAbsolute),
BITFIELD (EsSeg),
BITFIELD (RegMem),
+ BITFIELD (Mem),
+ BITFIELD (Byte),
+ BITFIELD (Word),
+ BITFIELD (Dword),
+ BITFIELD (Fword),
+ BITFIELD (Qword),
+ BITFIELD (Tbyte),
+ BITFIELD (Xmmword),
+ BITFIELD (Ymmword),
+ BITFIELD (Unspecified),
+ BITFIELD (Anysize),
+ BITFIELD (Vex_Imm4),
#ifdef OTUnused
BITFIELD (OTUnused),
#endif
};
+static int lineno;
+static const char *filename;
+
static int
compare (const void *x, const void *y)
{
process_copyright (FILE *fp)
{
fprintf (fp, "/* This file is automatically generated by i386-gen. Do not edit! */\n\
-/* Copyright 2007 Free Software Foundation, Inc.\n\
+/* Copyright 2007, 2008 Free Software Foundation, Inc.\n\
\n\
This file is part of the GNU opcodes library.\n\
\n\
if (strcmp (f, "CpuSledgehammer") == 0)
f= "CpuK8";
+ else if (strcmp (f, "Mmword") == 0)
+ f= "Qword";
+ else if (strcmp (f, "Oword") == 0)
+ f= "Xmmword";
for (i = 0; i < size; i++)
if (strcasecmp (array[i].name, f) == 0)
return;
}
- printf ("Unknown bitfield: %s\n", f);
- abort ();
+ fail (_("%s: %d: Unknown bitfield: %s\n"), filename, lineno, f);
}
static void
static void
process_i386_opcodes (FILE *table)
{
- FILE *fp = fopen ("i386-opc.tbl", "r");
+ FILE *fp;
char buf[2048];
unsigned int i;
char *str, *p, *last;
char *opcode_length;
char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS];
+ filename = "i386-opc.tbl";
+ fp = fopen (filename, "r");
+
if (fp == NULL)
fail (_("can't find i386-opc.tbl for reading, errno = %s\n"),
xstrerror (errno));
if (fgets (buf, sizeof (buf), fp) == NULL)
break;
+ lineno++;
+
p = remove_leading_whitespaces (buf);
/* Skip comments. */
static void
process_i386_registers (FILE *table)
{
- FILE *fp = fopen ("i386-reg.tbl", "r");
+ FILE *fp;
char buf[2048];
char *str, *p, *last;
char *reg_name, *reg_type, *reg_flags, *reg_num;
+ char *dw2_32_num, *dw2_64_num;
+ filename = "i386-reg.tbl";
+ fp = fopen (filename, "r");
if (fp == NULL)
fail (_("can't find i386-reg.tbl for reading, errno = %s\n"),
xstrerror (errno));
if (fgets (buf, sizeof (buf), fp) == NULL)
break;
+ lineno++;
+
p = remove_leading_whitespaces (buf);
/* Skip comments. */
/* Find reg_num. */
reg_num = next_field (str, ',', &str);
+ if (str >= last)
+ abort ();
+
fprintf (table, " { \"%s\",\n ", reg_name);
process_i386_operand_type (table, reg_type, 0, "\t");
- fprintf (table, ",\n %s, %s },\n", reg_flags, reg_num);
+ /* Find 32-bit Dwarf2 register number. */
+ dw2_32_num = next_field (str, ',', &str);
+
+ if (str >= last)
+ abort ();
+
+ /* Find 64-bit Dwarf2 register number. */
+ dw2_64_num = next_field (str, ',', &str);
+
+ fprintf (table, ",\n %s, %s, { %s, %s } },\n",
+ reg_flags, reg_num, dw2_32_num, dw2_64_num);
}
fclose (fp);