[AArch64] Add SVE condition codes

[deliverable/binutils-gdb.git] / opcodes / i386-gen.c

diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 6ebad474bb596a9068e417d521d772ef1009bfc5..bf4a021d42662089608d2ccd370667444d09d5b2 100644 (file)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -223,8 +223,6 @@ static initializer cpu_flag_init[] =
     "unknown" },
   { "CPU_IAMCU_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586" },
-  { "CPU_IAMCU_COMPAT_FLAGS",
-    "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuNo64|CpuNop" },
   { "CPU_ADX_FLAGS",
     "CpuADX" },
   { "CPU_RDSEED_FLAGS",
@@ -259,6 +257,8 @@ static initializer cpu_flag_init[] =
     "CpuOSPKE" },
   { "CPU_RDPID_FLAGS",
     "CpuRDPID" },
+  { "CPU_PTWRITE_FLAGS",
+    "CpuPTWRITE" },
   { "CPU_ANY_X87_FLAGS",
     "CPU_ANY_287_FLAGS|Cpu8087" },
   { "CPU_ANY_287_FLAGS",
@@ -511,6 +511,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
   BITFIELD (CpuRDPID),
+  BITFIELD (CpuPTWRITE),
   BITFIELD (CpuRegMMX),
   BITFIELD (CpuRegXMM),
   BITFIELD (CpuRegYMM),