[AArch64][SVE 27/32] Add SVE integer immediate operands

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index a93c1f39084e2505ceea7d6e5530d649817945d8..05004084b4d9bdc3d5d03c6d356483b0720550ba 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -202,14 +202,22 @@ enum
   CpuOSPKE,
   /* RDPID instruction required */
   CpuRDPID,
+  /* PTWRITE instruction required */
+  CpuPTWRITE,
+  /* MMX register support required */
+  CpuRegMMX,
+  /* XMM register support required */
+  CpuRegXMM,
+  /* YMM register support required */
+  CpuRegYMM,
+  /* ZMM register support required */
+  CpuRegZMM,
+  /* Mask register support required */
+  CpuRegMask,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
   CpuNo64,
-  /* AMD64 support required  */
-  CpuAMD64,
-  /* Intel64 support required  */
-  CpuIntel64,
   /* The last bitfield in i386_cpu_flags.  */
   CpuMax = CpuNo64
 };
@@ -314,10 +322,14 @@ typedef union i386_cpu_flags
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
       unsigned int cpurdpid:1;
+      unsigned int cpuptwrite:1;
+      unsigned int cpuregmmx:1;
+      unsigned int cpuregxmm:1;
+      unsigned int cpuregymm:1;
+      unsigned int cpuregzmm:1;
+      unsigned int cpuregmask:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
-      unsigned int cpuamd64:1;
-      unsigned int cpuintel64:1;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
 #endif
@@ -558,6 +570,10 @@ enum
   ATTSyntax,
   /* Intel syntax.  */
   IntelSyntax,
+  /* AMD64.  */
+  AMD64,
+  /* Intel64.  */
+  Intel64,
   /* The last bitfield in i386_opcode_modifier.  */
   Opcode_Modifier_Max
 };
@@ -626,6 +642,8 @@ typedef struct i386_opcode_modifier
   unsigned int attmnemonic:1;
   unsigned int attsyntax:1;
   unsigned int intelsyntax:1;
+  unsigned int amd64:1;
+  unsigned int intel64:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */