#define CpuSSE4_2 (CpuSSE4_1 + 1)
/* SSE5 support required */
#define CpuSSE5 (CpuSSE4_2 + 1)
+/* SSE4.1 or SSE5 support required */
+#define CpuSSE4_1_Or_5 (CpuSSE5 + 1)
/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuSSE5 + 1)
+#define CpuLM (CpuSSE4_1_Or_5 + 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpusse5:1;
+ unsigned int cpusse4_1_or_5:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#define No_sSuf (No_lSuf + 1)
/* q suffix on instruction illegal */
#define No_qSuf (No_sSuf + 1)
+/* long double suffix on instruction illegal */
+#define No_ldSuf (No_qSuf + 1)
/* x suffix on instruction illegal */
-#define No_xSuf (No_qSuf + 1)
+#define No_xSuf (No_ldSuf + 1)
+/* check PTR size on instruction */
+#define CheckSize (No_xSuf + 1)
+/* BYTE PTR on instruction */
+#define Byte (CheckSize + 1)
+/* WORD PTR on instruction */
+#define Word (Byte + 1)
+/* DWORD PTR on instruction */
+#define Dword (Word + 1)
+/* QWORD PTR on instruction */
+#define QWord (Dword + 1)
+/* XMMWORD PTR on instruction */
+#define Xmmword (QWord + 1)
/* instruction needs FWAIT */
-#define FWait (No_xSuf + 1)
+#define FWait (Xmmword + 1)
/* quick test for string instructions */
#define IsString (FWait + 1)
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
#define RegKludge (IsString + 1)
+/* The first operand must be xmm0 */
+#define FirstXmm0 (RegKludge + 1)
+/* BYTE is OK in Intel syntax. */
+#define ByteOkIntel (FirstXmm0 + 1)
+/* Convert to DWORD */
+#define ToDword (ByteOkIntel + 1)
+/* Convert to QWORD */
+#define ToQword (ToDword + 1)
+/* Address prefix changes operand 0 */
+#define AddrPrefixOp0 (ToQword + 1)
/* opcode is a prefix */
-#define IsPrefix (RegKludge + 1)
+#define IsPrefix (AddrPrefixOp0 + 1)
/* instruction has extension in 8 bit imm */
#define ImmExt (IsPrefix + 1)
/* instruction don't need Rex64 prefix. */
#define Drexv (Drex + 1)
/* special DREX for comparisons */
#define Drexc (Drexv + 1)
+/* Compatible with old (<= 2.8.1) versions of gcc */
+#define OldGcc (Drexc + 1)
+/* AT&T mnemonic. */
+#define ATTMnemonic (OldGcc + 1)
+/* Intel mnemonic. */
+#define IntelMnemonic (ATTMnemonic + 1)
/* The last bitfield in i386_opcode_modifier. */
-#define Opcode_Modifier_Max Drexc
+#define Opcode_Modifier_Max IntelMnemonic
typedef struct i386_opcode_modifier
{
unsigned int no_lsuf:1;
unsigned int no_ssuf:1;
unsigned int no_qsuf:1;
+ unsigned int no_ldsuf:1;
unsigned int no_xsuf:1;
+ unsigned int checksize:1;
+ unsigned int byte:1;
+ unsigned int word:1;
+ unsigned int dword:1;
+ unsigned int qword:1;
+ unsigned int xmmword:1;
unsigned int fwait:1;
unsigned int isstring:1;
unsigned int regkludge:1;
+ unsigned int firstxmm0:1;
+ unsigned int byteokintel:1;
+ unsigned int todword:1;
+ unsigned int toqword:1;
+ unsigned int addrprefixop0:1;
unsigned int isprefix:1;
unsigned int immext:1;
unsigned int norex64:1;
unsigned int drex:1;
unsigned int drexv:1;
unsigned int drexc:1;
+ unsigned int oldgcc:1;
+ unsigned int attmnemonic:1;
+ unsigned int intelmnemonic:1;
} i386_opcode_modifier;
/* Position of operand_type bits. */