Copyright 2007
Free Software Foundation, Inc.
- This file is part of GAS, the GNU Assembler.
+ This file is part of the GNU opcodes library.
- GAS is free software; you can redistribute it and/or modify
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- GAS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
#define CpuVMX 0x40000 /* VMX Instructions required */
#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
-#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
+#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
#define CpuABM 0x200000 /* ABM New Instructions required */
+#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */
+#define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */
+
+/* SSE4.1/4.2 Instructions required */
+#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
/* The default value for unknown CPUs - enable all features to avoid problems. */
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
- |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
+ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
+ |CpuSSE4_2|CpuABM|CpuSSE4a)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
#define W 0x2 /* set if operands can be words or dwords
encoded the canonical way */
#define Modrm 0x4 /* insn has a modrm byte. */
-#define ShortForm 0x10 /* register is in low 3 bits of opcode */
-#define Jump 0x40 /* special case for jump insns. */
-#define JumpDword 0x80 /* call and jump */
-#define JumpByte 0x100 /* loop and jecxz */
-#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
-#define FloatMF 0x400 /* FP insn memory format bit, sized by 0x4 */
-#define FloatR 0x800 /* src/dest swap for floats. */
-#define FloatD 0x1000 /* has float insn direction bit. */
-#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
-#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
-#define Size64 0x8000 /* needs size prefix if in 64-bit mode */
-#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
-#define DefaultSize 0x20000 /* default insn size depends on mode */
-#define No_bSuf 0x40000 /* b suffix on instruction illegal */
-#define No_wSuf 0x80000 /* w suffix on instruction illegal */
-#define No_lSuf 0x100000 /* l suffix on instruction illegal */
-#define No_sSuf 0x200000 /* s suffix on instruction illegal */
-#define No_qSuf 0x400000 /* q suffix on instruction illegal */
-#define No_xSuf 0x800000 /* x suffix on instruction illegal */
-#define FWait 0x1000000 /* instruction needs FWAIT */
-#define IsString 0x2000000 /* quick test for string instructions */
-#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
-#define IsPrefix 0x8000000 /* opcode is a prefix */
-#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
-#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
-#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
-#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
+#define ShortForm 0x8 /* register is in low 3 bits of opcode */
+#define Jump 0x10 /* special case for jump insns. */
+#define JumpDword 0x20 /* call and jump */
+#define JumpByte 0x40 /* loop and jecxz */
+#define JumpInterSegment 0x80 /* special case for intersegment leaps/calls */
+#define FloatMF 0x100 /* FP insn memory format bit, sized by 0x4 */
+#define FloatR 0x200 /* src/dest swap for floats. */
+#define FloatD 0x400 /* has float insn direction bit. */
+#define Size16 0x800 /* needs size prefix if in 32-bit mode */
+#define Size32 0x1000 /* needs size prefix if in 16-bit mode */
+#define Size64 0x2000 /* needs size prefix if in 64-bit mode */
+#define IgnoreSize 0x4000 /* instruction ignores operand size prefix */
+#define DefaultSize 0x8000 /* default insn size depends on mode */
+#define No_bSuf 0x10000 /* b suffix on instruction illegal */
+#define No_wSuf 0x20000 /* w suffix on instruction illegal */
+#define No_lSuf 0x40000 /* l suffix on instruction illegal */
+#define No_sSuf 0x80000 /* s suffix on instruction illegal */
+#define No_qSuf 0x100000 /* q suffix on instruction illegal */
+#define No_xSuf 0x200000 /* x suffix on instruction illegal */
+#define FWait 0x400000 /* instruction needs FWAIT */
+#define IsString 0x800000 /* quick test for string instructions */
+#define RegKludge 0x1000000 /* fake an extra reg operand for clr, imul
+ and special register processing for
+ some instructions. */
+#define IsPrefix 0x2000000 /* opcode is a prefix */
+#define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */
+#define NoRex64 0x8000000 /* instruction don't need Rex64 prefix. */
+#define Rex64 0x10000000 /* instruction require Rex64 prefix. */
+#define Ugh 0x20000000 /* deprecated fp insn, gets a warning */
/* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g.
#define RegXMM 0x20000000 /* XMM registers in PIII */
#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
- /* InvMem is for instructions with a modrm byte that only allow a
- general register encoding in the i.tm.mode and i.tm.regmem fields,
- eg. control reg moves. They really ought to support a memory form,
- but don't, so we add an InvMem flag to the register operand to
- indicate that it should be encoded in the i.tm.regmem field. */
-#define InvMem 0x80000000
+ /* RegMem is for instructions with a modrm byte where the register
+ destination operand should be encoded in the mod and regmem fields.
+ Normally, it will be encoded in the reg field. We add a RegMem
+ flag to the destination register operand to indicate that it should
+ be encoded in the regmem field. */
+#define RegMem 0x80000000
#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
#define WordReg (Reg16|Reg32|Reg64)
#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
-#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
+#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */
/* The following aliases are defined because the opcode table
carefully specifies the allowed memory types for each instruction.
At the moment we can only tell a memory reference size by the
extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;
-extern const reg_entry i386_float_regtab[];
-extern const unsigned int i386_float_regtab_size;
typedef struct
{
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