#define CpuSSE4_1 (CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2 (CpuSSE4_1 + 1)
+/* SSE5 support required */
+#define CpuSSE5 (CpuSSE4_2 + 1)
/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuSSE4_2 + 1)
+#define CpuLM (CpuSSE5 + 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-#define CpuUnused (CpuNo64 + 1)
+#define CpuUnused (CpuMax + 1)
/* We can check if an instruction is available with array instead
of bitfield. */
unsigned int cpuabm:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
+ unsigned int cpusse5:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#define Rex64 (NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh (Rex64 + 1)
+#define Drex (Ugh + 1)
+/* instruction needs DREX with multiple encodings for memory ops */
+#define Drexv (Drex + 1)
+/* special DREX for comparisons */
+#define Drexc (Drexv + 1)
/* The last bitfield in i386_opcode_modifier. */
-#define Opcode_Modifier_Max Ugh
+#define Opcode_Modifier_Max Drexc
typedef struct i386_opcode_modifier
{
unsigned int norex64:1;
unsigned int rex64:1;
unsigned int ugh:1;
+ unsigned int drex:1;
+ unsigned int drexv:1;
+ unsigned int drexc:1;
} i386_opcode_modifier;
/* Position of operand_type bits. */
/* If you get a compiler error for zero width of the unused field,
comment it out. */
#if 0
-#define OTUnused (RegMem + 1)
+#define OTUnused (OTMax + 1)
#endif
typedef union i386_operand_type
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
- If this template has no extension opcode (the usual case) use None */
+ If this template has no extension opcode (the usual case) use None
+ Instructions with Drex use this to specify 2 bits for OC */
unsigned int extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
+ /* Opcode length. */
+ unsigned char opcode_length;
+
/* cpu feature flags */
i386_cpu_flags cpu_flags;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
+#define RegRip ((unsigned int ) ~0)
+#define RegEip (RegRip - 1)
+/* EIZ and RIZ are fake index registers. */
+#define RegEiz (RegEip - 1)
+#define RegRiz (RegEiz - 1)
}
reg_entry;