CpuSSE4_2,
/* AVX support required */
CpuAVX,
+ /* AVX2 support required */
+ CpuAVX2,
/* Intel L1OM support required */
CpuL1OM,
+ /* Intel K1OM support required */
+ CpuK1OM,
/* Xsave/xrstor New Instructions support required */
CpuXsave,
/* Xsaveopt New Instructions support required */
CpuXOP,
/* LWP support required */
CpuLWP,
+ /* BMI support required */
+ CpuBMI,
+ /* TBM support required */
+ CpuTBM,
/* MOVBE Instruction support required */
CpuMovbe,
/* EPT Instructions required */
CpuRdRnd,
/* F16C Instructions required */
CpuF16C,
+ /* Intel BMI2 support required */
+ CpuBMI2,
+ /* LZCNT support required */
+ CpuLZCNT,
+ /* INVPCID Instructions required */
+ CpuINVPCID,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
/* 64bit support required */
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
+ unsigned int cpuavx2:1;
unsigned int cpul1om:1;
+ unsigned int cpuk1om:1;
unsigned int cpuxsave:1;
unsigned int cpuxsaveopt:1;
unsigned int cpuaes:1;
unsigned int cpufma4:1;
unsigned int cpuxop:1;
unsigned int cpulwp:1;
+ unsigned int cpubmi:1;
+ unsigned int cputbm:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
unsigned int cpufsgsbase:1;
unsigned int cpurdrnd:1;
unsigned int cpuf16c:1;
+ unsigned int cpubmi2:1;
+ unsigned int cpulzcnt:1;
+ unsigned int cpuinvpcid:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
Size32,
/* needs size prefix if in 64-bit mode */
Size64,
+ /* check register size. */
+ CheckRegSize,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
IgnoreSize,
VEX.DDS. The second register operand is encoded in VEX.vvvv
where the content of first source register will be overwritten
by the result.
- For assembler, there are no difference between VEX.NDS and
- VEX.DDS.
- 2. VEX.NDD. Register destination is encoded in VEX.vvvv.
+ VEX.NDD2. The second destination register operand is encoded in
+ VEX.vvvv for instructions with 2 destination register operands.
+ For assembler, there are no difference between VEX.NDS, VEX.DDS
+ and VEX.NDD2.
+ 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
+ instructions with 1 destination register operand.
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
of the operands can access a memory location.
*/
VexSources,
/* instruction has VEX 8 bit imm */
VexImmExt,
+ /* Instruction with vector SIB byte:
+ 1: 128bit vector register.
+ 2: 256bit vector register.
+ */
+#define VecSIB128 1
+#define VecSIB256 2
+ VecSIB,
/* SSE to AVX support required */
SSE2AVX,
/* No AVX equivalent */
unsigned int size16:1;
unsigned int size32:1;
unsigned int size64:1;
+ unsigned int checkregsize:1;
unsigned int ignoresize:1;
unsigned int defaultsize:1;
unsigned int no_bsuf:1;
unsigned int vexopcode:3;
unsigned int vexsources:2;
unsigned int veximmext:1;
+ unsigned int vecsib:2;
unsigned int sse2avx:1;
unsigned int noavx:1;
unsigned int oldgcc:1;