Run --gc-sections tests only if supported.

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index f90dff59d442b782205d13dc1e1e5a906a0df5c2..8d5dade9ab2121895200ecee8efb895b62a6287a 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -92,8 +92,12 @@ enum
   CpuSSE4_2,
   /* AVX support required */
   CpuAVX,
+  /* AVX2 support required */
+  CpuAVX2,
   /* Intel L1OM support required */
   CpuL1OM,
+  /* Intel K1OM support required */
+  CpuK1OM,
   /* Xsave/xrstor New Instructions support required */
   CpuXsave,
   /* Xsaveopt New Instructions support required */
@@ -126,6 +130,12 @@ enum
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,
+  /* Intel BMI2 support required */
+  CpuBMI2,
+  /* LZCNT support required */
+  CpuLZCNT,
+  /* INVPCID Instructions required */
+  CpuINVPCID,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
   /* 64bit support required  */
@@ -181,7 +191,9 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpuavx:1;
+      unsigned int cpuavx2:1;
       unsigned int cpul1om:1;
+      unsigned int cpuk1om:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
@@ -198,6 +210,9 @@ typedef union i386_cpu_flags
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;
+      unsigned int cpubmi2:1;
+      unsigned int cpulzcnt:1;
+      unsigned int cpuinvpcid:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -307,9 +322,12 @@ enum
        VEX.DDS.  The second register operand is encoded in VEX.vvvv 
        where the content of first source register will be overwritten
        by the result.
-       For assembler, there are no difference between VEX.NDS and
-       VEX.DDS.
-     2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
+       VEX.NDD2.  The second destination register operand is encoded in
+       VEX.vvvv for instructions with 2 destination register operands.
+       For assembler, there are no difference between VEX.NDS, VEX.DDS
+       and VEX.NDD2.
+     2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
+     instructions with 1 destination register operand.
      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
        of the operands can access a memory location.
    */
@@ -350,6 +368,13 @@ enum
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
+  /* Instruction with vector SIB byte:
+       1: 128bit vector register.
+       2: 256bit vector register.
+   */
+#define VecSIB128      1
+#define VecSIB256      2
+  VecSIB,
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
@@ -412,6 +437,7 @@ typedef struct i386_opcode_modifier
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int veximmext:1;
+  unsigned int vecsib:2;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int oldgcc:1;