* osdata.c (info_osdata_command): Filter out "Title" columns

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 239f9de54d06e484945f637489e297143215517d..96bdfb54ead50550ffe02e3eb40cd97b6f1572bd 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright 2007, 2008, 2009, 2010
+   Copyright 2007, 2008, 2009, 2010, 2012
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
@@ -92,8 +92,12 @@ enum
   CpuSSE4_2,
   /* AVX support required */
   CpuAVX,
+  /* AVX2 support required */
+  CpuAVX2,
   /* Intel L1OM support required */
   CpuL1OM,
+  /* Intel K1OM support required */
+  CpuK1OM,
   /* Xsave/xrstor New Instructions support required */
   CpuXsave,
   /* Xsaveopt New Instructions support required */
@@ -110,6 +114,10 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
+  /* BMI support required */
+  CpuBMI,
+  /* TBM support required */
+  CpuTBM,
   /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -122,6 +130,18 @@ enum
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,
+  /* Intel BMI2 support required */
+  CpuBMI2,
+  /* LZCNT support required */
+  CpuLZCNT,
+  /* HLE support required */
+  CpuHLE,
+  /* RTM support required */
+  CpuRTM,
+  /* INVPCID Instructions required */
+  CpuINVPCID,
+  /* VMFUNC Instruction required */
+  CpuVMFUNC,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
   /* 64bit support required  */
@@ -177,7 +197,9 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpuavx:1;
+      unsigned int cpuavx2:1;
       unsigned int cpul1om:1;
+      unsigned int cpuk1om:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
@@ -186,12 +208,20 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
+      unsigned int cpubmi:1;
+      unsigned int cputbm:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;
+      unsigned int cpubmi2:1;
+      unsigned int cpulzcnt:1;
+      unsigned int cpuhle:1;
+      unsigned int cpurtm:1;
+      unsigned int cpuinvpcid:1;
+      unsigned int cpuvmfunc:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -237,6 +267,8 @@ enum
   Size32,
   /* needs size prefix if in 64-bit mode */
   Size64,
+  /* check register size.  */
+  CheckRegSize,
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
   IgnoreSize,
@@ -267,6 +299,18 @@ enum
   FirstXmm0,
   /* An implicit xmm0 as the first operand */
   Implicit1stXmm0,
+  /* The HLE prefix is OK:
+     1. With a LOCK prefix.
+     2. With or without a LOCK prefix.
+     3. With a RELEASE (0xf3) prefix.
+   */
+#define HLEPrefixNone          0
+#define HLEPrefixLock          1
+#define HLEPrefixAny           2
+#define HLEPrefixRelease       3
+  HLEPrefixOk,
+  /* An instruction on which a "rep" prefix is acceptable.  */
+  RepPrefixOk,
   /* Convert to DWORD */
   ToDword,
   /* Convert to QWORD */
@@ -296,12 +340,15 @@ enum
      0: VEX.vvvv must be 1111b.
      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
        the content of source registers will be preserved.
-       VEX.DDS.  The second register operand is encoded in VEX.vvvv 
+       VEX.DDS.  The second register operand is encoded in VEX.vvvv
        where the content of first source register will be overwritten
        by the result.
-       For assembler, there are no difference between VEX.NDS and
-       VEX.DDS.
-     2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
+       VEX.NDD2.  The second destination register operand is encoded in
+       VEX.vvvv for instructions with 2 destination register operands.
+       For assembler, there are no difference between VEX.NDS, VEX.DDS
+       and VEX.NDD2.
+     2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
+     instructions with 1 destination register operand.
      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
        of the operands can access a memory location.
    */
@@ -342,6 +389,13 @@ enum
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
+  /* Instruction with vector SIB byte:
+       1: 128bit vector register.
+       2: 256bit vector register.
+   */
+#define VecSIB128      1
+#define VecSIB256      2
+  VecSIB,
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
@@ -375,6 +429,7 @@ typedef struct i386_opcode_modifier
   unsigned int size16:1;
   unsigned int size32:1;
   unsigned int size64:1;
+  unsigned int checkregsize:1;
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
   unsigned int no_bsuf:1;
@@ -389,6 +444,8 @@ typedef struct i386_opcode_modifier
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
+  unsigned int hleprefixok:2;
+  unsigned int repprefixok:1;
   unsigned int todword:1;
   unsigned int toqword:1;
   unsigned int addrprefixop0:1;
@@ -403,6 +460,7 @@ typedef struct i386_opcode_modifier
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int veximmext:1;
+  unsigned int vecsib:2;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int oldgcc:1;
@@ -607,7 +665,7 @@ typedef struct insn_template
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None 
+     If this template has no extension opcode (the usual case) use None
      Instructions */
   unsigned int extension_opcode;
 #define None 0xffff            /* If no extension_opcode is possible.  */