FirstXmm0,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
- /* BYTE is OK in Intel syntax. */
- ByteOkIntel,
/* Convert to DWORD */
ToDword,
/* Convert to QWORD */
/* insn has VEX prefix:
1: 128bit VEX prefix.
2: 256bit VEX prefix.
+ 3: Scalar VEX prefix.
*/
-#define VEX128 1
-#define VEX256 2
+#define VEX128 1
+#define VEX256 2
+#define VEXScalar 3
Vex,
- /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
- We use VexNDS on insns with VEX DDS since the register-only source
- is the second source register. */
- VexNDS,
- /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
- VexNDD,
- /* insn has VEX NDD. Register destination is encoded in Vex prefix
- and one of the operands can access a memory location. */
- VexLWP,
+ /* How to encode VEX.vvvv:
+ 0: VEX.vvvv must be 1111b.
+ 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
+ the content of source registers will be preserved.
+ VEX.DDS. The second register operand is encoded in VEX.vvvv
+ where the content of first source register will be overwritten
+ by the result.
+ For assembler, there are no difference between VEX.NDS and
+ VEX.DDS.
+ 2. VEX.NDD. Register destination is encoded in VEX.vvvv.
+ 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
+ of the operands can access a memory location.
+ */
+#define VEXXDS 1
+#define VEXNDD 2
+#define VEXLWP 3
+ VexVVVV,
/* How the VEX.W bit is used:
0: Set by the REX.W bit.
1: VEX.W0. Should always be 0.
unsigned int regkludge:1;
unsigned int firstxmm0:1;
unsigned int implicit1stxmm0:1;
- unsigned int byteokintel:1;
unsigned int todword:1;
unsigned int toqword:1;
unsigned int addrprefixop0:1;
unsigned int rex64:1;
unsigned int ugh:1;
unsigned int vex:2;
- unsigned int vexnds:1;
- unsigned int vexndd:1;
- unsigned int vexlwp:1;
+ unsigned int vexvvvv:2;
unsigned int vexw:2;
unsigned int vexopcode:3;
unsigned int vexsources:2;