gdb: constify remote files_info

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 3137a6706e1d0c99d328f0e04da6bb749f23c23b..ba4edd712758de1fe6ffc3a59af830389ff78c46 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright 2007, 2008, 2009
+   Copyright 2007, 2008, 2009, 2010
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
@@ -252,8 +252,6 @@ enum
   FirstXmm0,
   /* An implicit xmm0 as the first operand */
   Implicit1stXmm0,
-  /* BYTE is OK in Intel syntax. */
-  ByteOkIntel,
   /* Convert to DWORD */
   ToDword,
   /* Convert to QWORD */
@@ -273,19 +271,29 @@ enum
   /* insn has VEX prefix:
        1: 128bit VEX prefix.
        2: 256bit VEX prefix.
+       3: Scalar VEX prefix.
    */
-#define VEX128 1
-#define VEX256 2
+#define VEX128         1
+#define VEX256         2
+#define VEXScalar      3
   Vex,
-  /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
-     We use VexNDS on insns with VEX DDS since the register-only source
-     is the second source register.  */
-  VexNDS,
-  /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
-  VexNDD,
-  /* insn has VEX NDD. Register destination is encoded in Vex prefix
-     and one of the operands can access a memory location.  */
-  VexLWP,
+  /* How to encode VEX.vvvv:
+     0: VEX.vvvv must be 1111b.
+     1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
+       the content of source registers will be preserved.
+       VEX.DDS.  The second register operand is encoded in VEX.vvvv 
+       where the content of first source register will be overwritten
+       by the result.
+       For assembler, there are no difference between VEX.NDS and
+       VEX.DDS.
+     2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
+     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
+       of the operands can access a memory location.
+   */
+#define VEXXDS 1
+#define VEXNDD 2
+#define VEXLWP 3
+  VexVVVV,
   /* How the VEX.W bit is used:
      0: Set by the REX.W bit.
      1: VEX.W0.  Should always be 0.
@@ -366,7 +374,6 @@ typedef struct i386_opcode_modifier
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
-  unsigned int byteokintel:1;
   unsigned int todword:1;
   unsigned int toqword:1;
   unsigned int addrprefixop0:1;
@@ -376,9 +383,7 @@ typedef struct i386_opcode_modifier
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
-  unsigned int vexnds:1;
-  unsigned int vexndd:1;
-  unsigned int vexlwp:1;
+  unsigned int vexvvvv:2;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
@@ -495,6 +500,9 @@ enum
   /* Any memory size.  */
   Anysize,
 
+  /* Vector 4 bit immediate.  */
+  Vec_Imm4,
+
   /* The last bitfield in i386_operand_type.  */
   OTMax
 };
@@ -556,6 +564,7 @@ typedef union i386_operand_type
       unsigned int ymmword:1;
       unsigned int unspecified:1;
       unsigned int anysize:1;
+      unsigned int vec_imm4:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif