CpuRDPID,
/* PTWRITE instruction required */
CpuPTWRITE,
+ /* CET instruction support required */
+ CpuCET,
/* MMX register support required */
CpuRegMMX,
/* XMM register support required */
/* If you get a compiler error for zero width of the unused field,
comment it out. */
+#if 0
#define CpuUnused (CpuMax + 1)
+#endif
/* We can check if an instruction is available with array instead
of bitfield. */
unsigned int cpuospke:1;
unsigned int cpurdpid:1;
unsigned int cpuptwrite:1;
+ unsigned int cpucet:1;
unsigned int cpuregmmx:1;
unsigned int cpuregxmm:1;
unsigned int cpuregymm:1;
D = 0,
/* set if operands can be words or dwords encoded the canonical way */
W,
- /* Skip the current insn and use the next insn in i386-opc.tbl to swap
- operand in encoding. */
- S,
+ /* load form instruction. Must be placed before store form. */
+ Load,
/* insn has a modrm byte. */
Modrm,
/* register is in low 3 bits of opcode */
IsString,
/* quick test if branch instruction is MPX supported */
BNDPrefixOk,
+ /* quick test if NOTRACK prefix is supported */
+ NoTrackPrefixOk,
/* quick test for lockable instructions */
IsLockable,
/* fake an extra reg operand for clr, imul and special register
{
unsigned int d:1;
unsigned int w:1;
- unsigned int s:1;
+ unsigned int load:1;
unsigned int modrm:1;
unsigned int shortform:1;
unsigned int jump:1;
unsigned int fwait:1;
unsigned int isstring:1;
unsigned int bndprefixok:1;
+ unsigned int notrackprefixok:1;
unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;