gdb/testsuite/

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 6c48dbc54e62f58370ff127b10ed1e6220dd55a9..cee1303ac4ae7d5561f8b538e79b54ebfe9f8a7c 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -102,6 +102,8 @@ enum
   CpuFMA,
   /* FMA4 support required */
   CpuFMA4,
+  /* LWP support required */
+  CpuLWP,
   /* MOVBE Instuction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -168,6 +170,7 @@ typedef union i386_cpu_flags
       unsigned int cpupclmul:1;
       unsigned int cpufma:1;
       unsigned int cpufma4:1;
+      unsigned int cpulwp:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -237,6 +240,8 @@ enum
   FWait,
   /* quick test for string instructions */
   IsString,
+  /* quick test for lockable instructions */
+  IsLockable,
   /* fake an extra reg operand for clr, imul and special register
      processing for some instructions.  */
   RegKludge,
@@ -273,6 +278,9 @@ enum
   VexNDS,
   /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
   VexNDD,
+  /* insn has VEX NDD. Register destination is encoded in Vex prefix
+     and one of the operands can access a memory location.  */
+  VexLWP,
   /* insn has VEX W0. */
   VexW0,
   /* insn has VEX W1. */
@@ -283,6 +291,10 @@ enum
   Vex0F38,
   /* insn has VEX 0x0F3A opcode prefix. */
   Vex0F3A,
+  /* insn has XOP 0x09 opcode prefix. */
+  XOP09,
+  /* insn has XOP 0x0A opcode prefix. */
+  XOP0A,
   /* insn has VEX prefix with 3 soures. */
   Vex3Sources,
   /* instruction has VEX 8 bit imm */
@@ -330,6 +342,7 @@ typedef struct i386_opcode_modifier
   unsigned int no_ldsuf:1;
   unsigned int fwait:1;
   unsigned int isstring:1;
+  unsigned int islockable:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
@@ -345,11 +358,14 @@ typedef struct i386_opcode_modifier
   unsigned int vex:2;
   unsigned int vexnds:1;
   unsigned int vexndd:1;
+  unsigned int vexlwp:1;
   unsigned int vexw0:1;
   unsigned int vexw1:1;
   unsigned int vex0f:1;
   unsigned int vex0f38:1;
   unsigned int vex0f3a:1;
+  unsigned int xop09:1;
+  unsigned int xop0a:1;
   unsigned int vex3sources:1;
   unsigned int veximmext:1;
   unsigned int sse2avx:1;