/* Declarations for Intel 80386 opcode table
- Copyright (C) 2007-2020 Free Software Foundation, Inc.
+ Copyright (C) 2007-2021 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
CpuAVX512_BF16,
/* Intel AVX-512 VP2INTERSECT Instructions support required. */
CpuAVX512_VP2INTERSECT,
+ /* TDX Instructions support required. */
+ CpuTDX,
+ /* Intel AVX VNNI Instructions support required. */
+ CpuAVX_VNNI,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
/* CET instructions support required */
CpuIBT,
CpuSHSTK,
+ /* AMX-INT8 instructions required */
+ CpuAMX_INT8,
+ /* AMX-BF16 instructions required */
+ CpuAMX_BF16,
+ /* AMX-TILE instructions required */
+ CpuAMX_TILE,
/* GFNI instructions required */
CpuGFNI,
/* VAES instructions required */
CpuPCONFIG,
/* WAITPKG instructions required */
CpuWAITPKG,
+ /* UINTR instructions required */
+ CpuUINTR,
/* CLDEMOTE instruction required */
CpuCLDEMOTE,
/* MOVDIRI instruction support required */
CpuMOVDIR64B,
/* ENQCMD instruction required */
CpuENQCMD,
+ /* SERIALIZE instruction required */
+ CpuSERIALIZE,
/* RDPRU instruction required */
CpuRDPRU,
/* MCOMMIT instruction required */
CpuMCOMMIT,
+ /* SEV-ES instruction(s) required */
+ CpuSEV_ES,
+ /* TSXLDTRK instruction required */
+ CpuTSXLDTRK,
+ /* KL instruction support required */
+ CpuKL,
+ /* WideKL instruction support required */
+ CpuWideKL,
+ /* HRESET instruction required */
+ CpuHRESET,
+ /* INVLPGB instructions required */
+ CpuINVLPGB,
+ /* TLBSYNC instructions required */
+ CpuTLBSYNC,
+ /* SNP instructions required */
+ CpuSNP,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
unsigned int cpuavx512_bitalg:1;
unsigned int cpuavx512_bf16:1;
unsigned int cpuavx512_vp2intersect:1;
+ unsigned int cputdx:1;
+ unsigned int cpuavx_vnni:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
unsigned int cpuptwrite:1;
unsigned int cpuibt:1;
unsigned int cpushstk:1;
+ unsigned int cpuamx_int8:1;
+ unsigned int cpuamx_bf16:1;
+ unsigned int cpuamx_tile:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
unsigned int cpuvpclmulqdq:1;
unsigned int cpuwbnoinvd:1;
unsigned int cpupconfig:1;
unsigned int cpuwaitpkg:1;
+ unsigned int cpuuintr:1;
unsigned int cpucldemote:1;
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
unsigned int cpuenqcmd:1;
+ unsigned int cpuserialize:1;
unsigned int cpurdpru:1;
unsigned int cpumcommit:1;
+ unsigned int cpusev_es:1;
+ unsigned int cputsxldtrk:1;
+ unsigned int cpukl:1;
+ unsigned int cpuwidekl:1;
+ unsigned int cpuhreset:1;
+ unsigned int cpuinvlpgb:1;
+ unsigned int cputlbsync:1;
+ unsigned int cpusnp:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
CheckRegSize,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
- IgnoreSize,
+#define IGNORESIZE 1
/* default insn size depends on mode */
- DefaultSize,
+#define DEFAULTSIZE 2
+ MnemonicSize,
/* any memory size */
Anysize,
/* b suffix on instruction illegal */
RegMem,
/* quick test if branch instruction is MPX supported */
BNDPrefixOk,
- /* quick test if NOTRACK prefix is supported */
- NoTrackPrefixOk,
- /* quick test for lockable instructions */
- IsLockable,
/* fake an extra reg operand for clr, imul and special register
processing for some instructions. */
RegKludge,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
- /* The HLE prefix is OK:
- 1. With a LOCK prefix.
- 2. With or without a LOCK prefix.
- 3. With a RELEASE (0xf3) prefix.
- */
-#define HLEPrefixNone 0
-#define HLEPrefixLock 1
-#define HLEPrefixAny 2
-#define HLEPrefixRelease 3
- HLEPrefixOk,
- /* An instruction on which a "rep" prefix is acceptable. */
- RepPrefixOk,
+#define PrefixNone 0
+#define PrefixRep 1
+#define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */
+#define PrefixNoTrack 3
+ /* Prefixes implying "LOCK okay" must come after Lock. All others have
+ to come before. */
+#define PrefixLock 4
+#define PrefixHLELock 5 /* Okay with a LOCK prefix. */
+#define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */
+ PrefixOk,
/* Convert to DWORD */
ToDword,
/* Convert to QWORD */
ImmExt,
/* instruction don't need Rex64 prefix. */
NoRex64,
- /* instruction require Rex64 prefix. */
- Rex64,
/* deprecated fp insn, gets a warning */
Ugh,
+ /* Intel AVX Instructions support via {vex} prefix */
+ PseudoVexPrefix,
/* insn has VEX prefix:
1: 128bit VEX prefix (or operand dependent).
2: 256bit VEX prefix.
#define VEXW1 2
#define VEXWIG 3
VexW,
+ /* Regular opcode prefix:
+ 0: None
+ 1: Add 0x66 opcode prefix.
+ 2: Add 0xf2 opcode prefix.
+ 3: Add 0xf3 opcode prefix.
+ */
+#define PREFIX_NONE 0
+#define PREFIX_0X66 1
+#define PREFIX_0XF2 2
+#define PREFIX_0XF3 3
/* VEX opcode prefix:
0: VEX 0x0F opcode prefix.
1: VEX 0x0F38 opcode prefix.
#define XOP08 3
#define XOP09 4
#define XOP0A 5
- VexOpcode,
+ OpcodePrefix,
/* number of VEX source operands:
0: <= 2 source operands.
1: 2 XOP source operands.
#define XOP2SOURCES 1
#define VEX3SOURCES 2
VexSources,
- /* Instruction with vector SIB byte:
+ /* Instruction with a mandatory SIB byte:
1: 128bit vector register.
2: 256bit vector register.
3: 512bit vector register.
*/
-#define VecSIB128 1
-#define VecSIB256 2
-#define VecSIB512 3
- VecSIB,
+#define VECSIB128 1
+#define VECSIB256 2
+#define VECSIB512 3
+#define SIBMEM 4
+ SIB,
+
/* SSE to AVX support required */
SSE2AVX,
/* No AVX equivalent */
*/
ImplicitQuadGroup,
+ /* Two source operands are swapped. */
+ SwapSources,
+
/* Support encoding optimization. */
Optimize,
unsigned int floatr:1;
unsigned int size:2;
unsigned int checkregsize:1;
- unsigned int ignoresize:1;
- unsigned int defaultsize:1;
+ unsigned int mnemonicsize:2;
unsigned int anysize:1;
unsigned int no_bsuf:1;
unsigned int no_wsuf:1;
unsigned int isstring:2;
unsigned int regmem:1;
unsigned int bndprefixok:1;
- unsigned int notrackprefixok:1;
- unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int implicit1stxmm0:1;
- unsigned int hleprefixok:2;
- unsigned int repprefixok:1;
+ unsigned int prefixok:3;
unsigned int todword:1;
unsigned int toqword:1;
unsigned int addrprefixopreg:1;
unsigned int isprefix:1;
unsigned int immext:1;
unsigned int norex64:1;
- unsigned int rex64:1;
unsigned int ugh:1;
+ unsigned int pseudovexprefix:1;
unsigned int vex:2;
unsigned int vexvvvv:2;
unsigned int vexw:2;
- unsigned int vexopcode:3;
+ unsigned int opcodeprefix:3;
unsigned int vexsources:2;
- unsigned int vecsib:2;
+ unsigned int sib:3;
unsigned int sse2avx:1;
unsigned int noavx:1;
unsigned int evex:3;
unsigned int disp8memshift:3;
unsigned int nodefmask:1;
unsigned int implicitquadgroup:1;
+ unsigned int swapsources:1;
unsigned int optimize:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
Ymmword,
/* ZMMWORD size. */
Zmmword,
+ /* TMMWORD size. */
+ Tmmword,
/* Unspecified memory size. */
Unspecified,
unsigned int xmmword:1;
unsigned int ymmword:1;
unsigned int zmmword:1;
+ unsigned int tmmword:1;
unsigned int unspecified:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
+/* Pseudo prefixes. */
+#define Prefix_Disp8 0 /* {disp8} */
+#define Prefix_Disp16 1 /* {disp16} */
+#define Prefix_Disp32 2 /* {disp32} */
+#define Prefix_Load 3 /* {load} */
+#define Prefix_Store 4 /* {store} */
+#define Prefix_VEX 5 /* {vex} */
+#define Prefix_VEX3 6 /* {vex3} */
+#define Prefix_EVEX 7 /* {evex} */
+#define Prefix_REX 8 /* {rex} */
+#define Prefix_NoOptimize 9 /* {nooptimize} */
+
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
/* these are for register name --> number & type hash lookup */
typedef struct
{
- char *reg_name;
+ const char *reg_name;
i386_operand_type reg_type;
unsigned char reg_flags;
#define RegRex 0x1 /* Extended register. */
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