/* Declarations for Intel 80386 opcode table
- Copyright 2007, 2008, 2009
+ Copyright 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
Cpu586,
/* i686 or better required */
Cpu686,
- /* CLFLUSH Instuction support required */
+ /* CLFLUSH Instruction support required */
CpuClflush,
- /* SYSCALL Instuctions support required */
+ /* NOP Instruction support required */
+ CpuNop,
+ /* SYSCALL Instructions support required */
CpuSYSCALL,
/* Floating point support required */
Cpu8087,
CpuAVX,
/* Intel L1OM support required */
CpuL1OM,
- /* Xsave/xrstor New Instuctions support required */
+ /* Xsave/xrstor New Instructions support required */
CpuXsave,
+ /* Xsaveopt New Instructions support required */
+ CpuXsaveopt,
/* AES support required */
CpuAES,
/* PCLMUL support required */
CpuXOP,
/* LWP support required */
CpuLWP,
- /* MOVBE Instuction support required */
+ /* MOVBE Instruction support required */
CpuMovbe,
/* EPT Instructions required */
CpuEPT,
- /* RDTSCP Instuction support required */
+ /* RDTSCP Instruction support required */
CpuRdtscp,
+ /* FSGSBASE Instructions required */
+ CpuFSGSBase,
+ /* RDRND Instructions required */
+ CpuRdRnd,
+ /* F16C Instructions required */
+ CpuF16C,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
/* 64bit support required */
unsigned int cpui586:1;
unsigned int cpui686:1;
unsigned int cpuclflush:1;
+ unsigned int cpunop:1;
unsigned int cpusyscall:1;
unsigned int cpu8087:1;
unsigned int cpu287:1;
unsigned int cpuavx:1;
unsigned int cpul1om:1;
unsigned int cpuxsave:1;
+ unsigned int cpuxsaveopt:1;
unsigned int cpuaes:1;
unsigned int cpupclmul:1;
unsigned int cpufma:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
+ unsigned int cpufsgsbase:1;
+ unsigned int cpurdrnd:1;
+ unsigned int cpuf16c:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
Size32,
/* needs size prefix if in 64-bit mode */
Size64,
+ /* check register size. */
+ CheckRegSize,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
IgnoreSize,
FirstXmm0,
/* An implicit xmm0 as the first operand */
Implicit1stXmm0,
- /* BYTE is OK in Intel syntax. */
- ByteOkIntel,
/* Convert to DWORD */
ToDword,
/* Convert to QWORD */
/* insn has VEX prefix:
1: 128bit VEX prefix.
2: 256bit VEX prefix.
+ 3: Scalar VEX prefix.
*/
-#define VEX128 1
-#define VEX256 2
+#define VEX128 1
+#define VEX256 2
+#define VEXScalar 3
Vex,
- /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
- We use VexNDS on insns with VEX DDS since the register-only source
- is the second source register. */
- VexNDS,
- /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
- VexNDD,
- /* insn has VEX NDD. Register destination is encoded in Vex prefix
- and one of the operands can access a memory location. */
- VexLWP,
+ /* How to encode VEX.vvvv:
+ 0: VEX.vvvv must be 1111b.
+ 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
+ the content of source registers will be preserved.
+ VEX.DDS. The second register operand is encoded in VEX.vvvv
+ where the content of first source register will be overwritten
+ by the result.
+ For assembler, there are no difference between VEX.NDS and
+ VEX.DDS.
+ 2. VEX.NDD. Register destination is encoded in VEX.vvvv.
+ 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
+ of the operands can access a memory location.
+ */
+#define VEXXDS 1
+#define VEXNDD 2
+#define VEXLWP 3
+ VexVVVV,
/* How the VEX.W bit is used:
0: Set by the REX.W bit.
1: VEX.W0. Should always be 0.
#define VEXW0 1
#define VEXW1 2
VexW,
- /* insn has VEX 0x0F opcode prefix. */
- Vex0F,
- /* insn has VEX 0x0F38 opcode prefix. */
- Vex0F38,
- /* insn has VEX 0x0F3A opcode prefix. */
- Vex0F3A,
- /* insn has XOP 0x08 opcode prefix. */
- XOP08,
- /* insn has XOP 0x09 opcode prefix. */
- XOP09,
- /* insn has XOP 0x0A opcode prefix. */
- XOP0A,
+ /* VEX opcode prefix:
+ 0: VEX 0x0F opcode prefix.
+ 1: VEX 0x0F38 opcode prefix.
+ 2: VEX 0x0F3A opcode prefix
+ 3: XOP 0x08 opcode prefix.
+ 4: XOP 0x09 opcode prefix
+ 5: XOP 0x0A opcode prefix.
+ */
+#define VEX0F 0
+#define VEX0F38 1
+#define VEX0F3A 2
+#define XOP08 3
+#define XOP09 4
+#define XOP0A 5
+ VexOpcode,
/* number of VEX source operands:
- 0: < 2 source operands.
- 1: 2 source operands.
+ 0: <= 2 source operands.
+ 1: 2 XOP source operands.
2: 3 source operands.
*/
-#define VEX2SOURCES 1
+#define XOP2SOURCES 1
#define VEX3SOURCES 2
VexSources,
/* instruction has VEX 8 bit imm */
unsigned int size16:1;
unsigned int size32:1;
unsigned int size64:1;
+ unsigned int checkregsize:1;
unsigned int ignoresize:1;
unsigned int defaultsize:1;
unsigned int no_bsuf:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
unsigned int implicit1stxmm0:1;
- unsigned int byteokintel:1;
unsigned int todword:1;
unsigned int toqword:1;
unsigned int addrprefixop0:1;
unsigned int rex64:1;
unsigned int ugh:1;
unsigned int vex:2;
- unsigned int vexnds:1;
- unsigned int vexndd:1;
- unsigned int vexlwp:1;
+ unsigned int vexvvvv:2;
unsigned int vexw:2;
- unsigned int vex0f:1;
- unsigned int vex0f38:1;
- unsigned int vex0f3a:1;
- unsigned int xop08:1;
- unsigned int xop09:1;
- unsigned int xop0a:1;
+ unsigned int vexopcode:3;
unsigned int vexsources:2;
unsigned int veximmext:1;
unsigned int sse2avx:1;
/* Any memory size. */
Anysize,
+ /* Vector 4 bit immediate. */
+ Vec_Imm4,
+
/* The last bitfield in i386_operand_type. */
OTMax
};
unsigned int ymmword:1;
unsigned int unspecified:1;
unsigned int anysize:1;
+ unsigned int vec_imm4:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif