* src/gdb/target.h: Remove all tests for already defined

[deliverable/binutils-gdb.git] / opcodes / i386-opc.tbl

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index e644a391415f58eeeb82c70c97119c8debc784c1..ec644968dc521d8ee12fcb7973cb2752ee67dc5d 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -909,10 +909,10 @@ fucompi, 1, 0xdfe8, None, 2, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 
 // Pentium4 extensions.
 
-movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 clflush, 1, 0xfae, 0x7, 2, CpuClflush, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-lfence, 0, 0xfae, 0xe8, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
-mfence, 0, 0xfae, 0xf0, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
+lfence, 0, 0xfae, 0xe8, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 }
+mfence, 0, 0xfae, 0xf0, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 }
 // Processors that do not support PAUSE treat this opcode as a NOP instruction.
 pause, 0, 0xf390, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
@@ -1754,17 +1754,19 @@ aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSu
 
 // PCLMUL
 
+pclmulqdq, 3, 0x6644, None, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pclmulqdq, 3, 0x660f3a44, None, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmullqlqdq, 2, 0x6644, 0x0, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmulhqlqdq, 2, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmullqhqdq, 2, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmulhqhqdq, 2, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 
 // AVX instructions.
 
-// We add Imm8 to Vex_Imm4.  We use Imm8 to indicate that the operand
-// is an immediate.  We will check if its value will fit 4 bits.
-
 vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
 vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2359,6 +2361,14 @@ vaesenclast, 3, 0x66dd, None, 1, CpuAVX|CpuAES, Modrm|Vex|Vex0F38|VexNDS|IgnoreS
 vaesimc, 2, 0x66db, None, 1, CpuAVX|CpuAES, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vaeskeygenassist, 3, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 
+// PCLMUL + AVX
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vpclmullqlqdq, 3, 0x6644, 0x0, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vpclmulhqlqdq, 3, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+
 // FMA instructions
 
 vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
@@ -2578,21 +2588,21 @@ pperm, 4, 0x0f2423, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|N
 permps, 4, 0x0f2420, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 permpd, 4, 0x0f2421, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protb, 3, 0x0f2440, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protb, 3, 0x0f7b40, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protb, 3, 0x0f7b40, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protw, 3, 0x0f2441, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protw, 3, 0x0f7b41, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protw, 3, 0x0f7b41, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protd, 3, 0x0f2442, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protd, 3, 0x0f7b42, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8,  RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protd, 3, 0x0f7b42, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8,  RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protq, 3, 0x0f2443, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protq, 3, 0x0f7b43, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protq, 3, 0x0f7b43, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlb, 3, 0x0f2444, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlw, 3, 0x0f2445, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshld, 3, 0x0f2446, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlq, 3, 0x0f2447, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshab, 3, 0x0f2448, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshaw, 3, 0x0f2449, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshad, 3, 0x0f244a, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshaq, 3, 0x0f244b, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshab, 3, 0x0f2448, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshaw, 3, 0x0f2449, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshad, 3, 0x0f244a, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshaq, 3, 0x0f244b, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 comps, 4, 0x0f252c, 0x0, 3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Modrm|Drexc,      { Imm8,            Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM,          RegXMM }
 comeqps, 3, 0x0f252c, 0x0, 3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Modrm|ImmExt|Drexc,      { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM,          RegXMM }
 comltps, 3, 0x0f252c, 0x1, 3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Modrm|ImmExt|Drexc,      { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM,          RegXMM }