/* Assemble Matsushita MN10300 instructions.
- Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This file is part of the GNU opcodes library.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-/* This file is formatted at > 80 columns. Attempting to read it on a
- screeen with less than 80 columns will be difficult. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* This file is formatted at > 80 columns. Attempting to read it
+ on a screeen with less than 80 columns will be difficult. */
#include "sysdep.h"
#include "opcode/mn10300.h"
\f
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED 0
- {0, 0, 0},
+ {0, 0, 0},
/* dn register in the first register operand position. */
#define DN0 (UNUSED+1)
{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
/* 32bit immediate, high 16 bits in the main instruction
- word, 16bits in the extension word.
+ word, 16bits in the extension word.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
/* 32bit immediate, high 16 bits in the main instruction
word, 16bits in the extension word, low 16bits are left
- shifted 8 places.
+ shifted 8 places.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
/* 32bit immediate, high 24 bits in the main instruction
word, 8 in the extension word, low 8 bits are left
- shifted 16 places.
+ shifted 16 places.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
/* Either an open paren or close paren. */
#define PAREN (SIMM16+1)
- {0, 0, MN10300_OPERAND_PAREN},
+ {0, 0, MN10300_OPERAND_PAREN},
/* dn register that appears in the first and second register positions. */
#define DN01 (PAREN+1)
/* + for autoincrement */
#define PLUS (XRM2+1)
- {0, 0, MN10300_OPERAND_PLUS},
+ {0, 0, MN10300_OPERAND_PLUS},
#define XRN02 (PLUS+1)
{4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
#define FDN3 (FDN2+1)
{5, -12, MN10300_OPERAND_FDREG },
-} ;
+} ;
-#define MEM(ADDR) PAREN, ADDR, PAREN
-#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
-#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
-#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
+#define MEM(ADDR) PAREN, ADDR, PAREN
+#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
+#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
+#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
\f
/* The opcode table.
{ "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, XRN02}},
-{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, XRN02}},
+{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}},
+{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}},
{ "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}},
{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-
+
{ 0, 0, 0, 0, 0, 0, {0}},
} ;