/* Assemble Matsushita MN10300 instructions.
- Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
/* This file is formatted at > 80 columns. Attempting to read it on a
screeen with less than 80 columns will be difficult. */
-#include "ansidecl.h"
+#include "sysdep.h"
#include "opcode/mn10300.h"
\f
#define IMM16_PCREL (IMM16+1)
{16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
-/* 16bit unsigned dispacement in a memory operation which
+/* 16bit unsigned displacement in a memory operation which
may promote to a 32bit displacement. */
#define IMM16_MEM (IMM16_PCREL+1)
{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
#define DI (MDR+1)
{2, 2, MN10300_OPERAND_DREG},
-/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
+/* 8 bit signed displacement, may promote to 16bit signed displacement. */
#define SD8 (DI+1)
{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
-/* 16 bit signed displacement, may promote to 32bit dispacement. */
+/* 16 bit signed displacement, may promote to 32bit displacement. */
#define SD16 (SD8+1)
{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define REGS (REGS_SHIFT8+1)
{8, 0, MN10300_OPERAND_REG_LIST},
-/* start-sanitize-am33 */
/* UStack pointer. */
#define USP (REGS+1)
{0, 0, MN10300_OPERAND_USP},
#define RD2 (RD0+1)
{4, -4, MN10300_OPERAND_RREG},
-/* 8 unsigned dispacement in a memory operation which
+/* 8 unsigned displacement in a memory operation which
may promote to a 32bit displacement. */
#define IMM8_MEM (RD2+1)
{8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
#define RI (IMM8_MEM+1)
{4, 4, MN10300_OPERAND_RREG},
-/* 24 bit signed displacement, may promote to 32bit dispacement. */
+/* 24 bit signed displacement, may promote to 32bit displacement. */
#define SD24 (RI+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define SIMM24 (IMM24+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
-/* 16bit unsigned dispacement in a memory operation which
+/* 24bit unsigned displacement in a memory operation which
may promote to a 32bit displacement. */
#define IMM24_MEM (SIMM24+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
-/* 32bit immediate, high 24 bits in the main instruction
- word, 8 in the extension word.
+/* 32bit immediate, high 8 bits in the main instruction
+ word, 24 in the extension word.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
/* 4 bit immediate for dsp instructions. */
#define SIMM4_6 (SIMM4_2+1)
{4, 12, MN10300_OPERAND_SIGNED},
-/* end-sanitize-am33 */
} ;
{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
-/* start-sanitize-am33 */
{ "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}},
{ "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}},
{ "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}},
{ "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
{ "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
-{ "mov", 0xf97a00, 0xffff00, 0x5, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
+{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
{ "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
{ "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
-{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
-{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
-{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
-{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
+{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
+{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
+{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
+{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
-{ "mov", 0xfb7a0000, 0xffff0000, 0x5, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
+{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
-{ "mov", 0xfd7a0000, 0xffff0000, 0x5, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
+{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
-{ "mov", 0xfe7a0000, 0xffff0000, 0x5, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
-/* end-sanitize-am33 */
+{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
/* These must come after most of the other move instructions to avoid matching
a symbolic name with IMMxx operands. Ugh. */
{ "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}},
moves. */
{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}},
{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}},
-/* start-sanitize-am33 */
/* These are the same as the previous non-promoting versions. The am33
does not have restrictions on the offsets used to load/store the stack
pointer. */
{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}},
{ "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}},
{ "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}},
{ "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
{ "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
{ "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
{ "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
{ "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
-/* start-sanitize-am33 */
{ "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
{ "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
{ "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
{ "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
{ "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
{ "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
-{ "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
-{ "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
-{ "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
-{ "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
+{ "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
+{ "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
+{ "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
+{ "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
{ "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
{ "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
{ "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
{ "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
{ "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
{ "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
-/* end-sanitize-am33 */
{ "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
{ "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
{ "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
{ "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
{ "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
{ "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
-/* start-sanitize-am33 */
{ "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
{ "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
{ "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}},
{ "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
{ "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
{ "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
-/* end-sanitize-am33 */
{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
{ "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
-/* start-sanitize-am33 */
{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
{ "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
{ "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
-{ "movhu", 0xf9fa00, 0xffff00, 0x5, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
+{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
-{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
-{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
-{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
-{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
+{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
+{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
+{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
+{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
{ "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
{ "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
-/* end-sanitize-am33 */
{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
-/* start-sanitize-am33 */
{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
{ "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
-{ "movhu", 0xfbfa0000, 0xffff0000, 0x5, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
+{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
-{ "movhu", 0xfdfa0000, 0xffff0000, 0x5, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
+{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
-{ "movhu", 0xfefa0000, 0xffff0000, 0x5, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
-/* end-sanitize-am33 */
+{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
{ "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}},
{ "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}},
-/* start-sanitize-am33 */
{ "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}},
{ "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}},
-/* end-sanitize-am33 */
{ "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}},
-/* start-sanitize-am33 */
{ "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}},
{ "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
{ "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
{ "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}},
{ "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}},
{ "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}},
-/* start-sanitize-am33 */
{ "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
{ "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
{ "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}},
-/* start-sanitize-am33 */
{ "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
{ "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
{ "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
-/* start-sanitize-am33 */
{ "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
{ "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
-/* start-sanitize-am33 */
{ "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "subc", 0xfa8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
-/* end-sanitize-am33 */
{ "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
-/* end-sanitize-am33 */
{ "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
{ "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}},
{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}},
-/* start-sanitize-am33 */
{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
-/* start-sanitize-am33 */
{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
{ "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
{ "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
{ "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
{ "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}},
-/* start-sanitize-am33 */
{ "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
{ "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
-/* start-sanitize-am33 */
{ "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
{ "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
{ "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
-/* start-sanitize-am33 */
{ "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}},
{ "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
-/* start-sanitize-am33 */
{ "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
{ "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
{ "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
-/* start-sanitize-am33 */
{ "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}},
{ "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
-/* start-sanitize-am33 */
{ "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
-/* start-sanitize-am33 */
{ "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
-/* start-sanitize-am33 */
{ "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
{ "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
{ "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
{ "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
-/* start-sanitize-am33 */
/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
them to match last since they do not promote. */
{ "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
{ "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
{ "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
{ "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
{ "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
-/* start-sanitize-am33 */
{ "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
-/* start-sanitize-am33 */
{ "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
{ "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}},
-/* start-sanitize-am33 */
{ "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
-/* start-sanitize-am33 */
{ "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
{ "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
{ "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}},
-/* start-sanitize-am33 */
{ "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
{ "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
-/* start-sanitize-am33 */
{ "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
{ "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
{ "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
-/* end-sanitize-am33 */
{ "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}},
-/* start-sanitize-am33 */
{ "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}},
-/* start-sanitize-am33 */
{ "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
-/* end-sanitize-am33 */
{ "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
{ "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
{ "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}},
{ "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}},
{ "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
{ "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
-/* start-sanitize-am33 */
{ "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
-/* end-sanitize-am33 */
{ "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
-/* start-sanitize-am33 */
{ "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
-/* end-sanitize-am33 */
/* Extension. We need some instruction to trigger "emulated syscalls"
for our simulator. */
-/* start-sanitize-am33 */
{ "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}},
-/* end-sanitize-am33 */
{ "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}},
/* Extension. When talking to the simulator, gdb requires some instruction
both mn10x00 architectures. */
{ "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}},
-/* start-sanitize-am33 */
{ "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
{ "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
{ "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-/* end-sanitize-am33 */
{ 0, 0, 0, 0, 0, 0, {0}},