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[deliverable/binutils-gdb.git] / opcodes / m32c-asm.c

diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c
index 02475eadfc675d05cc0bedf1a651dd66dde4b01d..9407ed8d2d1446bfb1def1d201fe9afe861199cb 100644 (file)
--- a/opcodes/m32c-asm.c
+++ b/opcodes/m32c-asm.c
@@ -503,6 +503,24 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
   return 0;
 }
 
+static const char *
+parse_bit3_S (CGEN_CPU_DESC cd, const char **strp,
+            int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  
+  errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+  if (errmsg)
+    return errmsg;
+
+  if (value < 0 || value > 7)
+    return _("immediate is out of range 0-7");
+
+  *valuep = value;
+  return 0;
+}
+
 static const char *
 parse_lab_5_3 (CGEN_CPU_DESC cd,
               const char **strp,
@@ -794,14 +812,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
                          const CGEN_INSN *insn)
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
-  int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
+  CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
   /* If attributes are absent, assume no restriction.  */
   if (machs == 0)
     machs = ~0;
 
   return ((machs & cd->machs)
-         && (isas & cd->isas));
+          && cgen_bitset_intersect_p (& isas, cd->isas));
 }
 
 /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
@@ -933,6 +951,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_BIT16RN :
       errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst16_rn);
       break;
+    case M32C_OPERAND_BIT3_S :
+      errmsg = parse_bit3_S (cd, strp, M32C_OPERAND_BIT3_S, (long *) (& fields->f_imm3_S));
+      break;
     case M32C_OPERAND_BIT32ANPREFIXED :
       errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed);
       break;