* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.

[deliverable/binutils-gdb.git] / opcodes / m32c-opc.h

diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h
index 4e49ff454d65199b256a550b4a29d227b60f2e73..22ee675986746a146ee450fd76e83927573925b8 100644 (file)
--- a/opcodes/m32c-opc.h
+++ b/opcodes/m32c-opc.h
@@ -286,9 +286,9 @@ typedef enum cgen_insn_type {
  , M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI
  , M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI
  , M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI
+ , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI
  , M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI
  , M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI
  , M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI
@@ -678,17 +678,17 @@ typedef enum cgen_insn_type {
  , M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI
  , M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI
  , M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI
+ , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI
  , M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI
- , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI
+ , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
  , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
  , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
  , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
@@ -1236,7 +1236,7 @@ typedef enum cgen_insn_type {
  , M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
  , M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI
  , M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1L_DST32_2_S_R0_DIRECT_HI
+ , M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI
  , M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI
  , M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED
  , M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI
@@ -1576,16 +1576,34 @@ typedef enum cgen_insn_type {
  , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI
  , M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI
  , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI
- , M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI
- , M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI
- , M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI
+ , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI
+ , M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI
+ , M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI
+ , M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI
+ , M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI
+ , M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI
+ , M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI
+ , M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI
+ , M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI
+ , M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI
  , M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI
  , M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI
  , M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI
@@ -2987,7 +3005,7 @@ typedef enum cgen_insn_type {
  , M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI
  , M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI
  , M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_ADD16_Q_SP, M32C_INSN_ADD16_B_G_SP, M32C_INSN_ADD16_W_G_SP, M32C_INSN_ADD32_L_IMM3_Q
+ , M32C_INSN_ADD16_WQ_SP, M32C_INSN_ADD16_B_G_SP, M32C_INSN_ADD16_W_G_SP, M32C_INSN_ADD32_L_IMM3_Q
  , M32C_INSN_ADD32_L_IMM8_S, M32C_INSN_ADD32_L_IMM16_G, M32C_INSN_DADC16_B_IMM8, M32C_INSN_DADC16_W_IMM16
  , M32C_INSN_DADC16_B_R0H_R0L, M32C_INSN_DADC16_W_R1_R0, M32C_INSN_DADD16_B_IMM8, M32C_INSN_DADD16_W_IMM16
  , M32C_INSN_DADD16_B_R0H_R0L, M32C_INSN_DADD16_W_R1_R0, M32C_INSN_BM16_C, M32C_INSN_BM32_C
@@ -3154,6 +3172,7 @@ struct cgen_fields
   long f_dsp_48_u16;
   long f_dsp_48_s16;
   long f_dsp_64_u16;
+  long f_dsp_8_s24;
   long f_dsp_8_u24;
   long f_dsp_16_u24;
   long f_dsp_24_u24;