This file is used to generate m32r-dis.c.
-Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
-#include "m32r-opc.h"
#include "bfd.h"
+#include "symcat.h"
+#include "m32r-opc.h"
/* ??? The layout of this stuff is still work in progress.
For speed in assembly/disassembly, we use inline functions. That of course
static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int));
+static int extract_normal
+ PARAMS ((PTR, cgen_insn_t, unsigned int, int, int, int, long *));
+static void print_normal
+ PARAMS ((PTR, long, unsigned int, unsigned long, int));
+static void print_keyword
+ PARAMS ((PTR, CGEN_KEYWORD *, long, unsigned int));
static int extract_insn_normal
- PARAMS ((const struct cgen_insn *, void *, cgen_insn_t, struct cgen_fields *));
+ PARAMS ((const CGEN_INSN *, void *, cgen_insn_t, CGEN_FIELDS *));
static void print_insn_normal
- PARAMS ((void *, const struct cgen_insn *, struct cgen_fields *, bfd_vma, int));
+ PARAMS ((void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int));
\f
-/* Default extraction routine.
-
- ATTRS is a mask of the boolean attributes. We only need `unsigned',
- but for generality we take a bitmask of all of them. */
-
-static int
-extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
- void *buf_ctrl;
- cgen_insn_t insn_value;
- unsigned int attrs;
- int start, length, shift, total_length;
- long *valuep;
-{
- long value;
-
-#ifdef CGEN_INT_INSN
-#if 0
- value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length)))
- & ((1 << length) - 1));
-#else
- value = ((insn_value >> (total_length - (start + length)))
- & ((1 << length) - 1));
-#endif
- if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
- && (value & (1 << (length - 1))))
- value -= 1 << length;
-#else
- /* FIXME: unfinished */
-#endif
+/* -- disassembler routines inserted here */
+/* -- dis.c */
- /* This is backwards as we undo the effects of insert_normal. */
- if (shift < 0)
- value >>= -shift;
- else
- value <<= shift;
+/* Immediate values are prefixed with '#'. */
- *valuep = value;
- return 1;
-}
+#define CGEN_PRINT_NORMAL(info, value, attrs, pc, length) \
+do { \
+ if ((attrs) & (1 << CGEN_OPERAND_HASH_PREFIX)) \
+ (*info->fprintf_func) (info->stream, "#"); \
+} while (0)
-/* Default print handler. */
+/* Handle '#' prefixes as operands. */
static void
-print_normal (dis_info, value, attrs, pc, length)
- void *dis_info;
+print_hash (dis_info, value, attrs, pc, length)
+ PTR dis_info;
long value;
unsigned int attrs;
unsigned long pc; /* FIXME: should be bfd_vma */
int length;
{
disassemble_info *info = dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE))
- ; /* nothing to do (??? at least not yet) */
- else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_PCREL_ADDR))
- (*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info);
- /* ??? Not all cases of this are currently caught. */
- else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_ABS_ADDR))
- /* FIXME: Why & 0xffffffff? */
- (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
- else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
- (*info->fprintf_func) (info->stream, "0x%lx", value);
- else
- (*info->fprintf_func) (info->stream, "%ld", value);
+ (*info->fprintf_func) (info->stream, "#");
}
-/* Keyword print handler. */
-
-static void
-print_keyword (dis_info, keyword_table, value, attrs)
- void *dis_info;
- struct cgen_keyword *keyword_table;
- long value;
- CGEN_ATTR *attrs;
-{
- disassemble_info *info = dis_info;
- const struct cgen_keyword_entry *ke;
-
- ke = cgen_keyword_lookup_value (keyword_table, value);
- if (ke != NULL)
- (*info->fprintf_func) (info->stream, "%s", ke->name);
- else
- (*info->fprintf_func) (info->stream, "???");
-}
-\f
-/* -- disassembler routines inserted here */
-/* -- dis.c */
-
#undef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN my_print_insn
char *buf;
int buflen;
{
- unsigned long insn_value;
-
/* 32 bit insn? */
if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
return print_insn (pc, info, buf, buflen);
the handlers.
*/
-CGEN_INLINE int
+int
m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
int opindex;
- void *buf_ctrl;
+ PTR buf_ctrl;
cgen_insn_t insn_value;
- struct cgen_fields *fields;
+ CGEN_FIELDS * fields;
{
int length;
switch (opindex)
{
- case 0 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
+ case M32R_OPERAND_SR :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+ break;
+ case M32R_OPERAND_DR :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+ break;
+ case M32R_OPERAND_SRC1 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+ break;
+ case M32R_OPERAND_SRC2 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
break;
- case 1 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
+ case M32R_OPERAND_SCR :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
break;
- case 2 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
+ case M32R_OPERAND_DCR :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
break;
- case 3 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
+ case M32R_OPERAND_SIMM8 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8);
break;
- case 4 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
+ case M32R_OPERAND_SIMM16 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
break;
- case 5 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
+ case M32R_OPERAND_UIMM4 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm4);
break;
- case 6 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8);
+ case M32R_OPERAND_UIMM5 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm5);
break;
- case 7 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
+ case M32R_OPERAND_UIMM16 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
break;
- case 8 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm4);
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_imm1 = ((value) + (1));
+ }
break;
- case 9 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm5);
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_accd);
break;
- case 10 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_accs);
break;
- case 11 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_hi16);
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, CGEN_FIELDS_BITSIZE (fields), & fields->f_acc);
break;
- case 12 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
break;
- case 13 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
+ case M32R_OPERAND_HI16 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
break;
- case 14 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm24);
+ case M32R_OPERAND_SLO16 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
break;
- case 15 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp8);
+ case M32R_OPERAND_ULO16 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
break;
- case 16 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp16);
+ case M32R_OPERAND_UIMM24 :
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
break;
- case 17 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp24);
+ case M32R_OPERAND_DISP8 :
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_disp8 = ((value) << (2));
+ }
+ break;
+ case M32R_OPERAND_DISP16 :
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_disp16 = ((value) << (2));
+ }
+ break;
+ case M32R_OPERAND_DISP24 :
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_disp24 = ((value) << (2));
+ }
break;
default :
the handlers.
*/
-CGEN_INLINE void
+void
m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
int opindex;
- disassemble_info *info;
- struct cgen_fields *fields;
- int attrs;
+ disassemble_info * info;
+ CGEN_FIELDS * fields;
+ void const * attrs;
bfd_vma pc;
int length;
{
switch (opindex)
{
- case 0 :
+ case M32R_OPERAND_SR :
print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 1 :
+ case M32R_OPERAND_DR :
print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 2 :
+ case M32R_OPERAND_SRC1 :
print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 3 :
+ case M32R_OPERAND_SRC2 :
print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 4 :
+ case M32R_OPERAND_SCR :
print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 5 :
+ case M32R_OPERAND_DCR :
print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 6 :
- print_normal (info, fields->f_simm8, 0, pc, length);
+ case M32R_OPERAND_SIMM8 :
+ print_normal (info, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
- case 7 :
- print_normal (info, fields->f_simm16, 0, pc, length);
+ case M32R_OPERAND_SIMM16 :
+ print_normal (info, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
- case 8 :
- print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ case M32R_OPERAND_UIMM4 :
+ print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case 9 :
- print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ case M32R_OPERAND_UIMM5 :
+ print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case 10 :
- print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ case M32R_OPERAND_UIMM16 :
+ print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ print_normal (info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
- case 11 :
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ print_hash (info, fields->f_nil, 0, pc, length);
+ break;
+ case M32R_OPERAND_HI16 :
print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case 12 :
+ case M32R_OPERAND_SLO16 :
print_normal (info, fields->f_simm16, 0, pc, length);
break;
- case 13 :
+ case M32R_OPERAND_ULO16 :
print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case 14 :
- print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ case M32R_OPERAND_UIMM24 :
+ print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case 15 :
+ case M32R_OPERAND_DISP8 :
print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
- case 16 :
+ case M32R_OPERAND_DISP16 :
print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
- case 17 :
+ case M32R_OPERAND_DISP24 :
print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
}
}
-cgen_extract_fn *m32r_cgen_extract_handlers[] = {
+cgen_extract_fn * m32r_cgen_extract_handlers[] =
+{
0, /* default */
extract_insn_normal,
};
-cgen_print_fn *m32r_cgen_print_handlers[] = {
+cgen_print_fn * m32r_cgen_print_handlers[] =
+{
0, /* default */
print_insn_normal,
};
enum cgen_endian endian;
{
m32r_cgen_init_tables (mach);
- cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
+ cgen_set_cpu (& m32r_cgen_opcode_table, mach, endian);
cgen_dis_init ();
}
+\f
+/* Default extraction routine.
+
+ ATTRS is a mask of the boolean attributes. We only need `unsigned',
+ but for generality we take a bitmask of all of them. */
+
+static int
+extract_normal (buf_ctrl, insn_value, attrs, start, length, total_length, valuep)
+ PTR buf_ctrl;
+ cgen_insn_t insn_value;
+ unsigned int attrs;
+ int start, length, total_length;
+ long *valuep;
+{
+ long value;
+
+#ifdef CGEN_INT_INSN
+#if 0
+ value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length)))
+ & ((1 << length) - 1));
+#else
+ value = ((insn_value >> (total_length - (start + length)))
+ & ((1 << length) - 1));
+#endif
+ if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+ && (value & (1 << (length - 1))))
+ value -= 1 << length;
+#else
+ /* FIXME: unfinished */
+#endif
+
+ *valuep = value;
+
+ /* FIXME: for now */
+ return 1;
+}
+
+/* Default print handler. */
+
+static void
+print_normal (dis_info, value, attrs, pc, length)
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ unsigned long pc; /* FIXME: should be bfd_vma */
+ int length;
+{
+ disassemble_info *info = dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_PRINT_NORMAL (info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_FAKE))
+ ; /* nothing to do (??? at least not yet) */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info);
+ /* ??? Not all cases of this are currently caught. */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ /* FIXME: Why & 0xffffffff? */
+ (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+ else
+ (*info->fprintf_func) (info->stream, "%ld", value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (dis_info, keyword_table, value, attrs)
+ PTR dis_info;
+ CGEN_KEYWORD *keyword_table;
+ long value;
+ unsigned int attrs;
+{
+ disassemble_info *info = dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
\f
/* Default insn extractor.
static int
extract_insn_normal (insn, buf_ctrl, insn_value, fields)
- const struct cgen_insn *insn;
- void *buf_ctrl;
+ const CGEN_INSN *insn;
+ PTR buf_ctrl;
cgen_insn_t insn_value;
- struct cgen_fields *fields;
+ CGEN_FIELDS *fields;
{
- const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
const unsigned char *syn;
- /* ??? Some of the operand extract routines need to know the insn length,
- which might be computed as we go. Set a default value and it'll be
- modified as necessary. */
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
CGEN_INIT_EXTRACT ();
- for (syn = syntax->syntax; *syn; ++syn)
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
{
int length;
continue;
length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn),
- buf_ctrl, insn_value, fields);
+ buf_ctrl, insn_value, fields);
if (length == 0)
return 0;
}
- /* We recognized and successfully extracted this insn.
- If a length is recorded with this insn, it has a fixed length.
- Otherwise we require the syntax string to have a fake operand which
- sets the `length' field in `flds'. */
- /* FIXME: wip */
- if (syntax->length > 0)
- return syntax->length;
- return fields->length;
+ /* We recognized and successfully extracted this insn. */
+ return CGEN_INSN_BITSIZE (insn);
}
/* Default insn printer.
- DIS_INFO is defined as `void *' so the disassembler needn't know anything
+ DIS_INFO is defined as `PTR' so the disassembler needn't know anything
about disassemble_info.
*/
static void
print_insn_normal (dis_info, insn, fields, pc, length)
- void *dis_info;
- const struct cgen_insn *insn;
- struct cgen_fields *fields;
+ PTR dis_info;
+ const CGEN_INSN *insn;
+ CGEN_FIELDS *fields;
bfd_vma pc;
int length;
{
- const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
disassemble_info *info = dis_info;
const unsigned char *syn;
CGEN_INIT_PRINT ();
- for (syn = syntax->syntax; *syn; ++syn)
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
{
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
if (CGEN_SYNTAX_CHAR_P (*syn))
{
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
}
\f
/* Default value for CGEN_PRINT_INSN.
- Given BUFLEN bytes (target byte order) read into BUF, look up the
+ Given BUFLEN bits (target byte order) read into BUF, look up the
insn in the instruction table and disassemble it.
The result is the size of the insn in bytes. */
char *buf;
int buflen;
{
- int i;
unsigned long insn_value;
const CGEN_INSN_LIST *insn_list;
while (insn_list != NULL)
{
const CGEN_INSN *insn = insn_list->insn;
- const struct cgen_syntax *syntax = CGEN_INSN_SYNTAX (insn);
- struct cgen_fields fields;
+ CGEN_FIELDS fields;
int length;
#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the extract
handler. */
- if ((insn_value & syntax->mask) == syntax->value)
+ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
{
/* Printing is handled in two passes. The first pass parses the
machine insn and extracts the fields. The second pass prints
/* We try to have as much common code as possible.
But at this point some targets need to take over. */
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
- but if not possible, try to move this hook elsewhere rather than
+ but if not possible try to move this hook elsewhere rather than
have two hooks. */
length = CGEN_PRINT_INSN (pc, info, buffer, CGEN_BASE_INSN_BITSIZE);
if (length)
projects / deliverable / binutils-gdb.git / blobdiff