Fix arm-epoc-pe build problem:

[deliverable/binutils-gdb.git] / opcodes / m32r-ibld.c

diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 5b785477954f9697e37655b929b887aad6e83448..30c3c6a8ce9c635f0bcdf6a60cde7b3dd0bee178 100644 (file)
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -3,7 +3,7 @@
 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
 - the resultant file is machine generated, cgen-ibld.in isn't
 
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and GDB, the GNU debugger.
 
@@ -203,6 +203,7 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
   if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
     {
       unsigned long maxval = mask;
+      
       if ((unsigned long) value > maxval)
        {
          /* xgettext:c-format */
@@ -214,15 +215,19 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
     }
   else
     {
-      long minval = - (1L << (length - 1));
-      long maxval = (1L << (length - 1)) - 1;
-      if (value < minval || value > maxval)
+      if (! cgen_signed_overflow_ok_p (cd))
        {
-         sprintf
-           /* xgettext:c-format */
-           (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
-            value, minval, maxval);
-         return errbuf;
+         long minval = - (1L << (length - 1));
+         long maxval =   (1L << (length - 1)) - 1;
+         
+         if (value < minval || value > maxval)
+           {
+             sprintf
+               /* xgettext:c-format */
+               (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+                value, minval, maxval);
+             return errbuf;
+           }
        }
     }
 
@@ -584,6 +589,15 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
+      break;
+    case M32R_OPERAND_ACCD :
+      errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
+      break;
+    case M32R_OPERAND_ACCS :
+      errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
+      break;
     case M32R_OPERAND_DCR :
       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
       break;
@@ -616,6 +630,13 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case M32R_OPERAND_HI16 :
       errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
       break;
+    case M32R_OPERAND_IMM1 :
+      {
+        long value = fields->f_imm1;
+        value = ((value) - (1));
+        errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
+      }
+      break;
     case M32R_OPERAND_SCR :
       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
       break;
@@ -694,6 +715,15 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
+      break;
+    case M32R_OPERAND_ACCD :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
+      break;
+    case M32R_OPERAND_ACCS :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
+      break;
     case M32R_OPERAND_DCR :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
       break;
@@ -729,6 +759,14 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case M32R_OPERAND_HI16 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
       break;
+    case M32R_OPERAND_IMM1 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
+        value = ((value) + (1));
+        fields->f_imm1 = value;
+      }
+      break;
     case M32R_OPERAND_SCR :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
       break;
@@ -801,6 +839,15 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      value = fields->f_acc;
+      break;
+    case M32R_OPERAND_ACCD :
+      value = fields->f_accd;
+      break;
+    case M32R_OPERAND_ACCS :
+      value = fields->f_accs;
+      break;
     case M32R_OPERAND_DCR :
       value = fields->f_r1;
       break;
@@ -822,6 +869,9 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
     case M32R_OPERAND_HI16 :
       value = fields->f_hi16;
       break;
+    case M32R_OPERAND_IMM1 :
+      value = fields->f_imm1;
+      break;
     case M32R_OPERAND_SCR :
       value = fields->f_r2;
       break;
@@ -879,6 +929,15 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
 
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      value = fields->f_acc;
+      break;
+    case M32R_OPERAND_ACCD :
+      value = fields->f_accd;
+      break;
+    case M32R_OPERAND_ACCS :
+      value = fields->f_accs;
+      break;
     case M32R_OPERAND_DCR :
       value = fields->f_r1;
       break;
@@ -900,6 +959,9 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
     case M32R_OPERAND_HI16 :
       value = fields->f_hi16;
       break;
+    case M32R_OPERAND_IMM1 :
+      value = fields->f_imm1;
+      break;
     case M32R_OPERAND_SCR :
       value = fields->f_r2;
       break;
@@ -961,6 +1023,15 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
 {
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      fields->f_acc = value;
+      break;
+    case M32R_OPERAND_ACCD :
+      fields->f_accd = value;
+      break;
+    case M32R_OPERAND_ACCS :
+      fields->f_accs = value;
+      break;
     case M32R_OPERAND_DCR :
       fields->f_r1 = value;
       break;
@@ -981,6 +1052,9 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
     case M32R_OPERAND_HI16 :
       fields->f_hi16 = value;
       break;
+    case M32R_OPERAND_IMM1 :
+      fields->f_imm1 = value;
+      break;
     case M32R_OPERAND_SCR :
       fields->f_r2 = value;
       break;
@@ -1035,6 +1109,15 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
 {
   switch (opindex)
     {
+    case M32R_OPERAND_ACC :
+      fields->f_acc = value;
+      break;
+    case M32R_OPERAND_ACCD :
+      fields->f_accd = value;
+      break;
+    case M32R_OPERAND_ACCS :
+      fields->f_accs = value;
+      break;
     case M32R_OPERAND_DCR :
       fields->f_r1 = value;
       break;
@@ -1055,6 +1138,9 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
     case M32R_OPERAND_HI16 :
       fields->f_hi16 = value;
       break;
+    case M32R_OPERAND_IMM1 :
+      fields->f_imm1 = value;
+      break;
     case M32R_OPERAND_SCR :
       fields->f_r2 = value;
       break;