/* Generic opcode table support for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
-This file is used to generate m32r-opc.c.
+THIS FILE IS USED TO GENERATE m32r-opc.c.
Copyright (C) 1998 Free Software Foundation, Inc.
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "bfd.h"
#include "symcat.h"
#include "m32r-opc.h"
+#include "opintl.h"
+
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
/* Look up instruction INSN_VALUE and extract its fields.
- If non-null INSN is the insn table entry.
+ INSN, if non-null, is the insn table entry.
Otherwise INSN_VALUE is examined to compute it.
LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
+ 0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
+ If INSN != NULL, LENGTH must be valid.
+ ALIAS_P is non-zero if alias insns are to be included in the search.
+
The result a pointer to the insn table entry, or NULL if the instruction
wasn't recognized. */
const CGEN_INSN *
-m32r_cgen_lookup_insn (insn, insn_value, length, fields)
+m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
+ CGEN_OPCODE_DESC od;
const CGEN_INSN *insn;
cgen_insn_t insn_value;
int length;
CGEN_FIELDS *fields;
+ int alias_p;
{
- char buf[4];
+ char buf[16];
if (!insn)
{
buf[0] = insn_value;
break;
case 16:
- if (cgen_current_endian == CGEN_ENDIAN_BIG)
+ if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
bfd_putb16 (insn_value, buf);
else
bfd_putl16 (insn_value, buf);
break;
case 32:
- if (cgen_current_endian == CGEN_ENDIAN_BIG)
+ if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
bfd_putb32 (insn_value, buf);
else
bfd_putl32 (insn_value, buf);
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
- insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
+ insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
while (insn_list != NULL)
{
insn = insn_list->insn;
- /* Basic bit mask must be correct. */
- /* ??? May wish to allow target to defer this check until the extract
- handler. */
- if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if (alias_p
+ || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
{
- length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
- if (length > 0)
- return insn;
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the
+ extract handler. */
+ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ {
+ /* ??? 0 is passed for `pc' */
+ int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL,
+ insn_value, fields,
+ (bfd_vma) 0);
+ if (elength > 0)
+ {
+ /* sanity check */
+ if (length != 0 && length != elength)
+ abort ();
+ return insn;
+ }
+ }
}
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
}
else
{
- length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
- if (length > 0)
- return insn;
+ /* Sanity check: can't pass an alias insn if ! alias_p. */
+ if (! alias_p
+ && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
+ abort ();
+ /* Sanity check: length must be correct. */
+ if (length != CGEN_INSN_BITSIZE (insn))
+ abort ();
+
+ /* ??? 0 is passed for `pc' */
+ length = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL, insn_value, fields,
+ (bfd_vma) 0);
+ /* Sanity check: must succeed.
+ Could relax this later if it ever proves useful. */
+ if (length == 0)
+ abort ();
+ return insn;
}
return NULL;
}
-/* Fill in the operand instances used by insn INSN_VALUE.
- If non-null INS is the insn table entry.
- Otherwise INSN_VALUE is examined to compute it.
- LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
- INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
- The result a pointer to the insn table entry, or NULL if the instruction
- wasn't recognized. */
+/* Fill in the operand instances used by INSN whose operands are FIELDS.
+ INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
+ in. */
-const CGEN_INSN *
-m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
- const CGEN_INSN *insn;
- cgen_insn_t insn_value;
- int length;
+void
+m32r_cgen_get_insn_operands (od, insn, fields, indices)
+ CGEN_OPCODE_DESC od;
+ const CGEN_INSN * insn;
+ const CGEN_FIELDS * fields;
int *indices;
{
- CGEN_FIELDS fields;
const CGEN_OPERAND_INSTANCE *opinst;
int i;
- insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields);
- if (! insn)
- return NULL;
-
for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
- CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
+ opinst != NULL
+ && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
++i, ++opinst)
{
const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
if (op == NULL)
indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
else
- indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
+ indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
+ fields);
}
+}
+
+/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
+ isn't known.
+ The INSN, INSN_VALUE, and LENGTH arguments are passed to
+ m32r_cgen_lookup_insn unchanged.
+
+ The result is the insn table entry or NULL if the instruction wasn't
+ recognized. */
+
+const CGEN_INSN *
+m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
+ CGEN_OPCODE_DESC od;
+ const CGEN_INSN *insn;
+ cgen_insn_t insn_value;
+ int length;
+ int *indices;
+{
+ CGEN_FIELDS fields;
+
+ /* Pass non-zero for ALIAS_P only if INSN != NULL.
+ If INSN == NULL, we want a real insn. */
+ insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
+ insn != NULL);
+ if (! insn)
+ return NULL;
+ m32r_cgen_get_insn_operands (od, insn, &fields, indices);
return insn;
}
/* Attributes. */
{ 0, 0 }
};
-static const CGEN_ATTR_ENTRY WRITE_LR_attr[] =
-{
- { "NO", WRITE_LR_NO },
- { "YES", WRITE_LR_YES },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY WRITE_SRC_attr[] =
-{
- { "NO", WRITE_SRC_NO },
- { "YES", WRITE_SRC_YES },
- { 0, 0 }
-};
-
/* start-sanitize-m32rx */
static const CGEN_ATTR_ENTRY PIPE_attr[] =
{
{
{ "ABS-ADDR", NULL },
{ "FAKE", NULL },
+ { "HASH-PREFIX", NULL },
{ "NEGATIVE", NULL },
- { "PC", NULL },
{ "PCREL-ADDR", NULL },
{ "RELAX", NULL },
{ "RELOC", NULL },
/* start-sanitize-m32rx */
{ "PIPE", & PIPE_attr[0] },
/* end-sanitize-m32rx */
- { "WRITE_LR", & WRITE_LR_attr[0] },
- { "WRITE_SRC", & WRITE_SRC_attr[0] },
{ "ALIAS", NULL },
{ "COND-CTI", NULL },
{ "FILL-SLOT", NULL },
+ { "NO-DIS", NULL },
{ "PARALLEL", NULL },
{ "RELAX", NULL },
{ "RELAXABLE", NULL },
+ { "SPECIAL", NULL },
{ "UNCOND-CTI", NULL },
{ 0, 0 }
};
{ "cr3", 3 },
{ "cr4", 4 },
{ "cr5", 5 },
- { "cr6", 6 }
+ { "cr6", 6 },
+ { "cr7", 7 },
+ { "cr8", 8 },
+ { "cr9", 9 },
+ { "cr10", 10 },
+ { "cr11", 11 },
+ { "cr12", 12 },
+ { "cr13", 13 },
+ { "cr14", 14 },
+ { "cr15", 15 }
};
CGEN_KEYWORD m32r_cgen_opval_h_cr =
{
& m32r_cgen_opval_h_cr_entries[0],
- 12
+ 21
};
/* start-sanitize-m32rx */
{ HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
/* start-sanitize-m32rx */
{ HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
/* end-sanitize-m32rx */
{ HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
{ HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
{ HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
{ HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
{ HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
+ { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
{ 0 }
};
/* The operand table. */
-#define OP_ENT(op) m32r_cgen_operand_table[CONCAT2 (M32R_OPERAND_,op)]
+#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
+#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
+
const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
{
/* pc: program counter */
{ "pc", & HW_ENT (HW_H_PC), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
/* sr: source register */
{ "sr", & HW_ENT (HW_H_GR), 12, 4,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* simm8: 8 bit signed immediate */
{ "simm8", & HW_ENT (HW_H_SINT), 8, 8,
- { 0, 0, { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
/* simm16: 16 bit signed immediate */
{ "simm16", & HW_ENT (HW_H_SINT), 16, 16,
- { 0, 0, { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
/* uimm4: 4 bit trap number */
{ "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* uimm5: 5 bit shift count */
{ "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* start-sanitize-m32rx */
/* imm1: 1 bit immediate */
{ "imm1", & HW_ENT (HW_H_UINT), 15, 1,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* accd: accumulator destination register */
{ "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* end-sanitize-m32rx */
+/* hash: # prefix */
+ { "hash", & HW_ENT (HW_H_SINT), 0, 0,
+ { 0, 0, { 0 } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", & HW_ENT (HW_H_HI16), 16, 16,
{ 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* uimm24: 24 bit address */
{ "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
- { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* disp8: 8 bit displacement */
{ "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
{ 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
/* accum: accumulator */
{ "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* start-sanitize-m32rx */
-/* abort-parallel-execution: abort parallel execution */
- { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* end-sanitize-m32rx */
};
/* Operand references. */
-static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+#define INPUT CGEN_OPERAND_INSTANCE_INPUT
+#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
+
+static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_5_addv3_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_6_addx_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_7_bc8_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_9_bc24_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_11_beq_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
+ { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_12_beqz_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
+ { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_13_bl8_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_14_bl24_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_15_bcl8_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_16_bcl24_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
+ { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_17_bra8_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_18_bra24_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_19_cmp_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_20_cmpi_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_21_cmpui_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_22_cmpz_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
+ { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_23_div_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_24_jc_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_25_jl_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_26_jmp_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_27_ld_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_29_ld_d_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_31_ldb_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_32_ldb_d_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_33_ldh_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_34_ldh_d_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
+ { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_35_ld24_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_36_ldi8_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
+ { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_37_ldi16_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_38_machi_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_39_machi_a_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_40_mulhi_a_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_41_mv_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_42_mvfachi_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_43_mvfachi_a_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_44_mvfc_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
+ { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_45_mvtachi_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_46_mvtachi_a_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_47_mvtc_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_49_rac_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_50_rac_d_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_51_rac_ds_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
+ { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_52_rac_dsi_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
+ { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_53_rte_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
+static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_54_seth_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_55_slli_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_57_st_d_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_59_trap_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_62_satb_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_63_sat_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_64_sadd_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
+static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_65_macwu1_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_66_sc_ops[] = {
- { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
- { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, & OP_ENT (ABORT_PARALLEL_EXECUTION), 0 },
+static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
+ { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
+ { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
+ { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
{ 0 }
};
-#define OP 1 /* syntax value for mnemonic */
+static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
+ { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
+ { 0 }
+};
-static const CGEN_SYNTAX syntax_table[] =
-{
-/* <op> $dr,$sr */
-/* 0 */ { OP, ' ', 130, ',', 129, 0 },
-/* <op> $dr,$sr,#$slo16 */
-/* 1 */ { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
-/* <op> $dr,$sr,$slo16 */
-/* 2 */ { OP, ' ', 130, ',', 129, ',', 145, 0 },
-/* <op> $dr,$sr,#$uimm16 */
-/* 3 */ { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
-/* <op> $dr,$sr,$uimm16 */
-/* 4 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
-/* <op> $dr,$sr,#$ulo16 */
-/* 5 */ { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
-/* <op> $dr,$sr,$ulo16 */
-/* 6 */ { OP, ' ', 130, ',', 129, ',', 146, 0 },
-/* <op> $dr,#$simm8 */
-/* 7 */ { OP, ' ', 130, ',', '#', 135, 0 },
-/* <op> $dr,$simm8 */
-/* 8 */ { OP, ' ', 130, ',', 135, 0 },
-/* <op> $dr,$sr,#$simm16 */
-/* 9 */ { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
-/* <op> $dr,$sr,$simm16 */
-/* 10 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
-/* <op> $disp8 */
-/* 11 */ { OP, ' ', 148, 0 },
-/* <op> $disp24 */
-/* 12 */ { OP, ' ', 150, 0 },
-/* <op> $src1,$src2,$disp16 */
-/* 13 */ { OP, ' ', 131, ',', 132, ',', 149, 0 },
-/* <op> $src2,$disp16 */
-/* 14 */ { OP, ' ', 132, ',', 149, 0 },
-/* <op> $src1,$src2 */
-/* 15 */ { OP, ' ', 131, ',', 132, 0 },
-/* <op> $src2,#$simm16 */
-/* 16 */ { OP, ' ', 132, ',', '#', 136, 0 },
-/* <op> $src2,$simm16 */
-/* 17 */ { OP, ' ', 132, ',', 136, 0 },
-/* <op> $src2,#$uimm16 */
-/* 18 */ { OP, ' ', 132, ',', '#', 139, 0 },
-/* <op> $src2,$uimm16 */
-/* 19 */ { OP, ' ', 132, ',', 139, 0 },
-/* <op> $src2 */
-/* 20 */ { OP, ' ', 132, 0 },
-/* <op> $sr */
-/* 21 */ { OP, ' ', 129, 0 },
-/* <op> $dr,@$sr */
-/* 22 */ { OP, ' ', 130, ',', '@', 129, 0 },
-/* <op> $dr,@($sr) */
-/* 23 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
-/* <op> $dr,@($slo16,$sr) */
-/* 24 */ { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
-/* <op> $dr,@($sr,$slo16) */
-/* 25 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
-/* <op> $dr,@$sr+ */
-/* 26 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
-/* <op> $dr,#$uimm24 */
-/* 27 */ { OP, ' ', 130, ',', '#', 147, 0 },
-/* <op> $dr,$uimm24 */
-/* 28 */ { OP, ' ', 130, ',', 147, 0 },
-/* <op> $dr,$slo16 */
-/* 29 */ { OP, ' ', 130, ',', 145, 0 },
-/* <op> $src1,$src2,$acc */
-/* 30 */ { OP, ' ', 131, ',', 132, ',', 143, 0 },
-/* <op> $dr */
-/* 31 */ { OP, ' ', 130, 0 },
-/* <op> $dr,$accs */
-/* 32 */ { OP, ' ', 130, ',', 142, 0 },
-/* <op> $dr,$scr */
-/* 33 */ { OP, ' ', 130, ',', 133, 0 },
-/* <op> $src1 */
-/* 34 */ { OP, ' ', 131, 0 },
-/* <op> $src1,$accs */
-/* 35 */ { OP, ' ', 131, ',', 142, 0 },
-/* <op> $sr,$dcr */
-/* 36 */ { OP, ' ', 129, ',', 134, 0 },
-/* <op> */
-/* 37 */ { OP, 0 },
-/* <op> $accd */
-/* 38 */ { OP, ' ', 141, 0 },
-/* <op> $accd,$accs */
-/* 39 */ { OP, ' ', 141, ',', 142, 0 },
-/* <op> $accd,$accs,#$imm1 */
-/* 40 */ { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
-/* <op> $dr,#$hi16 */
-/* 41 */ { OP, ' ', 130, ',', '#', 144, 0 },
-/* <op> $dr,$hi16 */
-/* 42 */ { OP, ' ', 130, ',', 144, 0 },
-/* <op> $dr,#$uimm5 */
-/* 43 */ { OP, ' ', 130, ',', '#', 138, 0 },
-/* <op> $dr,$uimm5 */
-/* 44 */ { OP, ' ', 130, ',', 138, 0 },
-/* <op> $src1,@$src2 */
-/* 45 */ { OP, ' ', 131, ',', '@', 132, 0 },
-/* <op> $src1,@($src2) */
-/* 46 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
-/* <op> $src1,@($slo16,$src2) */
-/* 47 */ { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
-/* <op> $src1,@($src2,$slo16) */
-/* 48 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
-/* <op> $src1,@+$src2 */
-/* 49 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
-/* <op> $src1,@-$src2 */
-/* 50 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
-/* <op> #$uimm4 */
-/* 51 */ { OP, ' ', '#', 137, 0 },
-/* <op> $uimm4 */
-/* 52 */ { OP, ' ', 137, 0 },
-/* <op> $dr,$src2 */
-/* 53 */ { OP, ' ', 130, ',', 132, 0 },
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
};
-#undef OP
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
-static const CGEN_FORMAT format_table[] =
-{
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.dr.SI.sr.SI. */
-/* 0 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.slo16.HI.sr.SI. */
-/* 1 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16.sr.SI.uimm16.USI. */
-/* 2 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16.sr.SI.ulo16.UHI. */
-/* 3 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-simm8.simm8.dr.SI.simm8.SI. */
-/* 4 */ { 16, 16, 0xf000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16.simm16.SI.sr.SI. */
-/* 5 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.condbit.UBI.dr.SI.sr.SI. */
-/* 6 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.number.f-disp8.disp8.condbit.UBI.disp8.VM. */
-/* 7 */ { 16, 16, 0xff00 },
-/* f-op1.number.f-r1.number.f-disp8.disp8. */
-/* 8 */ { 16, 16, 0xff00 },
-/* f-op1.number.f-r1.number.f-disp24.disp24.condbit.UBI.disp24.VM. */
-/* 9 */ { 32, 32, 0xff000000 },
-/* f-op1.number.f-r1.number.f-disp24.disp24. */
-/* 10 */ { 32, 32, 0xff000000 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16.disp16.VM.src1.SI.src2.SI. */
-/* 11 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16.disp16.VM.src2.SI. */
-/* 12 */ { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.number.f-disp8.disp8.disp8.VM.pc.USI. */
-/* 13 */ { 16, 16, 0xff00 },
-/* f-op1.number.f-r1.number.f-disp24.disp24.disp24.VM.pc.USI. */
-/* 14 */ { 32, 32, 0xff000000 },
-/* f-op1.number.f-r1.number.f-disp8.disp8.condbit.UBI.disp8.VM.pc.USI. */
-/* 15 */ { 16, 16, 0xff00 },
-/* f-op1.number.f-r1.number.f-disp24.disp24.condbit.UBI.disp24.VM.pc.USI. */
-/* 16 */ { 32, 32, 0xff000000 },
-/* f-op1.number.f-r1.number.f-disp8.disp8.disp8.VM. */
-/* 17 */ { 16, 16, 0xff00 },
-/* f-op1.number.f-r1.number.f-disp24.disp24.disp24.VM. */
-/* 18 */ { 32, 32, 0xff000000 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.src1.SI.src2.SI. */
-/* 19 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16.simm16.SI.src2.SI. */
-/* 20 */ { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16.src2.SI.uimm16.USI. */
-/* 21 */ { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.src2.SI. */
-/* 22 */ { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number.dr.SI.sr.SI. */
-/* 23 */ { 32, 32, 0xf0f0ffff },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.condbit.UBI.sr.SI. */
-/* 24 */ { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.pc.USI.sr.SI. */
-/* 25 */ { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.sr.SI. */
-/* 26 */ { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.SI.sr.SI. */
-/* 27 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
-/* 28 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.SI.slo16.HI.sr.SI. */
-/* 29 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
-/* 30 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.QI.sr.SI. */
-/* 31 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.QI.slo16.HI.sr.SI. */
-/* 32 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.HI.sr.SI. */
-/* 33 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.HI.slo16.HI.sr.SI. */
-/* 34 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-uimm24.uimm24.uimm24.VM. */
-/* 35 */ { 32, 32, 0xf0000000 },
-/* f-op1.number.f-r1.dr.f-simm8.simm8.simm8.SI. */
-/* 36 */ { 16, 16, 0xf000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16.slo16.HI. */
-/* 37 */ { 32, 32, 0xf0ff0000 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.accum.DI.src1.SI.src2.SI. */
-/* 38 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2.acc.DI.src1.SI.src2.SI. */
-/* 39 */ { 16, 16, 0xf070 },
-/* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2.src1.SI.src2.SI. */
-/* 40 */ { 16, 16, 0xf070 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.sr.SI. */
-/* 41 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.accum.DI. */
-/* 42 */ { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-accs.accs.f-op3.number.accs.DI. */
-/* 43 */ { 16, 16, 0xf0f3 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr.scr.SI. */
-/* 44 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.number.accum.DI.src1.SI. */
-/* 45 */ { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.src1.f-op2.number.f-accs.accs.f-op3.number.accs.DI.src1.SI. */
-/* 46 */ { 16, 16, 0xf0f3 },
-/* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr.sr.SI. */
-/* 47 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
-/* 48 */ { 16, 16, 0xffff },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.number.accum.DI. */
-/* 49 */ { 16, 16, 0xffff },
-/* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.number.f-bit14.number.f-imm1.number.accum.DI. */
-/* 50 */ { 16, 16, 0xf3ff },
-/* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.accs.f-bit14.number.f-imm1.number.accs.DI. */
-/* 51 */ { 16, 16, 0xf3f3 },
-/* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.accs.f-bit14.number.f-imm1.imm1.accs.DI.imm1.USI. */
-/* 52 */ { 16, 16, 0xf3f2 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.number.h-bcond-0.VM.h-bie-0.VM.h-bpc-0.VM.h-bsm-0.VM. */
-/* 53 */ { 16, 16, 0xffff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16.hi16.UHI. */
-/* 54 */ { 32, 32, 0xf0ff0000 },
-/* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5.dr.SI.uimm5.USI. */
-/* 55 */ { 16, 16, 0xf0e0 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
-/* 56 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16.slo16.HI.src1.SI.src2.SI. */
-/* 57 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
-/* 58 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4.uimm4.USI. */
-/* 59 */ { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
-/* 60 */ { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
-/* 61 */ { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number.src2.SI. */
-/* 62 */ { 32, 32, 0xf0f0ffff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number.condbit.UBI.src2.SI. */
-/* 63 */ { 32, 32, 0xf0f0ffff },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.number.h-accums-0.DI.h-accums-1.DI. */
-/* 64 */ { 16, 16, 0xffff },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.h-accums-1.DI.src1.SI.src2.SI. */
-/* 65 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.number.condbit.UBI. */
-/* 66 */ { 16, 16, 0xffff },
-};
-
-#define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
-#define SYN(n) (& syntax_table[n])
-#define FMT(n) (& format_table[n])
-
-/* The instruction table. */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
+ { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
+ { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+#undef INPUT
+#undef OUTPUT
+
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.
+ This is currently non-static because the simulator accesses it
+ directly. */
const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
{
- /* null first entry, end of all hash chains */
+ /* Special null first entry.
+ A `num' value of zero is thus illegal.
+ Also, the special `illegal' insn resides here. */
{ { 0 }, 0 },
/* add $dr,$sr */
{
{ 1, 1, 1, 1 },
- "add", "add", SYN (0), FMT (0), 0xa0,
- & fmt_0_add_ops[0],
- { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ADD, "add", "add",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xa0,
+ "(set dr (add dr sr))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
-/* add3 $dr,$sr,#$slo16 */
+/* add3 $dr,$sr,$hash$slo16 */
{
{ 1, 1, 1, 1 },
- "add3", "add3", SYN (1), FMT (1), 0x80a00000,
- & fmt_1_add3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* add3 $dr,$sr,$slo16 */
- {
- { 1, 1, 1, 1 },
- "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
- & fmt_1_add3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ADD3, "add3", "add3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80a00000,
+ "(set dr (add sr slo16))",
+ (PTR) & fmt_add3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* and $dr,$sr */
{
{ 1, 1, 1, 1 },
- "and", "and", SYN (0), FMT (0), 0xc0,
- & fmt_0_add_ops[0],
- { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* and3 $dr,$sr,#$uimm16 */
- {
- { 1, 1, 1, 1 },
- "and3", "and3", SYN (3), FMT (2), 0x80c00000,
- & fmt_2_and3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_AND, "and", "and",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xc0,
+ "(set dr (and dr sr))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
/* and3 $dr,$sr,$uimm16 */
{
{ 1, 1, 1, 1 },
- "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
- & fmt_2_and3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_AND3, "and3", "and3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80c00000,
+ "(set dr (and sr uimm16))",
+ (PTR) & fmt_and3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* or $dr,$sr */
{
{ 1, 1, 1, 1 },
- "or", "or", SYN (0), FMT (0), 0xe0,
- & fmt_0_add_ops[0],
- { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* or3 $dr,$sr,#$ulo16 */
- {
- { 1, 1, 1, 1 },
- "or3", "or3", SYN (5), FMT (3), 0x80e00000,
- & fmt_3_or3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_OR, "or", "or",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xe0,
+ "(set dr (or dr sr))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
-/* or3 $dr,$sr,$ulo16 */
+/* or3 $dr,$sr,$hash$ulo16 */
{
{ 1, 1, 1, 1 },
- "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
- & fmt_3_or3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_OR3, "or3", "or3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80e00000,
+ "(set dr (or sr ulo16))",
+ (PTR) & fmt_or3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* xor $dr,$sr */
{
{ 1, 1, 1, 1 },
- "xor", "xor", SYN (0), FMT (0), 0xd0,
- & fmt_0_add_ops[0],
- { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* xor3 $dr,$sr,#$uimm16 */
- {
- { 1, 1, 1, 1 },
- "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
- & fmt_2_and3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_XOR, "xor", "xor",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xd0,
+ "(set dr (xor dr sr))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
/* xor3 $dr,$sr,$uimm16 */
{
{ 1, 1, 1, 1 },
- "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
- & fmt_2_and3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* addi $dr,#$simm8 */
- {
- { 1, 1, 1, 1 },
- "addi", "addi", SYN (7), FMT (4), 0x4000,
- & fmt_4_addi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_XOR3, "xor3", "xor3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80d00000,
+ "(set dr (xor sr uimm16))",
+ (PTR) & fmt_and3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* addi $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "addi.a", "addi", SYN (8), FMT (4), 0x4000,
- & fmt_4_addi_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ADDI, "addi", "addi",
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ { 16, 16, 0xf000 }, 0x4000,
+ "(set dr (add dr simm8))",
+ (PTR) & fmt_addi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* addv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "addv", "addv", SYN (0), FMT (0), 0x80,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* addv3 $dr,$sr,#$simm16 */
- {
- { 1, 1, 1, 1 },
- "addv3", "addv3", SYN (9), FMT (5), 0x80800000,
- & fmt_5_addv3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ADDV, "addv", "addv",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x80,
+ "(parallel () (set dr (add dr sr)) (set condbit (add-oflag dr sr (const 0))))",
+ (PTR) & fmt_addv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* addv3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "addv3.a", "addv3", SYN (10), FMT (5), 0x80800000,
- & fmt_5_addv3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ADDV3, "addv3", "addv3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80800000,
+ "(parallel () (set dr (add sr simm16)) (set condbit (add-oflag sr simm16 (const 0))))",
+ (PTR) & fmt_addv3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* addx $dr,$sr */
{
{ 1, 1, 1, 1 },
- "addx", "addx", SYN (0), FMT (6), 0x90,
- & fmt_6_addx_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* bc $disp8 */
- {
- { 1, 1, 1, 1 },
- "bc8", "bc", SYN (11), FMT (7), 0x7c00,
- & fmt_7_bc8_ops[0],
- { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ADDX, "addx", "addx",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x90,
+ "(parallel () (set dr (addc dr sr condbit)) (set condbit (add-cflag dr sr condbit)))",
+ (PTR) & fmt_addx_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* bc.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bc8.s", "bc.s", SYN (11), FMT (8), 0x7c00,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* bc $disp24 */
- {
- { 1, 1, 1, 1 },
- "bc24", "bc", SYN (12), FMT (9), 0xfc000000,
- & fmt_9_bc24_ops[0],
- { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BC8, "bc8", "bc.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7c00,
+ "(if condbit (set pc disp8))",
+ (PTR) & fmt_bc8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bc.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bc24.l", "bc.l", SYN (12), FMT (10), 0xfc000000,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BC24, "bc24", "bc.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfc000000,
+ "(if condbit (set pc disp24))",
+ (PTR) & fmt_bc24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* beq $src1,$src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "beq", "beq", SYN (13), FMT (11), 0xb0000000,
- & fmt_11_beq_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BEQ, "beq", "beq",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0xb0000000,
+ "(if (eq src1 src2) (set pc disp16))",
+ (PTR) & fmt_beq_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* beqz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "beqz", "beqz", SYN (14), FMT (12), 0xb0800000,
- & fmt_12_beqz_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BEQZ, "beqz", "beqz",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0800000,
+ "(if (eq src2 (const: WI 0)) (set pc disp16))",
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bgez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bgez", "bgez", SYN (14), FMT (12), 0xb0b00000,
- & fmt_12_beqz_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BGEZ, "bgez", "bgez",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0b00000,
+ "(if (ge src2 (const: WI 0)) (set pc disp16))",
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bgtz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bgtz", "bgtz", SYN (14), FMT (12), 0xb0d00000,
- & fmt_12_beqz_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BGTZ, "bgtz", "bgtz",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0d00000,
+ "(if (gt src2 (const: WI 0)) (set pc disp16))",
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* blez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "blez", "blez", SYN (14), FMT (12), 0xb0c00000,
- & fmt_12_beqz_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BLEZ, "blez", "blez",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0c00000,
+ "(if (le src2 (const: WI 0)) (set pc disp16))",
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bltz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bltz", "bltz", SYN (14), FMT (12), 0xb0a00000,
- & fmt_12_beqz_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BLTZ, "bltz", "bltz",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0a00000,
+ "(if (lt src2 (const: WI 0)) (set pc disp16))",
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bnez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bnez", "bnez", SYN (14), FMT (12), 0xb0900000,
- & fmt_12_beqz_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* bl $disp8 */
- {
- { 1, 1, 1, 1 },
- "bl8", "bl", SYN (11), FMT (13), 0x7e00,
- & fmt_13_bl8_ops[0],
- { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BNEZ, "bnez", "bnez",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0900000,
+ "(if (ne src2 (const: WI 0)) (set pc disp16))",
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bl8.s", "bl.s", SYN (11), FMT (8), 0x7e00,
- 0,
- { 4, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
- },
-/* bl $disp24 */
- {
- { 1, 1, 1, 1 },
- "bl24", "bl", SYN (12), FMT (14), 0xfe000000,
- & fmt_14_bl24_ops[0],
- { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BL8, "bl8", "bl.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7e00,
+ "(sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8))",
+ (PTR) & fmt_bl8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bl24.l", "bl.l", SYN (12), FMT (10), 0xfe000000,
- 0,
- { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
- },
-/* start-sanitize-m32rx */
-/* bcl $disp8 */
- {
- { 1, 1, 1, 1 },
- "bcl8", "bcl", SYN (11), FMT (15), 0x7800,
- & fmt_15_bcl8_ops[0],
- { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BL24, "bl24", "bl.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfe000000,
+ "(sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24))",
+ (PTR) & fmt_bl24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* bcl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bcl8.s", "bcl.s", SYN (11), FMT (8), 0x7800,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
- },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* bcl $disp24 */
- {
- { 1, 1, 1, 1 },
- "bcl24", "bcl", SYN (12), FMT (16), 0xf8000000,
- & fmt_16_bcl24_ops[0],
- { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BCL8, "bcl8", "bcl.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7800,
+ "(if condbit (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
+ (PTR) & fmt_bcl8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* bcl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bcl24.l", "bcl.l", SYN (12), FMT (10), 0xf8000000,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BCL24, "bcl24", "bcl.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf8000000,
+ "(if condbit (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
+ (PTR) & fmt_bcl24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
/* end-sanitize-m32rx */
-/* bnc $disp8 */
- {
- { 1, 1, 1, 1 },
- "bnc8", "bnc", SYN (11), FMT (7), 0x7d00,
- & fmt_7_bc8_ops[0],
- { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
- },
/* bnc.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bnc8.s", "bnc.s", SYN (11), FMT (8), 0x7d00,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* bnc $disp24 */
- {
- { 1, 1, 1, 1 },
- "bnc24", "bnc", SYN (12), FMT (9), 0xfd000000,
- & fmt_9_bc24_ops[0],
- { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BNC8, "bnc8", "bnc.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7d00,
+ "(if (not condbit) (set pc disp8))",
+ (PTR) & fmt_bc8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bnc.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bnc24.l", "bnc.l", SYN (12), FMT (10), 0xfd000000,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BNC24, "bnc24", "bnc.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfd000000,
+ "(if (not condbit) (set pc disp24))",
+ (PTR) & fmt_bc24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bne $src1,$src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bne", "bne", SYN (13), FMT (11), 0xb0100000,
- & fmt_11_beq_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* bra $disp8 */
- {
- { 1, 1, 1, 1 },
- "bra8", "bra", SYN (11), FMT (17), 0x7f00,
- & fmt_17_bra8_ops[0],
- { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BNE, "bne", "bne",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0xb0100000,
+ "(if (ne src1 src2) (set pc disp16))",
+ (PTR) & fmt_beq_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bra.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bra8.s", "bra.s", SYN (11), FMT (8), 0x7f00,
- 0,
- { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* bra $disp24 */
- {
- { 1, 1, 1, 1 },
- "bra24", "bra", SYN (12), FMT (18), 0xff000000,
- & fmt_18_bra24_ops[0],
- { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_BRA8, "bra8", "bra.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7f00,
+ "(set pc disp8)",
+ (PTR) & fmt_bra8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bra.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bra24.l", "bra.l", SYN (12), FMT (10), 0xff000000,
- 0,
- { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* start-sanitize-m32rx */
-/* bncl $disp8 */
- {
- { 1, 1, 1, 1 },
- "bncl8", "bncl", SYN (11), FMT (15), 0x7900,
- & fmt_15_bcl8_ops[0],
- { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BRA24, "bra24", "bra.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xff000000,
+ "(set pc disp24)",
+ (PTR) & fmt_bra24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* bncl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bncl8.s", "bncl.s", SYN (11), FMT (8), 0x7900,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
- },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* bncl $disp24 */
- {
- { 1, 1, 1, 1 },
- "bncl24", "bncl", SYN (12), FMT (16), 0xf9000000,
- & fmt_16_bcl24_ops[0],
- { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BNCL8, "bncl8", "bncl.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7900,
+ "(if (not condbit) (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
+ (PTR) & fmt_bcl8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* bncl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bncl24.l", "bncl.l", SYN (12), FMT (10), 0xf9000000,
- 0,
- { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_BNCL24, "bncl24", "bncl.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf9000000,
+ "(if (not condbit) (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
+ (PTR) & fmt_bcl24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
/* end-sanitize-m32rx */
/* cmp $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmp", "cmp", SYN (15), FMT (19), 0x40,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* cmpi $src2,#$simm16 */
- {
- { 1, 1, 1, 1 },
- "cmpi", "cmpi", SYN (16), FMT (20), 0x80400000,
- & fmt_20_cmpi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_CMP, "cmp", "cmp",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x40,
+ "(set condbit (lt src1 src2))",
+ (PTR) & fmt_cmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* cmpi $src2,$simm16 */
{
{ 1, 1, 1, 1 },
- "cmpi.a", "cmpi", SYN (17), FMT (20), 0x80400000,
- & fmt_20_cmpi_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_CMPI, "cmpi", "cmpi",
+ { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xfff00000 }, 0x80400000,
+ "(set condbit (lt src2 simm16))",
+ (PTR) & fmt_cmpi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* cmpu $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmpu", "cmpu", SYN (15), FMT (19), 0x50,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
- },
-/* cmpui $src2,#$uimm16 */
- {
- { 1, 1, 1, 1 },
- "cmpui", "cmpui", SYN (18), FMT (21), 0x80500000,
- & fmt_21_cmpui_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_CMPU, "cmpu", "cmpu",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50,
+ "(set condbit (ltu src1 src2))",
+ (PTR) & fmt_cmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* cmpui $src2,$uimm16 */
+/* cmpui $src2,$simm16 */
{
{ 1, 1, 1, 1 },
- "cmpui.a", "cmpui", SYN (19), FMT (21), 0x80500000,
- & fmt_21_cmpui_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_CMPUI, "cmpui", "cmpui",
+ { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xfff00000 }, 0x80500000,
+ "(set condbit (ltu src2 simm16))",
+ (PTR) & fmt_cmpi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* start-sanitize-m32rx */
/* cmpeq $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmpeq", "cmpeq", SYN (15), FMT (19), 0x60,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x60,
+ "(set condbit (eq src1 src2))",
+ (PTR) & fmt_cmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* cmpz $src2 */
{
{ 1, 1, 1, 1 },
- "cmpz", "cmpz", SYN (20), FMT (22), 0x70,
- & fmt_22_cmpz_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_CMPZ, "cmpz", "cmpz",
+ { { MNEM, ' ', OP (SRC2), 0 } },
+ { 16, 16, 0xfff0 }, 0x70,
+ "(set condbit (eq src2 (const 0)))",
+ (PTR) & fmt_cmpz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
/* end-sanitize-m32rx */
/* div $dr,$sr */
{
{ 1, 1, 1, 1 },
- "div", "div", SYN (0), FMT (23), 0x90000000,
- & fmt_23_div_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_DIV, "div", "div",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90000000,
+ "(if (ne sr (const 0)) (set dr (div dr sr)))",
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* divu $dr,$sr */
{
{ 1, 1, 1, 1 },
- "divu", "divu", SYN (0), FMT (23), 0x90100000,
- & fmt_23_div_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_DIVU, "divu", "divu",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90100000,
+ "(if (ne sr (const 0)) (set dr (udiv dr sr)))",
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* rem $dr,$sr */
{
{ 1, 1, 1, 1 },
- "rem", "rem", SYN (0), FMT (23), 0x90200000,
- & fmt_23_div_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_REM, "rem", "rem",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90200000,
+ "(if (ne sr (const 0)) (set dr (mod dr sr)))",
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* remu $dr,$sr */
{
{ 1, 1, 1, 1 },
- "remu", "remu", SYN (0), FMT (23), 0x90300000,
- & fmt_23_div_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_REMU, "remu", "remu",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90300000,
+ "(if (ne sr (const 0)) (set dr (umod dr sr)))",
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* start-sanitize-m32rx */
/* divh $dr,$sr */
{
{ 1, 1, 1, 1 },
- "divh", "divh", SYN (0), FMT (23), 0x90000010,
- & fmt_23_div_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_DIVH, "divh", "divh",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90000010,
+ "(if (ne sr (const 0)) (set dr (div (ext: WI (trunc: HI dr)) sr)))",
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* jc $sr */
{
{ 1, 1, 1, 1 },
- "jc", "jc", SYN (21), FMT (24), 0x1cc0,
- & fmt_24_jc_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_JC, "jc", "jc",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1cc0,
+ "(if condbit (set pc (and sr (const -4))))",
+ (PTR) & fmt_jc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* jnc $sr */
{
{ 1, 1, 1, 1 },
- "jnc", "jnc", SYN (21), FMT (24), 0x1dc0,
- & fmt_24_jc_ops[0],
- { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_JNC, "jnc", "jnc",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1dc0,
+ "(if (not condbit) (set pc (and sr (const -4))))",
+ (PTR) & fmt_jc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* end-sanitize-m32rx */
/* jl $sr */
{
{ 1, 1, 1, 1 },
- "jl", "jl", SYN (21), FMT (25), 0x1ec0,
- & fmt_25_jl_ops[0],
- { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
+ M32R_INSN_JL, "jl", "jl",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1ec0,
+ "(parallel () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc (and sr (const -4))))",
+ (PTR) & fmt_jl_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* jmp $sr */
{
{ 1, 1, 1, 1 },
- "jmp", "jmp", SYN (21), FMT (26), 0x1fc0,
- & fmt_26_jmp_ops[0],
- { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_JMP, "jmp", "jmp",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1fc0,
+ "(set pc (and sr (const -4)))",
+ (PTR) & fmt_jmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* ld $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ld", "ld", SYN (22), FMT (27), 0x20c0,
- & fmt_27_ld_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LD, "ld", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20c0,
+ "(set dr (mem: WI sr))",
+ (PTR) & fmt_ld_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ld $dr,@($sr) */
+/* ld $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ld-2", "ld", SYN (23), FMT (28), 0x20c0,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LD_D, "ld-d", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0c00000,
+ "(set dr (mem: WI (add sr slo16)))",
+ (PTR) & fmt_ld_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ld $dr,@($slo16,$sr) */
+/* ldb $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ld-d", "ld", SYN (24), FMT (29), 0xa0c00000,
- & fmt_29_ld_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDB, "ldb", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2080,
+ "(set dr (ext: WI (mem: QI sr)))",
+ (PTR) & fmt_ldb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ld $dr,@($sr,$slo16) */
+/* ldb $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ld-d2", "ld", SYN (25), FMT (30), 0xa0c00000,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDB_D, "ldb-d", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0800000,
+ "(set dr (ext: WI (mem: QI (add sr slo16))))",
+ (PTR) & fmt_ldb_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ldb $dr,@$sr */
+/* ldh $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldb", "ldb", SYN (22), FMT (31), 0x2080,
- & fmt_31_ldb_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDH, "ldh", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20a0,
+ "(set dr (ext: WI (mem: HI sr)))",
+ (PTR) & fmt_ldh_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ldb $dr,@($sr) */
+/* ldh $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldb-2", "ldb", SYN (23), FMT (28), 0x2080,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDH_D, "ldh-d", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0a00000,
+ "(set dr (ext: WI (mem: HI (add sr slo16))))",
+ (PTR) & fmt_ldh_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ldb $dr,@($slo16,$sr) */
+/* ldub $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldb-d", "ldb", SYN (24), FMT (32), 0xa0800000,
- & fmt_32_ldb_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDUB, "ldub", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2090,
+ "(set dr (zext: WI (mem: QI sr)))",
+ (PTR) & fmt_ldb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ldb $dr,@($sr,$slo16) */
+/* ldub $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldb-d2", "ldb", SYN (25), FMT (30), 0xa0800000,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDUB_D, "ldub-d", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0900000,
+ "(set dr (zext: WI (mem: QI (add sr slo16))))",
+ (PTR) & fmt_ldb_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ldh $dr,@$sr */
+/* lduh $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldh", "ldh", SYN (22), FMT (33), 0x20a0,
- & fmt_33_ldh_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDUH, "lduh", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20b0,
+ "(set dr (zext: WI (mem: HI sr)))",
+ (PTR) & fmt_ldh_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ldh $dr,@($sr) */
+/* lduh $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldh-2", "ldh", SYN (23), FMT (28), 0x20a0,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDUH_D, "lduh-d", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0b00000,
+ "(set dr (zext: WI (mem: HI (add sr slo16))))",
+ (PTR) & fmt_ldh_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ldh $dr,@($slo16,$sr) */
+/* ld $dr,@$sr+ */
{
{ 1, 1, 1, 1 },
- "ldh-d", "ldh", SYN (24), FMT (34), 0xa0a00000,
- & fmt_34_ldh_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LD_PLUS, "ld-plus", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20e0,
+ "(parallel () (set dr (mem: WI sr)) (set sr (add sr (const 4))))",
+ (PTR) & fmt_ld_plus_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ldh $dr,@($sr,$slo16) */
+/* ld24 $dr,$uimm24 */
{
{ 1, 1, 1, 1 },
- "ldh-d2", "ldh", SYN (25), FMT (30), 0xa0a00000,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LD24, "ld24", "ld24",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
+ { 32, 32, 0xf0000000 }, 0xe0000000,
+ "(set dr uimm24)",
+ (PTR) & fmt_ld24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ldub $dr,@$sr */
+/* ldi8 $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "ldub", "ldub", SYN (22), FMT (31), 0x2090,
- & fmt_31_ldb_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDI8, "ldi8", "ldi8",
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ { 16, 16, 0xf000 }, 0x6000,
+ "(set dr simm8)",
+ (PTR) & fmt_ldi8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* ldub $dr,@($sr) */
+/* ldi16 $dr,$hash$slo16 */
{
{ 1, 1, 1, 1 },
- "ldub-2", "ldub", SYN (23), FMT (28), 0x2090,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LDI16, "ldi16", "ldi16",
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
+ { 32, 32, 0xf0ff0000 }, 0x90f00000,
+ "(set dr slo16)",
+ (PTR) & fmt_ldi16_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* ldub $dr,@($slo16,$sr) */
+/* lock $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldub-d", "ldub", SYN (24), FMT (32), 0xa0900000,
- & fmt_32_ldb_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_LOCK, "lock", "lock",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20d0,
+ "(sequence () (set (reg h-lock) (const: UBI 1)) (set dr (mem: WI sr)))",
+ (PTR) & fmt_lock_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* ldub $dr,@($sr,$slo16) */
+/* machi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ldub-d2", "ldub", SYN (25), FMT (30), 0xa0900000,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACHI, "machi", "machi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3040,
+ "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* lduh $dr,@$sr */
+/* start-sanitize-m32rx */
+/* machi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "lduh", "lduh", SYN (22), FMT (33), 0x20b0,
- & fmt_33_ldh_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACHI_A, "machi-a", "machi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3040,
+ "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* lduh $dr,@($sr) */
+/* end-sanitize-m32rx */
+/* maclo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "lduh-2", "lduh", SYN (23), FMT (28), 0x20b0,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACLO, "maclo", "maclo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3050,
+ "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* lduh $dr,@($slo16,$sr) */
+/* start-sanitize-m32rx */
+/* maclo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "lduh-d", "lduh", SYN (24), FMT (34), 0xa0b00000,
- & fmt_34_ldh_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACLO_A, "maclo-a", "maclo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3050,
+ "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* lduh $dr,@($sr,$slo16) */
+/* end-sanitize-m32rx */
+/* macwhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "lduh-d2", "lduh", SYN (25), FMT (30), 0xa0b00000,
- 0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACWHI, "macwhi", "macwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3060,
+ "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ld $dr,@$sr+ */
+/* start-sanitize-m32rx */
+/* macwhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ld-plus", "ld", SYN (26), FMT (27), 0x20e0,
- & fmt_27_ld_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
+ M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3060,
+ "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16)))))))",
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
-/* ld24 $dr,#$uimm24 */
+/* end-sanitize-m32rx */
+/* macwlo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ld24", "ld24", SYN (27), FMT (35), 0xe0000000,
- & fmt_35_ld24_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACWLO, "macwlo", "macwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3070,
+ "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ld24 $dr,$uimm24 */
+/* start-sanitize-m32rx */
+/* macwlo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ld24.a", "ld24", SYN (28), FMT (35), 0xe0000000,
- & fmt_35_ld24_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3070,
+ "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI src2)))))",
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
-/* ldi $dr,#$simm8 */
+/* end-sanitize-m32rx */
+/* mul $dr,$sr */
{
{ 1, 1, 1, 1 },
- "ldi8", "ldi", SYN (7), FMT (36), 0x6000,
- & fmt_36_ldi8_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MUL, "mul", "mul",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1060,
+ "(set dr (mul dr sr))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ldi $dr,$simm8 */
+/* mulhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ldi8.a", "ldi", SYN (8), FMT (36), 0x6000,
- & fmt_36_ldi8_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULHI, "mulhi", "mulhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3000,
+ "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ldi8 $dr,#$simm8 */
+/* start-sanitize-m32rx */
+/* mulhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ldi8a", "ldi8", SYN (7), FMT (36), 0x6000,
- & fmt_36_ldi8_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3000,
+ "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* ldi8 $dr,$simm8 */
+/* end-sanitize-m32rx */
+/* mullo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ldi8a.a", "ldi8", SYN (8), FMT (36), 0x6000,
- & fmt_36_ldi8_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULLO, "mullo", "mullo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3010,
+ "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ldi $dr,$slo16 */
+/* start-sanitize-m32rx */
+/* mullo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ldi16", "ldi", SYN (29), FMT (37), 0x90f00000,
- & fmt_37_ldi16_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULLO_A, "mullo-a", "mullo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3010,
+ "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* ldi16 $dr,$slo16 */
+/* end-sanitize-m32rx */
+/* mulwhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ldi16a", "ldi16", SYN (29), FMT (37), 0x90f00000,
- & fmt_37_ldi16_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULWHI, "mulwhi", "mulwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3020,
+ "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 8)) (const 8)))",
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* lock $dr,@$sr */
+/* start-sanitize-m32rx */
+/* mulwhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "lock", "lock", SYN (22), FMT (0), 0x20d0,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3020,
+ "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16))))))",
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
-/* machi $src1,$src2 */
+/* end-sanitize-m32rx */
+/* mulwlo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "machi", "machi", SYN (15), FMT (38), 0x3040,
- & fmt_38_machi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULWLO, "mulwlo", "mulwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3030,
+ "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2))) (const 8)) (const 8)))",
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* start-sanitize-m32rx */
-/* machi $src1,$src2,$acc */
+/* mulwlo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "machi-a", "machi", SYN (30), FMT (39), 0x3040,
- & fmt_39_machi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3030,
+ "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI src2))))",
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
/* end-sanitize-m32rx */
-/* maclo $src1,$src2 */
+/* mv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "maclo", "maclo", SYN (15), FMT (38), 0x3050,
- & fmt_38_machi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MV, "mv", "mv",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1080,
+ "(set dr sr)",
+ (PTR) & fmt_mv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
+ },
+/* mvfachi $dr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x50f0,
+ "(set dr (trunc: WI (sra: DI accum (const 32))))",
+ (PTR) & fmt_mvfachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* start-sanitize-m32rx */
-/* maclo $src1,$src2,$acc */
+/* mvfachi $dr,$accs */
{
{ 1, 1, 1, 1 },
- "maclo-a", "maclo", SYN (30), FMT (39), 0x3050,
- & fmt_39_machi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
+ { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x50f0,
+ "(set dr (trunc: WI (sra: DI accs (const 32))))",
+ (PTR) & fmt_mvfachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* end-sanitize-m32rx */
-/* macwhi $src1,$src2 */
+/* mvfaclo $dr */
{
{ 1, 1, 1, 1 },
- "macwhi", "macwhi", SYN (15), FMT (38), 0x3060,
- & fmt_38_machi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x50f1,
+ "(set dr (trunc: WI accum))",
+ (PTR) & fmt_mvfachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* macwlo $src1,$src2 */
+/* start-sanitize-m32rx */
+/* mvfaclo $dr,$accs */
{
{ 1, 1, 1, 1 },
- "macwlo", "macwlo", SYN (15), FMT (38), 0x3070,
- & fmt_38_machi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
+ { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x50f1,
+ "(set dr (trunc: WI accs))",
+ (PTR) & fmt_mvfachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* mul $dr,$sr */
+/* end-sanitize-m32rx */
+/* mvfacmi $dr */
{
{ 1, 1, 1, 1 },
- "mul", "mul", SYN (0), FMT (0), 0x1060,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x50f2,
+ "(set dr (trunc: WI (sra: DI accum (const 16))))",
+ (PTR) & fmt_mvfachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* mulhi $src1,$src2 */
+/* start-sanitize-m32rx */
+/* mvfacmi $dr,$accs */
{
{ 1, 1, 1, 1 },
- "mulhi", "mulhi", SYN (15), FMT (19), 0x3000,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
+ { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x50f2,
+ "(set dr (trunc: WI (sra: DI accs (const 16))))",
+ (PTR) & fmt_mvfachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* mvfc $dr,$scr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVFC, "mvfc", "mvfc",
+ { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1090,
+ "(set dr scr)",
+ (PTR) & fmt_mvfc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
+ },
+/* mvtachi $src1 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ { 16, 16, 0xf0ff }, 0x5070,
+ "(set accum (or: DI (and: DI accum (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
+ (PTR) & fmt_mvtachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* start-sanitize-m32rx */
-/* mulhi $src1,$src2,$acc */
+/* mvtachi $src1,$accs */
{
{ 1, 1, 1, 1 },
- "mulhi-a", "mulhi", SYN (30), FMT (40), 0x3000,
- & fmt_40_mulhi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x5070,
+ "(set accs (or: DI (and: DI accs (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
+ (PTR) & fmt_mvtachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* end-sanitize-m32rx */
-/* mullo $src1,$src2 */
+/* mvtaclo $src1 */
{
{ 1, 1, 1, 1 },
- "mullo", "mullo", SYN (15), FMT (19), 0x3010,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ { 16, 16, 0xf0ff }, 0x5071,
+ "(set accum (or: DI (and: DI accum (const: DI 18446744069414584320)) (zext: DI src1)))",
+ (PTR) & fmt_mvtachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* start-sanitize-m32rx */
-/* mullo $src1,$src2,$acc */
+/* mvtaclo $src1,$accs */
{
{ 1, 1, 1, 1 },
- "mullo-a", "mullo", SYN (30), FMT (40), 0x3010,
- & fmt_40_mulhi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x5071,
+ "(set accs (or: DI (and: DI accs (const: DI 18446744069414584320)) (zext: DI src1)))",
+ (PTR) & fmt_mvtachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* end-sanitize-m32rx */
-/* mulwhi $src1,$src2 */
+/* mvtc $sr,$dcr */
{
{ 1, 1, 1, 1 },
- "mulwhi", "mulwhi", SYN (15), FMT (19), 0x3020,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MVTC, "mvtc", "mvtc",
+ { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x10a0,
+ "(set dcr sr)",
+ (PTR) & fmt_mvtc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* mulwlo $src1,$src2 */
+/* neg $dr,$sr */
{
{ 1, 1, 1, 1 },
- "mulwlo", "mulwlo", SYN (15), FMT (19), 0x3030,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_NEG, "neg", "neg",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x30,
+ "(set dr (neg sr))",
+ (PTR) & fmt_mv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* mv $dr,$sr */
+/* nop */
{
{ 1, 1, 1, 1 },
- "mv", "mv", SYN (0), FMT (41), 0x1080,
- & fmt_41_mv_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_NOP, "nop", "nop",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x7000,
+ "(c-code: VM PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+)",
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* mvfachi $dr */
+/* not $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_NOT, "not", "not",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xb0,
+ "(set dr (inv sr))",
+ (PTR) & fmt_mv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
+ },
+/* rac */
{
{ 1, 1, 1, 1 },
- "mvfachi", "mvfachi", SYN (31), FMT (42), 0x50f0,
- & fmt_42_mvfachi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_RAC, "rac", "rac",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x5090,
+ "(sequence ((DI tmp1)) (set tmp1 (sll: DI accum (const 1))) (set tmp1 (add: DI tmp1 (const: DI 32768))) (set accum (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
+ (PTR) & fmt_rac_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* start-sanitize-m32rx */
-/* mvfachi $dr,$accs */
+/* rac $accd,$accs,$imm1 */
{
{ 1, 1, 1, 1 },
- "mvfachi-a", "mvfachi", SYN (32), FMT (43), 0x50f0,
- & fmt_43_mvfachi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_RAC_DSI, "rac-dsi", "rac",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
+ { 16, 16, 0xf3f2 }, 0x5090,
+ "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 32768))) (set accd (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
+ (PTR) & fmt_rac_dsi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* end-sanitize-m32rx */
-/* mvfaclo $dr */
+/* rach */
{
{ 1, 1, 1, 1 },
- "mvfaclo", "mvfaclo", SYN (31), FMT (42), 0x50f1,
- & fmt_42_mvfachi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_RACH, "rach", "rach",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x5080,
+ "(sequence ((DI tmp1)) (set tmp1 (and accum (const: DI 72057594037927935))) (if (andif: WI (ge tmp1 (const: DI 70366596694016)) (le tmp1 (const: DI 36028797018963967))) (set tmp1 (const: DI 70366596694016)) (if (andif: WI (ge tmp1 (const: DI 36028797018963968)) (le tmp1 (const: DI 71987225293750272))) (set tmp1 (const: DI 71987225293750272)) (set tmp1 (and (add accum (const: DI 1073741824)) (const: DI 18446744071562067968))))) (set tmp1 (sll tmp1 (const 1))) (set accum (sra: DI (sll: DI tmp1 (const 7)) (const 7))))",
+ (PTR) & fmt_rac_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* start-sanitize-m32rx */
-/* mvfaclo $dr,$accs */
+/* rach $accd,$accs,$imm1 */
{
{ 1, 1, 1, 1 },
- "mvfaclo-a", "mvfaclo", SYN (32), FMT (43), 0x50f1,
- & fmt_43_mvfachi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_RACH_DSI, "rach-dsi", "rach",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
+ { 16, 16, 0xf3f2 }, 0x5080,
+ "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 2147483648))) (set accd (cond: DI ((gt tmp1 (const: DI 140733193388032)) (const: DI 140733193388032)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744069414584320))))))",
+ (PTR) & fmt_rac_dsi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* end-sanitize-m32rx */
-/* mvfacmi $dr */
+/* rte */
{
{ 1, 1, 1, 1 },
- "mvfacmi", "mvfacmi", SYN (31), FMT (42), 0x50f2,
- & fmt_42_mvfachi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_RTE, "rte", "rte",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x10d6,
+ "(sequence () (set (reg h-sm) (reg h-bsm)) (set (reg h-ie) (reg h-bie)) (set condbit (reg h-bcond)) (set pc (and (reg h-bpc) (const -4))))",
+ (PTR) & fmt_rte_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
-/* start-sanitize-m32rx */
-/* mvfacmi $dr,$accs */
+/* seth $dr,$hash$hi16 */
{
{ 1, 1, 1, 1 },
- "mvfacmi-a", "mvfacmi", SYN (32), FMT (43), 0x50f2,
- & fmt_43_mvfachi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SETH, "seth", "seth",
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
+ { 32, 32, 0xf0ff0000 }, 0xd0c00000,
+ "(set dr (sll: WI hi16 (const 16)))",
+ (PTR) & fmt_seth_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* mvfc $dr,$scr */
+/* sll $dr,$sr */
{
{ 1, 1, 1, 1 },
- "mvfc", "mvfc", SYN (33), FMT (44), 0x1090,
- & fmt_44_mvfc_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SLL, "sll", "sll",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1040,
+ "(set dr (sll dr (and sr (const 31))))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* mvtachi $src1 */
+/* sll3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "mvtachi", "mvtachi", SYN (34), FMT (45), 0x5070,
- & fmt_45_mvtachi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SLL3, "sll3", "sll3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x90c00000,
+ "(set dr (sll sr (and: WI simm16 (const 31))))",
+ (PTR) & fmt_sll3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* start-sanitize-m32rx */
-/* mvtachi $src1,$accs */
+/* slli $dr,$uimm5 */
{
{ 1, 1, 1, 1 },
- "mvtachi-a", "mvtachi", SYN (35), FMT (46), 0x5070,
- & fmt_46_mvtachi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SLLI, "slli", "slli",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
+ { 16, 16, 0xf0e0 }, 0x5040,
+ "(set dr (sll dr uimm5))",
+ (PTR) & fmt_slli_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* mvtaclo $src1 */
+/* sra $dr,$sr */
{
{ 1, 1, 1, 1 },
- "mvtaclo", "mvtaclo", SYN (34), FMT (45), 0x5071,
- & fmt_45_mvtachi_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SRA, "sra", "sra",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1020,
+ "(set dr (sra dr (and sr (const 31))))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* start-sanitize-m32rx */
-/* mvtaclo $src1,$accs */
+/* sra3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "mvtaclo-a", "mvtaclo", SYN (35), FMT (46), 0x5071,
- & fmt_46_mvtachi_a_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SRA3, "sra3", "sra3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x90a00000,
+ "(set dr (sra sr (and: WI simm16 (const 31))))",
+ (PTR) & fmt_sll3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* mvtc $sr,$dcr */
+/* srai $dr,$uimm5 */
{
{ 1, 1, 1, 1 },
- "mvtc", "mvtc", SYN (36), FMT (47), 0x10a0,
- & fmt_47_mvtc_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SRAI, "srai", "srai",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
+ { 16, 16, 0xf0e0 }, 0x5020,
+ "(set dr (sra dr uimm5))",
+ (PTR) & fmt_slli_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* neg $dr,$sr */
+/* srl $dr,$sr */
{
{ 1, 1, 1, 1 },
- "neg", "neg", SYN (0), FMT (41), 0x30,
- & fmt_41_mv_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SRL, "srl", "srl",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1000,
+ "(set dr (srl dr (and sr (const 31))))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* nop */
+/* srl3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "nop", "nop", SYN (37), FMT (48), 0x7000,
- 0,
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SRL3, "srl3", "srl3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x90800000,
+ "(set dr (srl sr (and: WI simm16 (const 31))))",
+ (PTR) & fmt_sll3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* not $dr,$sr */
+/* srli $dr,$uimm5 */
{
{ 1, 1, 1, 1 },
- "not", "not", SYN (0), FMT (41), 0xb0,
- & fmt_41_mv_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SRLI, "srli", "srli",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
+ { 16, 16, 0xf0e0 }, 0x5000,
+ "(set dr (srl dr uimm5))",
+ (PTR) & fmt_slli_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* rac */
+/* st $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "rac", "rac", SYN (37), FMT (49), 0x5090,
- & fmt_49_rac_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ST, "st", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2040,
+ "(set: WI (mem: WI src2) src1)",
+ (PTR) & fmt_st_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* start-sanitize-m32rx */
-/* rac $accd */
+/* st $src1,@($slo16,$src2) */
{
{ 1, 1, 1, 1 },
- "rac-d", "rac", SYN (38), FMT (50), 0x5090,
- & fmt_50_rac_d_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ST_D, "st-d", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0400000,
+ "(set: WI (mem: WI (add src2 slo16)) src1)",
+ (PTR) & fmt_st_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* rac $accd,$accs */
+/* stb $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "rac-ds", "rac", SYN (39), FMT (51), 0x5090,
- & fmt_51_rac_ds_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_STB, "stb", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2000,
+ "(set: QI (mem: QI src2) src1)",
+ (PTR) & fmt_stb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* rac $accd,$accs,#$imm1 */
+/* stb $src1,@($slo16,$src2) */
{
{ 1, 1, 1, 1 },
- "rac-dsi", "rac", SYN (40), FMT (52), 0x5090,
- & fmt_52_rac_dsi_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_STB_D, "stb-d", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0000000,
+ "(set: QI (mem: QI (add src2 slo16)) src1)",
+ (PTR) & fmt_stb_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* rach */
+/* sth $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "rach", "rach", SYN (37), FMT (49), 0x5080,
- & fmt_49_rac_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_STH, "sth", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2020,
+ "(set: HI (mem: HI src2) src1)",
+ (PTR) & fmt_sth_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* start-sanitize-m32rx */
-/* rach $accd */
+/* sth $src1,@($slo16,$src2) */
{
{ 1, 1, 1, 1 },
- "rach-d", "rach", SYN (38), FMT (50), 0x5080,
- & fmt_50_rac_d_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_STH_D, "sth-d", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0200000,
+ "(set: HI (mem: HI (add src2 slo16)) src1)",
+ (PTR) & fmt_sth_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* rach $accd,$accs */
+/* st $src1,@+$src2 */
{
{ 1, 1, 1, 1 },
- "rach-ds", "rach", SYN (39), FMT (51), 0x5080,
- & fmt_51_rac_ds_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ST_PLUS, "st-plus", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2060,
+ "(sequence ((WI new-src2)) (set new-src2 (add: WI src2 (const: WI 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
+ (PTR) & fmt_st_plus_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* rach $accd,$accs,#$imm1 */
+/* st $src1,@-$src2 */
{
{ 1, 1, 1, 1 },
- "rach-dsi", "rach", SYN (40), FMT (52), 0x5080,
- & fmt_52_rac_dsi_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_ST_MINUS, "st-minus", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2070,
+ "(sequence ((WI new-src2)) (set new-src2 (sub src2 (const 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
+ (PTR) & fmt_st_plus_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* rte */
+/* sub $dr,$sr */
{
{ 1, 1, 1, 1 },
- "rte", "rte", SYN (37), FMT (53), 0x10d6,
- & fmt_53_rte_ops[0],
- { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SUB, "sub", "sub",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20,
+ "(set dr (sub dr sr))",
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* seth $dr,#$hi16 */
+/* subv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "seth", "seth", SYN (41), FMT (54), 0xd0c00000,
- & fmt_54_seth_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SUBV, "subv", "subv",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x0,
+ "(parallel () (set dr (sub dr sr)) (set condbit (sub-oflag dr sr (const 0))))",
+ (PTR) & fmt_addv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* seth $dr,$hi16 */
+/* subx $dr,$sr */
{
{ 1, 1, 1, 1 },
- "seth.a", "seth", SYN (42), FMT (54), 0xd0c00000,
- & fmt_54_seth_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SUBX, "subx", "subx",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x10,
+ "(parallel () (set dr (subc dr sr condbit)) (set condbit (sub-cflag dr sr condbit)))",
+ (PTR) & fmt_addx_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
-/* sll $dr,$sr */
+/* trap $uimm4 */
{
{ 1, 1, 1, 1 },
- "sll", "sll", SYN (0), FMT (0), 0x1040,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_TRAP, "trap", "trap",
+ { { MNEM, ' ', OP (UIMM4), 0 } },
+ { 16, 16, 0xfff0 }, 0x10f0,
+ "(sequence () (set (reg h-cr 6) (add pc (const 4))) (set (reg h-cr 0) (and (sll (reg h-cr 0) (const 8)) (const 65408))) (set: WI pc (c-call: WI m32r_trap uimm4)))",
+ (PTR) & fmt_trap_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
-/* sll3 $dr,$sr,#$simm16 */
+/* unlock $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "sll3", "sll3", SYN (9), FMT (5), 0x90c00000,
- & fmt_5_addv3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_UNLOCK, "unlock", "unlock",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2050,
+ "(sequence () (if (reg h-lock) (set (mem: WI src2) src1)) (set (reg h-lock) (const: UBI 0)))",
+ (PTR) & fmt_unlock_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
-/* sll3 $dr,$sr,$simm16 */
+/* start-sanitize-m32rx */
+/* satb $dr,$sr */
{
{ 1, 1, 1, 1 },
- "sll3.a", "sll3", SYN (10), FMT (5), 0x90c00000,
- & fmt_5_addv3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SATB, "satb", "satb",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x80600300,
+ "(set dr (cond: WI ((ge sr (const 127)) (const 127)) ((le sr (const -128)) (const -128)) (else sr)))",
+ (PTR) & fmt_satb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* slli $dr,#$uimm5 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sath $dr,$sr */
{
{ 1, 1, 1, 1 },
- "slli", "slli", SYN (43), FMT (55), 0x5040,
- & fmt_55_slli_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SATH, "sath", "sath",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x80600200,
+ "(set dr (cond: WI ((ge sr (const 32767)) (const 32767)) ((le sr (const -32768)) (const -32768)) (else sr)))",
+ (PTR) & fmt_satb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* slli $dr,$uimm5 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sat $dr,$sr */
{
{ 1, 1, 1, 1 },
- "slli.a", "slli", SYN (44), FMT (55), 0x5040,
- & fmt_55_slli_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SAT, "sat", "sat",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x80600000,
+ "(set dr (if: WI condbit (if: WI (lt sr (const 0)) (const 2147483647) (const 2147483648)) sr))",
+ (PTR) & fmt_sat_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* sra $dr,$sr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* pcmpbz $src2 */
{
{ 1, 1, 1, 1 },
- "sra", "sra", SYN (0), FMT (0), 0x1020,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
+ { { MNEM, ' ', OP (SRC2), 0 } },
+ { 16, 16, 0xfff0 }, 0x370,
+ "(set condbit (cond: BI ((eq (and src2 (const 255)) (const 0)) (const: BI 1)) ((eq (and src2 (const 65280)) (const 0)) (const: BI 1)) ((eq (and src2 (const 16711680)) (const 0)) (const: BI 1)) ((eq (and src2 (const 4278190080)) (const 0)) (const: BI 1)) (else (const: BI 0))))",
+ (PTR) & fmt_cmpz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
-/* sra3 $dr,$sr,#$simm16 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sadd */
{
{ 1, 1, 1, 1 },
- "sra3", "sra3", SYN (9), FMT (5), 0x90a00000,
- & fmt_5_addv3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SADD, "sadd", "sadd",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x50e4,
+ "(set (reg h-accums 0) (add (sra (reg h-accums 1) (const 16)) (reg h-accums 0)))",
+ (PTR) & fmt_sadd_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* sra3 $dr,$sr,$simm16 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* macwu1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "sra3.a", "sra3", SYN (10), FMT (5), 0x90a00000,
- & fmt_5_addv3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACWU1, "macwu1", "macwu1",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50b0,
+ "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535))))) (const 8)) (const 8)))",
+ (PTR) & fmt_macwu1_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* srai $dr,#$uimm5 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* msblo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "srai", "srai", SYN (43), FMT (55), 0x5020,
- & fmt_55_slli_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MSBLO, "msblo", "msblo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50d0,
+ "(set accum (sra: DI (sll: DI (sub accum (sra: DI (sll: DI (mul: DI (ext: DI (trunc: HI src1)) (ext: DI (trunc: HI src2))) (const 32)) (const 16))) (const 8)) (const 8)))",
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* srai $dr,$uimm5 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* mulwu1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "srai.a", "srai", SYN (44), FMT (55), 0x5020,
- & fmt_55_slli_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MULWU1, "mulwu1", "mulwu1",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50a0,
+ "(set (reg h-accums 1) (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535)))) (const 16)) (const 16)))",
+ (PTR) & fmt_mulwu1_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* srl $dr,$sr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* maclh1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "srl", "srl", SYN (0), FMT (0), 0x1000,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_MACLH1, "maclh1", "maclh1",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50c0,
+ "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (sll: DI (ext: DI (mul: SI (ext: SI (trunc: HI src1)) (sra: SI src2 (const: SI 16)))) (const 16))) (const 8)) (const 8)))",
+ (PTR) & fmt_macwu1_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* srl3 $dr,$sr,#$simm16 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sc */
{
{ 1, 1, 1, 1 },
- "srl3", "srl3", SYN (9), FMT (5), 0x90800000,
- & fmt_5_addv3_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SC, "sc", "sc",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x7401,
+ "(if condbit (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
+))",
+ (PTR) & fmt_sc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
},
-/* srl3 $dr,$sr,$simm16 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* snc */
{
{ 1, 1, 1, 1 },
- "srl3.a", "srl3", SYN (10), FMT (5), 0x90800000,
- & fmt_5_addv3_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ M32R_INSN_SNC, "snc", "snc",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x7501,
+ "(if (not condbit) (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
+))",
+ (PTR) & fmt_sc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
},
-/* srli $dr,#$uimm5 */
+/* end-sanitize-m32rx */
+};
+
+#undef A
+#undef MNEM
+#undef OP
+
+static const CGEN_INSN_TABLE insn_table =
+{
+ & m32r_cgen_insn_table_entries[0],
+ sizeof (CGEN_INSN),
+ MAX_INSNS,
+ NULL
+};
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_INSN macro_insn_table_entries[] =
+{
+/* bc $disp8 */
{
{ 1, 1, 1, 1 },
- "srli", "srli", SYN (43), FMT (55), 0x5000,
- & fmt_55_slli_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bc8r", "bc",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7c00,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* srli $dr,$uimm5 */
+/* bc $disp24 */
{
{ 1, 1, 1, 1 },
- "srli.a", "srli", SYN (44), FMT (55), 0x5000,
- & fmt_55_slli_ops[0],
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bc24r", "bc",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfc000000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* st $src1,@$src2 */
+/* bl $disp8 */
{
{ 1, 1, 1, 1 },
- "st", "st", SYN (45), FMT (19), 0x2040,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bl8r", "bl",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7e00,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* st $src1,@($src2) */
+/* bl $disp24 */
{
{ 1, 1, 1, 1 },
- "st-2", "st", SYN (46), FMT (56), 0x2040,
+ -1, "bl24r", "bl",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfe000000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* st $src1,@($slo16,$src2) */
+/* bcl $disp8 */
{
{ 1, 1, 1, 1 },
- "st-d", "st", SYN (47), FMT (57), 0xa0400000,
- & fmt_57_st_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bcl8r", "bcl",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7800,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
},
-/* st $src1,@($src2,$slo16) */
+/* bcl $disp24 */
{
{ 1, 1, 1, 1 },
- "st-d2", "st", SYN (48), FMT (58), 0xa0400000,
+ -1, "bcl24r", "bcl",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf8000000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* stb $src1,@$src2 */
+/* bnc $disp8 */
{
{ 1, 1, 1, 1 },
- "stb", "stb", SYN (45), FMT (19), 0x2000,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bnc8r", "bnc",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7d00,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* stb $src1,@($src2) */
+/* bnc $disp24 */
{
{ 1, 1, 1, 1 },
- "stb-2", "stb", SYN (46), FMT (56), 0x2000,
+ -1, "bnc24r", "bnc",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfd000000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* stb $src1,@($slo16,$src2) */
+/* bra $disp8 */
{
{ 1, 1, 1, 1 },
- "stb-d", "stb", SYN (47), FMT (57), 0xa0000000,
- & fmt_57_st_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bra8r", "bra",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7f00,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* stb $src1,@($src2,$slo16) */
+/* bra $disp24 */
{
{ 1, 1, 1, 1 },
- "stb-d2", "stb", SYN (48), FMT (58), 0xa0000000,
+ -1, "bra24r", "bra",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xff000000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* sth $src1,@$src2 */
+/* bncl $disp8 */
{
{ 1, 1, 1, 1 },
- "sth", "sth", SYN (45), FMT (19), 0x2020,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "bncl8r", "bncl",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7900,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
},
-/* sth $src1,@($src2) */
+/* bncl $disp24 */
{
{ 1, 1, 1, 1 },
- "sth-2", "sth", SYN (46), FMT (56), 0x2020,
+ -1, "bncl24r", "bncl",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf9000000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* sth $src1,@($slo16,$src2) */
+/* ld $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "sth-d", "sth", SYN (47), FMT (57), 0xa0200000,
- & fmt_57_st_d_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "ld-2", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20c0,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* sth $src1,@($src2,$slo16) */
+/* ld $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "sth-d2", "sth", SYN (48), FMT (58), 0xa0200000,
+ -1, "ld-d2", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0c00000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* st $src1,@+$src2 */
+/* ldb $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "st-plus", "st", SYN (49), FMT (19), 0x2060,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
+ -1, "ldb-2", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2080,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* st $src1,@-$src2 */
+/* ldb $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "st-minus", "st", SYN (50), FMT (19), 0x2070,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
+ -1, "ldb-d2", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0800000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* sub $dr,$sr */
+/* ldh $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "sub", "sub", SYN (0), FMT (0), 0x20,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "ldh-2", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20a0,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* subv $dr,$sr */
+/* ldh $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "subv", "subv", SYN (0), FMT (0), 0x0,
- & fmt_0_add_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "ldh-d2", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0a00000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* subx $dr,$sr */
+/* ldub $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "subx", "subx", SYN (0), FMT (6), 0x10,
- & fmt_6_addx_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "ldub-2", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2090,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* trap #$uimm4 */
+/* ldub $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "trap", "trap", SYN (51), FMT (59), 0x10f0,
- & fmt_59_trap_ops[0],
- { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "ldub-d2", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0900000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* trap $uimm4 */
+/* lduh $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "trap.a", "trap", SYN (52), FMT (59), 0x10f0,
- & fmt_59_trap_ops[0],
- { 4, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "lduh-2", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20b0,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* unlock $src1,@$src2 */
+/* lduh $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "unlock", "unlock", SYN (45), FMT (19), 0x2050,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "lduh-d2", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0b00000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* push $src1 */
+/* pop $dr */
{
{ 1, 1, 1, 1 },
- "push", "push", SYN (34), FMT (60), 0x207f,
+ -1, "pop", "pop",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x20ef,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* pop $dr */
+/* ldi $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "pop", "pop", SYN (31), FMT (61), 0x20ef,
+ -1, "ldi8a", "ldi",
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ { 16, 16, 0xf000 }, 0x6000,
0,
- { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
},
-/* start-sanitize-m32rx */
-/* satb $dr,$src2 */
+/* ldi $dr,$hash$slo16 */
{
{ 1, 1, 1, 1 },
- "satb", "satb", SYN (53), FMT (62), 0x80000100,
- & fmt_62_satb_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "ldi16a", "ldi",
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
+ { 32, 32, 0xf0ff0000 }, 0x90f00000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* sath $dr,$src2 */
+/* rac $accd */
{
{ 1, 1, 1, 1 },
- "sath", "sath", SYN (53), FMT (62), 0x80000200,
- & fmt_62_satb_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "rac-d", "rac",
+ { { MNEM, ' ', OP (ACCD), 0 } },
+ { 16, 16, 0xf3ff }, 0x5090,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* sat $dr,$src2 */
+/* rac $accd,$accs */
{
{ 1, 1, 1, 1 },
- "sat", "sat", SYN (53), FMT (63), 0x80000000,
- & fmt_63_sat_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "rac-ds", "rac",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf3f3 }, 0x5090,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* pcmpbz $src2 */
+/* rach $accd */
{
{ 1, 1, 1, 1 },
- "pcmpbz", "pcmpbz", SYN (20), FMT (22), 0x370,
- & fmt_22_cmpz_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "rach-d", "rach",
+ { { MNEM, ' ', OP (ACCD), 0 } },
+ { 16, 16, 0xf3ff }, 0x5080,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* sadd */
+/* rach $accd,$accs */
{
{ 1, 1, 1, 1 },
- "sadd", "sadd", SYN (37), FMT (64), 0x50e4,
- & fmt_64_sadd_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "rach-ds", "rach",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf3f3 }, 0x5080,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* macwu1 $src1,$src2 */
+/* st $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "macwu1", "macwu1", SYN (15), FMT (65), 0x50b0,
- & fmt_65_macwu1_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "st-2", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2040,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* msblo $src1,$src2 */
+/* st $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "msblo", "msblo", SYN (15), FMT (38), 0x50d0,
- & fmt_38_machi_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "st-d2", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0400000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* mulwu1 $src1,$src2 */
+/* stb $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "mulwu1", "mulwu1", SYN (15), FMT (19), 0x50a0,
- & fmt_19_cmp_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "stb-2", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* maclh1 $src1,$src2 */
+/* stb $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "maclh1", "maclh1", SYN (15), FMT (65), 0x50c0,
- & fmt_65_macwu1_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "stb-d2", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0000000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* sc */
+/* sth $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "sc", "sc", SYN (37), FMT (66), 0x7401,
- & fmt_66_sc_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "sth-2", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2020,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* snc */
+/* sth $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "snc", "snc", SYN (37), FMT (66), 0x7501,
- & fmt_66_sc_ops[0],
- { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
+ -1, "sth-d2", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0200000,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+ },
+/* push $src1 */
+ {
+ { 1, 1, 1, 1 },
+ -1, "push", "push",
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ { 16, 16, 0xf0ff }, 0x207f,
+ 0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
-/* end-sanitize-m32rx */
};
#undef A
-#undef SYN
-#undef FMT
+#undef MNEM
+#undef OP
-CGEN_INSN_TABLE m32r_cgen_insn_table =
+static const CGEN_INSN_TABLE macro_insn_table =
{
- & m32r_cgen_insn_table_entries[0],
+ & macro_insn_table_entries[0],
sizeof (CGEN_INSN),
- MAX_INSNS,
- NULL,
- m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
- m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
+ (sizeof (macro_insn_table_entries) /
+ sizeof (macro_insn_table_entries[0])),
+ NULL
};
-/* The hash functions are recorded here to help keep assembler code out of
- the disassembler and vice versa. */
+static void
+init_tables ()
+{
+}
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN * insn;
+{
+ return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN * insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
-unsigned int
-m32r_cgen_asm_hash_insn (insn)
- const char * insn;
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
{
- return CGEN_ASM_HASH (insn);
+ return CGEN_ASM_HASH (mnem);
}
-unsigned int
-m32r_cgen_dis_hash_insn (buf, value)
+static unsigned int
+dis_hash_insn (buf, value)
const char * buf;
unsigned long value;
{
return CGEN_DIS_HASH (buf, value);
}
-CGEN_OPCODE_DATA m32r_cgen_opcode_data =
+/* Initialize an opcode table and return a descriptor.
+ It's much like opening a file, and must be the first function called. */
+
+CGEN_OPCODE_DESC
+m32r_cgen_opcode_open (mach, endian)
+ int mach;
+ enum cgen_endian endian;
{
- & m32r_cgen_hw_entries[0],
- & m32r_cgen_insn_table,
-};
+ CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
+ static int init_p;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (table, 0, sizeof (*table));
+
+ CGEN_OPCODE_MACH (table) = mach;
+ CGEN_OPCODE_ENDIAN (table) = endian;
+
+ CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
+
+ CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
+
+ * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
+
+ * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
+
+ CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
+ CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
+ CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
+
+ CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
+ CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
+ CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
+
+ return (CGEN_OPCODE_DESC) table;
+}
+
+/* Close an opcode table. */
void
-m32r_cgen_init_tables (mach)
- int mach;
+m32r_cgen_opcode_close (desc)
+ CGEN_OPCODE_DESC desc;
{
+ free (desc);
}
-/* Main entry point for stuffing values in cgen_fields. */
+/* Getting values from cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they return.
+ TODO: floating point, inlining support, remove cases where result type
+ not appropriate. */
-CGEN_INLINE void
-m32r_cgen_set_operand (opindex, valuep, fields)
+int
+m32r_cgen_get_int_operand (opindex, fields)
int opindex;
- const long * valuep;
- CGEN_FIELDS * fields;
+ const CGEN_FIELDS * fields;
{
+ int value;
+
switch (opindex)
{
case M32R_OPERAND_SR :
- fields->f_r2 = * valuep;
+ value = fields->f_r2;
break;
case M32R_OPERAND_DR :
- fields->f_r1 = * valuep;
+ value = fields->f_r1;
break;
case M32R_OPERAND_SRC1 :
- fields->f_r1 = * valuep;
+ value = fields->f_r1;
break;
case M32R_OPERAND_SRC2 :
- fields->f_r2 = * valuep;
+ value = fields->f_r2;
break;
case M32R_OPERAND_SCR :
- fields->f_r2 = * valuep;
+ value = fields->f_r2;
break;
case M32R_OPERAND_DCR :
- fields->f_r1 = * valuep;
+ value = fields->f_r1;
break;
case M32R_OPERAND_SIMM8 :
- fields->f_simm8 = * valuep;
+ value = fields->f_simm8;
break;
case M32R_OPERAND_SIMM16 :
- fields->f_simm16 = * valuep;
+ value = fields->f_simm16;
break;
case M32R_OPERAND_UIMM4 :
- fields->f_uimm4 = * valuep;
+ value = fields->f_uimm4;
break;
case M32R_OPERAND_UIMM5 :
- fields->f_uimm5 = * valuep;
+ value = fields->f_uimm5;
break;
case M32R_OPERAND_UIMM16 :
- fields->f_uimm16 = * valuep;
+ value = fields->f_uimm16;
break;
/* start-sanitize-m32rx */
case M32R_OPERAND_IMM1 :
- fields->f_imm1 = * valuep;
+ value = fields->f_imm1;
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCD :
- fields->f_accd = * valuep;
+ value = fields->f_accd;
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCS :
- fields->f_accs = * valuep;
+ value = fields->f_accs;
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACC :
- fields->f_acc = * valuep;
+ value = fields->f_acc;
break;
/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ value = fields->f_nil;
+ break;
case M32R_OPERAND_HI16 :
- fields->f_hi16 = * valuep;
+ value = fields->f_hi16;
break;
case M32R_OPERAND_SLO16 :
- fields->f_simm16 = * valuep;
+ value = fields->f_simm16;
break;
case M32R_OPERAND_ULO16 :
- fields->f_uimm16 = * valuep;
+ value = fields->f_uimm16;
break;
case M32R_OPERAND_UIMM24 :
- fields->f_uimm24 = * valuep;
+ value = fields->f_uimm24;
break;
case M32R_OPERAND_DISP8 :
- fields->f_disp8 = * valuep;
+ value = fields->f_disp8;
break;
case M32R_OPERAND_DISP16 :
- fields->f_disp16 = * valuep;
+ value = fields->f_disp16;
break;
case M32R_OPERAND_DISP24 :
- fields->f_disp24 = * valuep;
+ value = fields->f_disp24;
break;
default :
- fprintf (stderr, "Unrecognized field %d while setting operand.\n",
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
opindex);
abort ();
}
-}
-/* Main entry point for getting values from cgen_fields. */
+ return value;
+}
-CGEN_INLINE long
-m32r_cgen_get_operand (opindex, fields)
+bfd_vma
+m32r_cgen_get_vma_operand (opindex, fields)
int opindex;
const CGEN_FIELDS * fields;
{
- long value;
+ bfd_vma value;
switch (opindex)
{
value = fields->f_acc;
break;
/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ value = fields->f_nil;
+ break;
case M32R_OPERAND_HI16 :
value = fields->f_hi16;
break;
break;
default :
- fprintf (stderr, "Unrecognized field %d while getting operand.\n",
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
opindex);
abort ();
}
return value;
}
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they accept.
+ TODO: floating point, inlining support, remove cases where argument type
+ not appropriate. */
+
+void
+m32r_cgen_set_int_operand (opindex, fields, value)
+ int opindex;
+ CGEN_FIELDS * fields;
+ int value;
+{
+ switch (opindex)
+ {
+ case M32R_OPERAND_SR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC1 :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC2 :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_SCR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DCR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SIMM8 :
+ fields->f_simm8 = value;
+ break;
+ case M32R_OPERAND_SIMM16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_UIMM4 :
+ fields->f_uimm4 = value;
+ break;
+ case M32R_OPERAND_UIMM5 :
+ fields->f_uimm5 = value;
+ break;
+ case M32R_OPERAND_UIMM16 :
+ fields->f_uimm16 = value;
+ break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ fields->f_imm1 = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ fields->f_accd = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ fields->f_accs = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ fields->f_acc = value;
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ fields->f_nil = value;
+ break;
+ case M32R_OPERAND_HI16 :
+ fields->f_hi16 = value;
+ break;
+ case M32R_OPERAND_SLO16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_ULO16 :
+ fields->f_uimm16 = value;
+ break;
+ case M32R_OPERAND_UIMM24 :
+ fields->f_uimm24 = value;
+ break;
+ case M32R_OPERAND_DISP8 :
+ fields->f_disp8 = value;
+ break;
+ case M32R_OPERAND_DISP16 :
+ fields->f_disp16 = value;
+ break;
+ case M32R_OPERAND_DISP24 :
+ fields->f_disp24 = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+void
+m32r_cgen_set_vma_operand (opindex, fields, value)
+ int opindex;
+ CGEN_FIELDS * fields;
+ bfd_vma value;
+{
+ switch (opindex)
+ {
+ case M32R_OPERAND_SR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC1 :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC2 :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_SCR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DCR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SIMM8 :
+ fields->f_simm8 = value;
+ break;
+ case M32R_OPERAND_SIMM16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_UIMM4 :
+ fields->f_uimm4 = value;
+ break;
+ case M32R_OPERAND_UIMM5 :
+ fields->f_uimm5 = value;
+ break;
+ case M32R_OPERAND_UIMM16 :
+ fields->f_uimm16 = value;
+ break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ fields->f_imm1 = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ fields->f_accd = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ fields->f_accs = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ fields->f_acc = value;
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ fields->f_nil = value;
+ break;
+ case M32R_OPERAND_HI16 :
+ fields->f_hi16 = value;
+ break;
+ case M32R_OPERAND_SLO16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_ULO16 :
+ fields->f_uimm16 = value;
+ break;
+ case M32R_OPERAND_UIMM24 :
+ fields->f_uimm24 = value;
+ break;
+ case M32R_OPERAND_DISP8 :
+ fields->f_disp8 = value;
+ break;
+ case M32R_OPERAND_DISP16 :
+ fields->f_disp16 = value;
+ break;
+ case M32R_OPERAND_DISP24 :
+ fields->f_disp24 = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+