-/* CGEN opcode support for m32r.
+/* Generic opcode table support for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
-This file is machine generated.
+THIS FILE IS USED TO GENERATE m32r-opc.c.
-Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+Copyright (C) 1998 Free Software Foundation, Inc.
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "libiberty.h"
#include "bfd.h"
+#include "symcat.h"
#include "m32r-opc.h"
+#include "opintl.h"
+
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
+
+/* Cover function to read and properly byteswap an insn value. */
+
+CGEN_INSN_INT
+cgen_get_insn_value (od, buf, length)
+ CGEN_OPCODE_DESC od;
+ unsigned char *buf;
+ int length;
+{
+ CGEN_INSN_INT value;
+
+ switch (length)
+ {
+ case 8:
+ value = *buf;
+ break;
+ case 16:
+ if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
+ value = bfd_getb16 (buf);
+ else
+ value = bfd_getl16 (buf);
+ break;
+ case 32:
+ if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
+ value = bfd_getb32 (buf);
+ else
+ value = bfd_getl32 (buf);
+ break;
+ default:
+ abort ();
+ }
+
+ return value;
+}
+
+/* Cover function to store an insn value properly byteswapped. */
+
+void
+cgen_put_insn_value (od, buf, length, value)
+ CGEN_OPCODE_DESC od;
+ unsigned char *buf;
+ int length;
+ CGEN_INSN_INT value;
+{
+ switch (length)
+ {
+ case 8:
+ buf[0] = value;
+ break;
+ case 16:
+ if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
+ bfd_putb16 (value, buf);
+ else
+ bfd_putl16 (value, buf);
+ break;
+ case 32:
+ if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
+ bfd_putb32 (value, buf);
+ else
+ bfd_putl32 (value, buf);
+ break;
+ default:
+ abort ();
+ }
+}
+
+/* Look up instruction INSN_VALUE and extract its fields.
+ INSN, if non-null, is the insn table entry.
+ Otherwise INSN_VALUE is examined to compute it.
+ LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
+ 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
+ If INSN != NULL, LENGTH must be valid.
+ ALIAS_P is non-zero if alias insns are to be included in the search.
+
+ The result a pointer to the insn table entry, or NULL if the instruction
+ wasn't recognized. */
+
+const CGEN_INSN *
+m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
+ CGEN_OPCODE_DESC od;
+ const CGEN_INSN *insn;
+ CGEN_INSN_BYTES insn_value;
+ int length;
+ CGEN_FIELDS *fields;
+ int alias_p;
+{
+ unsigned char buf[16];
+ unsigned char *bufp;
+ unsigned int base_insn;
+#if CGEN_INT_INSN_P
+ CGEN_EXTRACT_INFO *info = NULL;
+#else
+ CGEN_EXTRACT_INFO ex_info;
+ CGEN_EXTRACT_INFO *info = &ex_info;
+#endif
+#if ! CGEN_INT_INSN_P
+ ex_info.dis_info = NULL;
+ ex_info.bytes = insn_value;
+ ex_info.valid = -1;
+#endif
+
+ if (!insn)
+ {
+ const CGEN_INSN_LIST *insn_list;
+
+#if CGEN_INT_INSN_P
+ cgen_put_insn_value (od, buf, length, insn_value);
+ bufp = buf;
+ base_insn = insn_value; /*???*/
+#else
+ base_insn = cgen_get_insn_value (od, buf, length);
+ bufp = insn_value;
+#endif
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
+ while (insn_list != NULL)
+ {
+ insn = insn_list->insn;
+
+ if (alias_p
+ || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
+ {
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the
+ extract handler. */
+ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ {
+ /* ??? 0 is passed for `pc' */
+ int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
+ insn_value, fields,
+ (bfd_vma) 0);
+ if (elength > 0)
+ {
+ /* sanity check */
+ if (length != 0 && length != elength)
+ abort ();
+ return insn;
+ }
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+ }
+ else
+ {
+ /* Sanity check: can't pass an alias insn if ! alias_p. */
+ if (! alias_p
+ && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
+ abort ();
+ /* Sanity check: length must be correct. */
+ if (length != CGEN_INSN_BITSIZE (insn))
+ abort ();
+
+ /* ??? 0 is passed for `pc' */
+ length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
+ (bfd_vma) 0);
+ /* Sanity check: must succeed.
+ Could relax this later if it ever proves useful. */
+ if (length == 0)
+ abort ();
+ return insn;
+ }
+
+ return NULL;
+}
+
+/* Fill in the operand instances used by INSN whose operands are FIELDS.
+ INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
+ in. */
+
+void
+m32r_cgen_get_insn_operands (od, insn, fields, indices)
+ CGEN_OPCODE_DESC od;
+ const CGEN_INSN * insn;
+ const CGEN_FIELDS * fields;
+ int *indices;
+{
+ const CGEN_OPERAND_INSTANCE *opinst;
+ int i;
+
+ for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
+ opinst != NULL
+ && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
+ ++i, ++opinst)
+ {
+ const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
+ if (op == NULL)
+ indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
+ else
+ indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
+ fields);
+ }
+}
+
+/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
+ isn't known.
+ The INSN, INSN_VALUE, and LENGTH arguments are passed to
+ m32r_cgen_lookup_insn unchanged.
+
+ The result is the insn table entry or NULL if the instruction wasn't
+ recognized. */
+
+const CGEN_INSN *
+m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
+ CGEN_OPCODE_DESC od;
+ const CGEN_INSN *insn;
+ CGEN_INSN_BYTES insn_value;
+ int length;
+ int *indices;
+{
+ CGEN_FIELDS fields;
+
+ /* Pass non-zero for ALIAS_P only if INSN != NULL.
+ If INSN == NULL, we want a real insn. */
+ insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
+ insn != NULL);
+ if (! insn)
+ return NULL;
+
+ m32r_cgen_get_insn_operands (od, insn, &fields, indices);
+ return insn;
+}
/* Attributes. */
-static const CGEN_ATTR_ENTRY MACH_attr[] =
-{ { "m32r", MACH_M32R },
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+ { "base", MACH_BASE },
+ { "m32r", MACH_M32R },
+/* start-sanitize-m32rx */
+ { "m32rx", MACH_M32RX },
+/* end-sanitize-m32rx */
+ { "max", MACH_MAX },
{ 0, 0 }
};
-const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
-{ { "ABS-ADDR", NULL },
- { "FAKE", NULL },
- { "NEGATIVE", NULL },
+/* start-sanitize-m32rx */
+static const CGEN_ATTR_ENTRY PIPE_attr[] =
+{
+ { "NONE", PIPE_NONE },
+ { "O", PIPE_O },
+ { "S", PIPE_S },
+ { "OS", PIPE_OS },
+ { 0, 0 }
+};
+
+/* end-sanitize-m32rx */
+const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0] },
+ { "CACHE-ADDR", NULL },
+ { "FUN-ACCESS", NULL },
{ "PC", NULL },
+ { "PROFILE", NULL },
+ { "SIGN-OPT", NULL },
+ { "UNSIGNED", NULL },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
+{
+ { "ABS-ADDR", NULL },
+ { "HASH-PREFIX", NULL },
+ { "NEGATIVE", NULL },
{ "PCREL-ADDR", NULL },
{ "RELAX", NULL },
{ "RELOC", NULL },
+ { "SEM-ONLY", NULL },
{ "SIGN-OPT", NULL },
{ "UNSIGNED", NULL },
{ 0, 0 }
};
-const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
-{ { "ALIAS", NULL },
+const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0] },
+/* start-sanitize-m32rx */
+ { "PIPE", & PIPE_attr[0] },
+/* end-sanitize-m32rx */
+ { "ALIAS", NULL },
{ "COND-CTI", NULL },
{ "FILL-SLOT", NULL },
+ { "NO-DIS", NULL },
{ "RELAX", NULL },
- { "RELAX-BC", NULL },
- { "RELAX-BL", NULL },
- { "RELAX-BNC", NULL },
- { "RELAX-BRA", NULL },
{ "RELAXABLE", NULL },
+ { "SKIP-CTI", NULL },
+ { "SPECIAL", NULL },
{ "UNCOND-CTI", NULL },
+ { "VIRTUAL", NULL },
{ 0, 0 }
};
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] =
-{ { "m32r", MACH_M32R }
-};
-
-CGEN_KEYWORD m32r_cgen_opval_mach =
-{ & m32r_cgen_opval_mach_entries[0],
- 1
-};
-
CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
-{ { "fp", 13 },
+{
+ { "fp", 13 },
{ "lr", 14 },
{ "sp", 15 },
{ "r0", 0 },
};
CGEN_KEYWORD m32r_cgen_opval_h_gr =
-{ & m32r_cgen_opval_h_gr_entries[0],
+{
+ & m32r_cgen_opval_h_gr_entries[0],
19
};
CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
-{ { "psw", 0 },
+{
+ { "psw", 0 },
{ "cbr", 1 },
{ "spi", 2 },
{ "spu", 3 },
{ "bpc", 6 },
+ { "bbpsw", 8 },
+ { "bbpc", 14 },
{ "cr0", 0 },
{ "cr1", 1 },
{ "cr2", 2 },
{ "cr3", 3 },
{ "cr4", 4 },
{ "cr5", 5 },
- { "cr6", 6 }
+ { "cr6", 6 },
+ { "cr7", 7 },
+ { "cr8", 8 },
+ { "cr9", 9 },
+ { "cr10", 10 },
+ { "cr11", 11 },
+ { "cr12", 12 },
+ { "cr13", 13 },
+ { "cr14", 14 },
+ { "cr15", 15 }
};
CGEN_KEYWORD m32r_cgen_opval_h_cr =
-{ & m32r_cgen_opval_h_cr_entries[0],
- 12
-};
-
-
-static CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
-{ { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
- { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
- { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
- { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
-};
-
-
-const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
+{
+ & m32r_cgen_opval_h_cr_entries[0],
+ 23
+};
+
+/* start-sanitize-m32rx */
+CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
+{
+ { "a0", 0 },
+ { "a1", 1 }
+};
+
+CGEN_KEYWORD m32r_cgen_opval_h_accums =
+{
+ & m32r_cgen_opval_h_accums_entries[0],
+ 2
+};
+
+/* end-sanitize-m32rx */
+
+/* The hardware table. */
+
+#define HW_ENT(n) m32r_cgen_hw_entries[n]
+static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
+{
+ { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
+ { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_SIGN_OPT)|(1<<CGEN_HW_UNSIGNED), { (1<<MACH_BASE) } } },
+ { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
+ { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+/* start-sanitize-m32rx */
+ { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } },
+/* end-sanitize-m32rx */
+ { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { 0 }
+};
+
+/* The operand table. */
+
+#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
+#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
+
+const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
{
/* pc: program counter */
- { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
+ { "pc", & HW_ENT (HW_H_PC), 0, 0,
+ { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
/* sr: source register */
- { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "sr", & HW_ENT (HW_H_GR), 12, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* dr: destination register */
- { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "dr", & HW_ENT (HW_H_GR), 4, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* src1: source register 1 */
- { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "src1", & HW_ENT (HW_H_GR), 4, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* src2: source register 2 */
- { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "src2", & HW_ENT (HW_H_GR), 12, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* scr: source control register */
- { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "scr", & HW_ENT (HW_H_CR), 12, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* dcr: destination control register */
- { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "dcr", & HW_ENT (HW_H_CR), 4, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* simm8: 8 bit signed immediate */
- { "simm8", 8, 8, { 0, 0, { 0 } } },
+ { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
/* simm16: 16 bit signed immediate */
- { "simm16", 16, 16, { 0, 0, { 0 } } },
+ { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
/* uimm4: 4 bit trap number */
- { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* uimm5: 5 bit shift count */
- { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* uimm16: 16 bit unsigned immediate */
- { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* start-sanitize-m32rx */
+/* imm1: 1 bit immediate */
+ { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* accd: accumulator destination register */
+ { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* accs: accumulator source register */
+ { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* acc: accumulator reg (d) */
+ { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* end-sanitize-m32rx */
+/* hash: # prefix */
+ { "hash", & HW_ENT (HW_H_SINT), 0, 0,
+ { 0, 0, { 0 } } },
/* hi16: high 16 bit immediate, sign optional */
- { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
+ { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* slo16: 16 bit signed immediate, for low() */
- { "slo16", 16, 16, { 0, 0, { 0 } } },
+ { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
+ { 0, 0, { 0 } } },
/* ulo16: 16 bit unsigned immediate, for low() */
- { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* uimm24: 24 bit address */
- { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* disp8: 8 bit displacement */
- { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
/* disp16: 16 bit displacement */
- { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
+ { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
/* disp24: 24 bit displacement */
- { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
+ { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
/* condbit: condition bit */
- { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
+ { "condbit", & HW_ENT (HW_H_COND), 0, 0,
+ { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
/* accum: accumulator */
- { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-};
-
-#define OP 1 /* syntax value for mnemonic */
-
-static const CGEN_SYNTAX syntax_table[] =
-{/* <op> $dr,$sr */
-/* 0 */ { OP, ' ', 130, ',', 129, 0 },
-/* <op> $dr,$sr,$slo16 */
-/* 1 */ { OP, ' ', 130, ',', 129, ',', 141, 0 },
-/* <op> $dr,$sr,$uimm16 */
-/* 2 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
-/* <op> $dr,$sr,$ulo16 */
-/* 3 */ { OP, ' ', 130, ',', 129, ',', 142, 0 },
-/* <op> $dr,$simm8 */
-/* 4 */ { OP, ' ', 130, ',', 135, 0 },
-/* <op> $dr,$sr,$simm16 */
-/* 5 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
-/* <op> $disp8 */
-/* 6 */ { OP, ' ', 144, 0 },
-/* <op> $disp24 */
-/* 7 */ { OP, ' ', 146, 0 },
-/* <op> $src1,$src2,$disp16 */
-/* 8 */ { OP, ' ', 131, ',', 132, ',', 145, 0 },
-/* <op> $src2,$disp16 */
-/* 9 */ { OP, ' ', 132, ',', 145, 0 },
-/* <op> $src1,$src2 */
-/* 10 */ { OP, ' ', 131, ',', 132, 0 },
-/* <op> $src2,$simm16 */
-/* 11 */ { OP, ' ', 132, ',', 136, 0 },
-/* <op> $src2,$uimm16 */
-/* 12 */ { OP, ' ', 132, ',', 139, 0 },
-/* <op> $sr */
-/* 13 */ { OP, ' ', 129, 0 },
-/* <op> $dr,@$sr */
-/* 14 */ { OP, ' ', 130, ',', '@', 129, 0 },
-/* <op> $dr,@($sr) */
-/* 15 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
-/* <op> $dr,@($slo16,$sr) */
-/* 16 */ { OP, ' ', 130, ',', '@', '(', 141, ',', 129, ')', 0 },
-/* <op> $dr,@($sr,$slo16) */
-/* 17 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 141, ')', 0 },
-/* <op> $dr,@$sr+ */
-/* 18 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
-/* <op> $dr,$uimm24 */
-/* 19 */ { OP, ' ', 130, ',', 143, 0 },
-/* <op> $dr,$slo16 */
-/* 20 */ { OP, ' ', 130, ',', 141, 0 },
-/* <op> $dr */
-/* 21 */ { OP, ' ', 130, 0 },
-/* <op> $dr,$scr */
-/* 22 */ { OP, ' ', 130, ',', 133, 0 },
-/* <op> $src1 */
-/* 23 */ { OP, ' ', 131, 0 },
-/* <op> $sr,$dcr */
-/* 24 */ { OP, ' ', 129, ',', 134, 0 },
-/* <op> */
-/* 25 */ { OP, 0 },
-/* <op> $dr,$hi16 */
-/* 26 */ { OP, ' ', 130, ',', 140, 0 },
-/* <op> $dr,$uimm5 */
-/* 27 */ { OP, ' ', 130, ',', 138, 0 },
-/* <op> $src1,@$src2 */
-/* 28 */ { OP, ' ', 131, ',', '@', 132, 0 },
-/* <op> $src1,@($src2) */
-/* 29 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
-/* <op> $src1,@($slo16,$src2) */
-/* 30 */ { OP, ' ', 131, ',', '@', '(', 141, ',', 132, ')', 0 },
-/* <op> $src1,@($src2,$slo16) */
-/* 31 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 141, ')', 0 },
-/* <op> $src1,@+$src2 */
-/* 32 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
-/* <op> $src1,@-$src2 */
-/* 33 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
-/* <op> $uimm4 */
-/* 34 */ { OP, ' ', 137, 0 },
+ { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
+ { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
};
-#undef OP
+/* Operand references. */
+
+#define INPUT CGEN_OPERAND_INSTANCE_INPUT
+#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
+
+static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
+ { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
+ { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
+ { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
+ { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
+ { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { 0 }
+};
-static const CGEN_FORMAT format_table[] =
-{/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
-/* 0 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
-/* 1 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
-/* 2 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
-/* 3 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.dr.f-simm8.simm8. */
-/* 4 */ { 16, 16, 0xf000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
-/* 5 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.number.f-disp8.disp8. */
-/* 6 */ { 16, 16, 0xff00 },
-/* f-op1.number.f-r1.number.f-disp24.disp24. */
-/* 7 */ { 32, 32, 0xff000000 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
-/* 8 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
-/* 9 */ { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
-/* 10 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
-/* 11 */ { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
-/* 12 */ { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
-/* 13 */ { 32, 32, 0xf0f0ffff },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
-/* 14 */ { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
-/* 15 */ { 32, 32, 0xf0000000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
-/* 16 */ { 32, 32, 0xf0ff0000 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
-/* 17 */ { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
-/* 18 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
-/* 19 */ { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
-/* 20 */ { 16, 16, 0xf0f0 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
-/* 21 */ { 16, 16, 0xffff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
-/* 22 */ { 32, 32, 0xf0ff0000 },
-/* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
-/* 23 */ { 16, 16, 0xf0e0 },
-/* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
-/* 24 */ { 32, 32, 0xf0f00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
-/* 25 */ { 16, 16, 0xfff0 },
-};
-
-#define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
-#define SYN(n) (& syntax_table[n])
-#define FMT(n) (& format_table[n])
-
-const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] =
-{ /* null first entry, end of all hash chains */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
+ { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
+ { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
+ { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
+ { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
+ { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
+ { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
+ { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
+ { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
+ { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
+ { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
+ { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
+ { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
+ { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
+ { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
+ { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
+ { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
+ { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
+ { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
+ { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
+ { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
+ { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
+ { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+/* end-sanitize-m32rx */
+#undef INPUT
+#undef OUTPUT
+
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.
+ This is currently non-static because the simulator accesses it
+ directly. */
+
+const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
{ { 0 }, 0 },
/* add $dr,$sr */
{
{ 1, 1, 1, 1 },
- "add", "add", SYN (0), FMT (0), 0xa0,
- { 0, 0, { 0 } }
+ M32R_INSN_ADD, "add", "add",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xa0,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
-/* add3 $dr,$sr,$slo16 */
+/* add3 $dr,$sr,$hash$slo16 */
{
{ 1, 1, 1, 1 },
- "add3", "add3", SYN (1), FMT (1), 0x80a00000,
- { 0, 0, { 0 } }
+ M32R_INSN_ADD3, "add3", "add3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80a00000,
+ (PTR) & fmt_add3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* and $dr,$sr */
{
{ 1, 1, 1, 1 },
- "and", "and", SYN (0), FMT (0), 0xc0,
- { 0, 0, { 0 } }
+ M32R_INSN_AND, "and", "and",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xc0,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* and3 $dr,$sr,$uimm16 */
{
{ 1, 1, 1, 1 },
- "and3", "and3", SYN (2), FMT (2), 0x80c00000,
- { 0, 0, { 0 } }
+ M32R_INSN_AND3, "and3", "and3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80c00000,
+ (PTR) & fmt_and3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* or $dr,$sr */
{
{ 1, 1, 1, 1 },
- "or", "or", SYN (0), FMT (0), 0xe0,
- { 0, 0, { 0 } }
+ M32R_INSN_OR, "or", "or",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xe0,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
-/* or3 $dr,$sr,$ulo16 */
+/* or3 $dr,$sr,$hash$ulo16 */
{
{ 1, 1, 1, 1 },
- "or3", "or3", SYN (3), FMT (3), 0x80e00000,
- { 0, 0, { 0 } }
+ M32R_INSN_OR3, "or3", "or3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80e00000,
+ (PTR) & fmt_or3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* xor $dr,$sr */
{
{ 1, 1, 1, 1 },
- "xor", "xor", SYN (0), FMT (0), 0xd0,
- { 0, 0, { 0 } }
+ M32R_INSN_XOR, "xor", "xor",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xd0,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* xor3 $dr,$sr,$uimm16 */
{
{ 1, 1, 1, 1 },
- "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
- { 0, 0, { 0 } }
+ M32R_INSN_XOR3, "xor3", "xor3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80d00000,
+ (PTR) & fmt_and3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* addi $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "addi", "addi", SYN (4), FMT (4), 0x4000,
- { 0, 0, { 0 } }
+ M32R_INSN_ADDI, "addi", "addi",
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ { 16, 16, 0xf000 }, 0x4000,
+ (PTR) & fmt_addi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* addv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "addv", "addv", SYN (0), FMT (0), 0x80,
- { 0, 0, { 0 } }
+ M32R_INSN_ADDV, "addv", "addv",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x80,
+ (PTR) & fmt_addv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* addv3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
- { 0, 0, { 0 } }
+ M32R_INSN_ADDV3, "addv3", "addv3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x80800000,
+ (PTR) & fmt_addv3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* addx $dr,$sr */
{
{ 1, 1, 1, 1 },
- "addx", "addx", SYN (0), FMT (0), 0x90,
- { 0, 0, { 0 } }
- },
-/* bc $disp8 */
- {
- { 1, 1, 1, 1 },
- "bc8", "bc", SYN (6), FMT (6), 0x7c00,
- { 0, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
+ M32R_INSN_ADDX, "addx", "addx",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x90,
+ (PTR) & fmt_addx_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* bc.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
- { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
- },
-/* bc $disp24 */
- {
- { 1, 1, 1, 1 },
- "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
- { 0, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
+ M32R_INSN_BC8, "bc8", "bc.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7c00,
+ (PTR) & fmt_bc8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bc.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
- { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
+ M32R_INSN_BC24, "bc24", "bc.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfc000000,
+ (PTR) & fmt_bc24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* beq $src1,$src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "beq", "beq", SYN (8), FMT (8), 0xb0000000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BEQ, "beq", "beq",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0xb0000000,
+ (PTR) & fmt_beq_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* beqz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BEQZ, "beqz", "beqz",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0800000,
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bgez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BGEZ, "bgez", "bgez",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0b00000,
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bgtz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BGTZ, "bgtz", "bgtz",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0d00000,
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* blez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BLEZ, "blez", "blez",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0c00000,
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bltz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BLTZ, "bltz", "bltz",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0a00000,
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bnez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
- { 0, 0|A(COND_CTI), { 0 } }
- },
-/* bl $disp8 */
- {
- { 1, 1, 1, 1 },
- "bl8", "bl", SYN (6), FMT (6), 0x7e00,
- { 0, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BNEZ, "bnez", "bnez",
+ { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xfff00000 }, 0xb0900000,
+ (PTR) & fmt_beqz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
- { 0, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { 0 } }
- },
-/* bl $disp24 */
- {
- { 1, 1, 1, 1 },
- "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
- { 0, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BL8, "bl8", "bl.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7e00,
+ (PTR) & fmt_bl8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
- { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BL24, "bl24", "bl.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfe000000,
+ (PTR) & fmt_bl24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* bnc $disp8 */
+/* start-sanitize-m32rx */
+/* bcl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
- { 0, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
+ M32R_INSN_BCL8, "bcl8", "bcl.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7800,
+ (PTR) & fmt_bcl8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
-/* bnc.s $disp8 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* bcl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
- { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
+ M32R_INSN_BCL24, "bcl24", "bcl.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf8000000,
+ (PTR) & fmt_bcl24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* bnc $disp24 */
+/* end-sanitize-m32rx */
+/* bnc.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
- { 0, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
+ M32R_INSN_BNC8, "bnc8", "bnc.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7d00,
+ (PTR) & fmt_bc8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bnc.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
- { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
+ M32R_INSN_BNC24, "bnc24", "bnc.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfd000000,
+ (PTR) & fmt_bc24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bne $src1,$src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bne", "bne", SYN (8), FMT (8), 0xb0100000,
- { 0, 0|A(COND_CTI), { 0 } }
+ M32R_INSN_BNE, "bne", "bne",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0xb0100000,
+ (PTR) & fmt_beq_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* bra $disp8 */
+/* bra.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bra8", "bra", SYN (6), FMT (6), 0x7f00,
- { 0, 0|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BRA8, "bra8", "bra.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7f00,
+ (PTR) & fmt_bra8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
-/* bra.s $disp8 */
+/* bra.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
- { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BRA24, "bra24", "bra.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xff000000,
+ (PTR) & fmt_bra24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* bra $disp24 */
+/* start-sanitize-m32rx */
+/* bncl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bra24", "bra", SYN (7), FMT (7), 0xff000000,
- { 0, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BNCL8, "bncl8", "bncl.s",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7900,
+ (PTR) & fmt_bcl8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
-/* bra.l $disp24 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* bncl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
- { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_BNCL24, "bncl24", "bncl.l",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf9000000,
+ (PTR) & fmt_bcl24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
+/* end-sanitize-m32rx */
/* cmp $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmp", "cmp", SYN (10), FMT (10), 0x40,
- { 0, 0, { 0 } }
+ M32R_INSN_CMP, "cmp", "cmp",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x40,
+ (PTR) & fmt_cmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* cmpi $src2,$simm16 */
{
{ 1, 1, 1, 1 },
- "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
- { 0, 0, { 0 } }
+ M32R_INSN_CMPI, "cmpi", "cmpi",
+ { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xfff00000 }, 0x80400000,
+ (PTR) & fmt_cmpi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* cmpu $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
- { 0, 0, { 0 } }
+ M32R_INSN_CMPU, "cmpu", "cmpu",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50,
+ (PTR) & fmt_cmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* cmpui $src2,$simm16 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_CMPUI, "cmpui", "cmpui",
+ { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xfff00000 }, 0x80500000,
+ (PTR) & fmt_cmpi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* start-sanitize-m32rx */
+/* cmpeq $src1,$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x60,
+ (PTR) & fmt_cmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
-/* cmpui $src2,$uimm16 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* cmpz $src2 */
{
{ 1, 1, 1, 1 },
- "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
- { 0, 0, { 0 } }
+ M32R_INSN_CMPZ, "cmpz", "cmpz",
+ { { MNEM, ' ', OP (SRC2), 0 } },
+ { 16, 16, 0xfff0 }, 0x70,
+ (PTR) & fmt_cmpz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
+/* end-sanitize-m32rx */
/* div $dr,$sr */
{
{ 1, 1, 1, 1 },
- "div", "div", SYN (0), FMT (13), 0x90000000,
- { 0, 0, { 0 } }
+ M32R_INSN_DIV, "div", "div",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90000000,
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* divu $dr,$sr */
{
{ 1, 1, 1, 1 },
- "divu", "divu", SYN (0), FMT (13), 0x90100000,
- { 0, 0, { 0 } }
+ M32R_INSN_DIVU, "divu", "divu",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90100000,
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* rem $dr,$sr */
{
{ 1, 1, 1, 1 },
- "rem", "rem", SYN (0), FMT (13), 0x90200000,
- { 0, 0, { 0 } }
+ M32R_INSN_REM, "rem", "rem",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90200000,
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* remu $dr,$sr */
{
{ 1, 1, 1, 1 },
- "remu", "remu", SYN (0), FMT (13), 0x90300000,
- { 0, 0, { 0 } }
+ M32R_INSN_REMU, "remu", "remu",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90300000,
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* jl $sr */
+/* start-sanitize-m32rx */
+/* divh $dr,$sr */
{
{ 1, 1, 1, 1 },
- "jl", "jl", SYN (13), FMT (14), 0x1ec0,
- { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_DIVH, "divh", "divh",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x90000010,
+ (PTR) & fmt_div_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* jmp $sr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* jc $sr */
{
{ 1, 1, 1, 1 },
- "jmp", "jmp", SYN (13), FMT (14), 0x1fc0,
- { 0, 0|A(UNCOND_CTI), { 0 } }
+ M32R_INSN_JC, "jc", "jc",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1cc0,
+ (PTR) & fmt_jc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
-/* ld $dr,@$sr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* jnc $sr */
{
{ 1, 1, 1, 1 },
- "ld", "ld", SYN (14), FMT (0), 0x20c0,
- { 0, 0, { 0 } }
+ M32R_INSN_JNC, "jnc", "jnc",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1dc0,
+ (PTR) & fmt_jc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
-/* ld $dr,@($sr) */
+/* end-sanitize-m32rx */
+/* jl $sr */
{
{ 1, 1, 1, 1 },
- "ld-2", "ld", SYN (15), FMT (0), 0x20c0,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_JL, "jl", "jl",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1ec0,
+ (PTR) & fmt_jl_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
-/* ld $dr,@($slo16,$sr) */
+/* jmp $sr */
{
{ 1, 1, 1, 1 },
- "ld-d", "ld", SYN (16), FMT (1), 0xa0c00000,
- { 0, 0, { 0 } }
+ M32R_INSN_JMP, "jmp", "jmp",
+ { { MNEM, ' ', OP (SR), 0 } },
+ { 16, 16, 0xfff0 }, 0x1fc0,
+ (PTR) & fmt_jmp_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
-/* ld $dr,@($sr,$slo16) */
+/* ld $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ld-d2", "ld", SYN (17), FMT (1), 0xa0c00000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LD, "ld", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20c0,
+ (PTR) & fmt_ld_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
-/* ldb $dr,@$sr */
+/* ld $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldb", "ldb", SYN (14), FMT (0), 0x2080,
- { 0, 0, { 0 } }
+ M32R_INSN_LD_D, "ld-d", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0c00000,
+ (PTR) & fmt_ld_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* ldb $dr,@($sr) */
+/* ldb $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldb-2", "ldb", SYN (15), FMT (0), 0x2080,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LDB, "ldb", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2080,
+ (PTR) & fmt_ldb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
/* ldb $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldb-d", "ldb", SYN (16), FMT (1), 0xa0800000,
- { 0, 0, { 0 } }
- },
-/* ldb $dr,@($sr,$slo16) */
- {
- { 1, 1, 1, 1 },
- "ldb-d2", "ldb", SYN (17), FMT (1), 0xa0800000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LDB_D, "ldb-d", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0800000,
+ (PTR) & fmt_ldb_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* ldh $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldh", "ldh", SYN (14), FMT (0), 0x20a0,
- { 0, 0, { 0 } }
+ M32R_INSN_LDH, "ldh", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20a0,
+ (PTR) & fmt_ldh_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
-/* ldh $dr,@($sr) */
+/* ldh $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldh-2", "ldh", SYN (15), FMT (0), 0x20a0,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LDH_D, "ldh-d", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0a00000,
+ (PTR) & fmt_ldh_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* ldh $dr,@($slo16,$sr) */
+/* ldub $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldh-d", "ldh", SYN (16), FMT (1), 0xa0a00000,
- { 0, 0, { 0 } }
+ M32R_INSN_LDUB, "ldub", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2090,
+ (PTR) & fmt_ldb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
-/* ldh $dr,@($sr,$slo16) */
+/* ldub $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldh-d2", "ldh", SYN (17), FMT (1), 0xa0a00000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LDUB_D, "ldub-d", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0900000,
+ (PTR) & fmt_ldb_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* ldub $dr,@$sr */
+/* lduh $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldub", "ldub", SYN (14), FMT (0), 0x2090,
- { 0, 0, { 0 } }
+ M32R_INSN_LDUH, "lduh", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20b0,
+ (PTR) & fmt_ldh_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
-/* ldub $dr,@($sr) */
+/* lduh $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldub-2", "ldub", SYN (15), FMT (0), 0x2090,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LDUH_D, "lduh-d", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0b00000,
+ (PTR) & fmt_ldh_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* ldub $dr,@($slo16,$sr) */
+/* ld $dr,@$sr+ */
{
{ 1, 1, 1, 1 },
- "ldub-d", "ldub", SYN (16), FMT (1), 0xa0900000,
- { 0, 0, { 0 } }
+ M32R_INSN_LD_PLUS, "ld-plus", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20e0,
+ (PTR) & fmt_ld_plus_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
-/* ldub $dr,@($sr,$slo16) */
+/* ld24 $dr,$uimm24 */
{
{ 1, 1, 1, 1 },
- "ldub-d2", "ldub", SYN (17), FMT (1), 0xa0900000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LD24, "ld24", "ld24",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
+ { 32, 32, 0xf0000000 }, 0xe0000000,
+ (PTR) & fmt_ld24_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* lduh $dr,@$sr */
+/* ldi8 $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "lduh", "lduh", SYN (14), FMT (0), 0x20b0,
- { 0, 0, { 0 } }
+ M32R_INSN_LDI8, "ldi8", "ldi8",
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ { 16, 16, 0xf000 }, 0x6000,
+ (PTR) & fmt_ldi8_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
-/* lduh $dr,@($sr) */
+/* ldi16 $dr,$hash$slo16 */
{
{ 1, 1, 1, 1 },
- "lduh-2", "lduh", SYN (15), FMT (0), 0x20b0,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_LDI16, "ldi16", "ldi16",
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
+ { 32, 32, 0xf0ff0000 }, 0x90f00000,
+ (PTR) & fmt_ldi16_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
-/* lduh $dr,@($slo16,$sr) */
+/* lock $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "lduh-d", "lduh", SYN (16), FMT (1), 0xa0b00000,
- { 0, 0, { 0 } }
+ M32R_INSN_LOCK, "lock", "lock",
+ { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20d0,
+ (PTR) & fmt_lock_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
-/* lduh $dr,@($sr,$slo16) */
+/* machi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "lduh-d2", "lduh", SYN (17), FMT (1), 0xa0b00000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_MACHI, "machi", "machi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3040,
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ld $dr,@$sr+ */
+/* start-sanitize-m32rx */
+/* machi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ld-plus", "ld", SYN (18), FMT (0), 0x20e0,
- { 0, 0, { 0 } }
+ M32R_INSN_MACHI_A, "machi-a", "machi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3040,
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* ld24 $dr,$uimm24 */
+/* end-sanitize-m32rx */
+/* maclo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ld24", "ld24", SYN (19), FMT (15), 0xe0000000,
- { 0, 0, { 0 } }
+ M32R_INSN_MACLO, "maclo", "maclo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3050,
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ldi $dr,$simm8 */
+/* start-sanitize-m32rx */
+/* maclo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
- { 0, 0, { 0 } }
+ M32R_INSN_MACLO_A, "maclo-a", "maclo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3050,
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* ldi8 $dr,$simm8 */
+/* end-sanitize-m32rx */
+/* macwhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_MACWHI, "macwhi", "macwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3060,
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* ldi $dr,$slo16 */
+/* start-sanitize-m32rx */
+/* macwhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "ldi16", "ldi", SYN (20), FMT (16), 0x90f00000,
- { 0, 0, { 0 } }
+ M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3060,
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
-/* ldi16 $dr,$slo16 */
+/* end-sanitize-m32rx */
+/* macwlo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "ldi16a", "ldi16", SYN (20), FMT (16), 0x90f00000,
- { 0, 0|A(ALIAS), { 0 } }
+ M32R_INSN_MACWLO, "macwlo", "macwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3070,
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* lock $dr,@$sr */
+/* start-sanitize-m32rx */
+/* macwlo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "lock", "lock", SYN (14), FMT (0), 0x20d0,
- { 0, 0, { 0 } }
+ M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3070,
+ (PTR) & fmt_machi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
-/* machi $src1,$src2 */
+/* end-sanitize-m32rx */
+/* mul $dr,$sr */
{
{ 1, 1, 1, 1 },
- "machi", "machi", SYN (10), FMT (10), 0x3040,
- { 0, 0, { 0 } }
+ M32R_INSN_MUL, "mul", "mul",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1060,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
},
-/* maclo $src1,$src2 */
+/* mulhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "maclo", "maclo", SYN (10), FMT (10), 0x3050,
- { 0, 0, { 0 } }
+ M32R_INSN_MULHI, "mulhi", "mulhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3000,
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* macwhi $src1,$src2 */
+/* start-sanitize-m32rx */
+/* mulhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
- { 0, 0, { 0 } }
+ M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3000,
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* macwlo $src1,$src2 */
+/* end-sanitize-m32rx */
+/* mullo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
- { 0, 0, { 0 } }
+ M32R_INSN_MULLO, "mullo", "mullo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3010,
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* mul $dr,$sr */
+/* start-sanitize-m32rx */
+/* mullo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "mul", "mul", SYN (0), FMT (0), 0x1060,
- { 0, 0, { 0 } }
+ M32R_INSN_MULLO_A, "mullo-a", "mullo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3010,
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* mulhi $src1,$src2 */
+/* end-sanitize-m32rx */
+/* mulwhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
- { 0, 0, { 0 } }
+ M32R_INSN_MULWHI, "mulwhi", "mulwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3020,
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* mullo $src1,$src2 */
+/* start-sanitize-m32rx */
+/* mulwhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "mullo", "mullo", SYN (10), FMT (10), 0x3010,
- { 0, 0, { 0 } }
+ M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3020,
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
-/* mulwhi $src1,$src2 */
+/* end-sanitize-m32rx */
+/* mulwlo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
- { 0, 0, { 0 } }
+ M32R_INSN_MULWLO, "mulwlo", "mulwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x3030,
+ (PTR) & fmt_mulhi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
-/* mulwlo $src1,$src2 */
+/* start-sanitize-m32rx */
+/* mulwlo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
- { 0, 0, { 0 } }
+ M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
+ { 16, 16, 0xf070 }, 0x3030,
+ (PTR) & fmt_mulhi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
+/* end-sanitize-m32rx */
/* mv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "mv", "mv", SYN (0), FMT (0), 0x1080,
- { 0, 0, { 0 } }
+ M32R_INSN_MV, "mv", "mv",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1080,
+ (PTR) & fmt_mv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* mvfachi $dr */
{
{ 1, 1, 1, 1 },
- "mvfachi", "mvfachi", SYN (21), FMT (17), 0x50f0,
- { 0, 0, { 0 } }
+ M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x50f0,
+ (PTR) & fmt_mvfachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
+ },
+/* start-sanitize-m32rx */
+/* mvfachi $dr,$accs */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
+ { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x50f0,
+ (PTR) & fmt_mvfachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
+/* end-sanitize-m32rx */
/* mvfaclo $dr */
{
{ 1, 1, 1, 1 },
- "mvfaclo", "mvfaclo", SYN (21), FMT (17), 0x50f1,
- { 0, 0, { 0 } }
+ M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x50f1,
+ (PTR) & fmt_mvfachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
+/* start-sanitize-m32rx */
+/* mvfaclo $dr,$accs */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
+ { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x50f1,
+ (PTR) & fmt_mvfachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
/* mvfacmi $dr */
{
{ 1, 1, 1, 1 },
- "mvfacmi", "mvfacmi", SYN (21), FMT (17), 0x50f2,
- { 0, 0, { 0 } }
+ M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x50f2,
+ (PTR) & fmt_mvfachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
+ },
+/* start-sanitize-m32rx */
+/* mvfacmi $dr,$accs */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
+ { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x50f2,
+ (PTR) & fmt_mvfachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* mvfc $dr,$scr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVFC, "mvfc", "mvfc",
+ { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1090,
+ (PTR) & fmt_mvfc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* mvtachi $src1 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ { 16, 16, 0xf0ff }, 0x5070,
+ (PTR) & fmt_mvtachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
+ },
+/* start-sanitize-m32rx */
+/* mvtachi $src1,$accs */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
+ { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x5070,
+ (PTR) & fmt_mvtachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* mvtaclo $src1 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ { 16, 16, 0xf0ff }, 0x5071,
+ (PTR) & fmt_mvtachi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
+ },
+/* start-sanitize-m32rx */
+/* mvtaclo $src1,$accs */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf0f3 }, 0x5071,
+ (PTR) & fmt_mvtachi_a_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* mvtc $sr,$dcr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MVTC, "mvtc", "mvtc",
+ { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x10a0,
+ (PTR) & fmt_mvtc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* neg $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_NEG, "neg", "neg",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x30,
+ (PTR) & fmt_mv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* nop */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_NOP, "nop", "nop",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x7000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* not $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_NOT, "not", "not",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0xb0,
+ (PTR) & fmt_mv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* rac */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_RAC, "rac", "rac",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x5090,
+ (PTR) & fmt_rac_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
+ },
+/* start-sanitize-m32rx */
+/* rac $accd,$accs,$imm1 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_RAC_DSI, "rac-dsi", "rac",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
+ { 16, 16, 0xf3f2 }, 0x5090,
+ (PTR) & fmt_rac_dsi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* rach */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_RACH, "rach", "rach",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x5080,
+ (PTR) & fmt_rac_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
+ },
+/* start-sanitize-m32rx */
+/* rach $accd,$accs,$imm1 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_RACH_DSI, "rach-dsi", "rach",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
+ { 16, 16, 0xf3f2 }, 0x5080,
+ (PTR) & fmt_rac_dsi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* rte */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_RTE, "rte", "rte",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x10d6,
+ (PTR) & fmt_rte_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ },
+/* seth $dr,$hash$hi16 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SETH, "seth", "seth",
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
+ { 32, 32, 0xf0ff0000 }, 0xd0c00000,
+ (PTR) & fmt_seth_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* sll $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SLL, "sll", "sll",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1040,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* sll3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SLL3, "sll3", "sll3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x90c00000,
+ (PTR) & fmt_sll3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* slli $dr,$uimm5 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SLLI, "slli", "slli",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
+ { 16, 16, 0xf0e0 }, 0x5040,
+ (PTR) & fmt_slli_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* sra $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SRA, "sra", "sra",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1020,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* sra3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SRA3, "sra3", "sra3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x90a00000,
+ (PTR) & fmt_sll3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* srai $dr,$uimm5 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SRAI, "srai", "srai",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
+ { 16, 16, 0xf0e0 }, 0x5020,
+ (PTR) & fmt_slli_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* srl $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SRL, "srl", "srl",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x1000,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* srl3 $dr,$sr,$simm16 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SRL3, "srl3", "srl3",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
+ { 32, 32, 0xf0f00000 }, 0x90800000,
+ (PTR) & fmt_sll3_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* srli $dr,$uimm5 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SRLI, "srli", "srli",
+ { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
+ { 16, 16, 0xf0e0 }, 0x5000,
+ (PTR) & fmt_slli_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* st $src1,@$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_ST, "st", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2040,
+ (PTR) & fmt_st_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* st $src1,@($slo16,$src2) */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_ST_D, "st-d", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0400000,
+ (PTR) & fmt_st_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* stb $src1,@$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_STB, "stb", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2000,
+ (PTR) & fmt_stb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* stb $src1,@($slo16,$src2) */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_STB_D, "stb-d", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0000000,
+ (PTR) & fmt_stb_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* sth $src1,@$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_STH, "sth", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2020,
+ (PTR) & fmt_sth_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* sth $src1,@($slo16,$src2) */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_STH_D, "sth-d", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0200000,
+ (PTR) & fmt_sth_d_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* st $src1,@+$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_ST_PLUS, "st-plus", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2060,
+ (PTR) & fmt_st_plus_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* st $src1,@-$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_ST_MINUS, "st-minus", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2070,
+ (PTR) & fmt_st_plus_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* sub $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SUB, "sub", "sub",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x20,
+ (PTR) & fmt_add_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* subv $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SUBV, "subv", "subv",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x0,
+ (PTR) & fmt_addv_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* subx $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SUBX, "subx", "subx",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 16, 16, 0xf0f0 }, 0x10,
+ (PTR) & fmt_addx_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
+ },
+/* trap $uimm4 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_TRAP, "trap", "trap",
+ { { MNEM, ' ', OP (UIMM4), 0 } },
+ { 16, 16, 0xfff0 }, 0x10f0,
+ (PTR) & fmt_trap_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ },
+/* unlock $src1,@$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_UNLOCK, "unlock", "unlock",
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x2050,
+ (PTR) & fmt_unlock_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
+ },
+/* start-sanitize-m32rx */
+/* satb $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SATB, "satb", "satb",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x80600300,
+ (PTR) & fmt_satb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sath $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SATH, "sath", "sath",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x80600200,
+ (PTR) & fmt_satb_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sat $dr,$sr */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SAT, "sat", "sat",
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ { 32, 32, 0xf0f0ffff }, 0x80600000,
+ (PTR) & fmt_sat_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+ },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* pcmpbz $src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
+ { { MNEM, ' ', OP (SRC2), 0 } },
+ { 16, 16, 0xfff0 }, 0x370,
+ (PTR) & fmt_cmpz_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
+ },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sadd */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_SADD, "sadd", "sadd",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x50e4,
+ (PTR) & fmt_sadd_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
+ },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* macwu1 $src1,$src2 */
+ {
+ { 1, 1, 1, 1 },
+ M32R_INSN_MACWU1, "macwu1", "macwu1",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50b0,
+ (PTR) & fmt_macwu1_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* mvfc $dr,$scr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* msblo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mvfc", "mvfc", SYN (22), FMT (18), 0x1090,
- { 0, 0, { 0 } }
+ M32R_INSN_MSBLO, "msblo", "msblo",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50d0,
+ (PTR) & fmt_machi_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* mvtachi $src1 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* mulwu1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mvtachi", "mvtachi", SYN (23), FMT (19), 0x5070,
- { 0, 0, { 0 } }
+ M32R_INSN_MULWU1, "mulwu1", "mulwu1",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50a0,
+ (PTR) & fmt_mulwu1_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* mvtaclo $src1 */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* maclh1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mvtaclo", "mvtaclo", SYN (23), FMT (19), 0x5071,
- { 0, 0, { 0 } }
+ M32R_INSN_MACLH1, "maclh1", "maclh1",
+ { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+ { 16, 16, 0xf0f0 }, 0x50c0,
+ (PTR) & fmt_macwu1_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
-/* mvtc $sr,$dcr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* sc */
{
{ 1, 1, 1, 1 },
- "mvtc", "mvtc", SYN (24), FMT (20), 0x10a0,
- { 0, 0, { 0 } }
+ M32R_INSN_SC, "sc", "sc",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x7401,
+ (PTR) & fmt_sc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
-/* neg $dr,$sr */
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+/* snc */
{
{ 1, 1, 1, 1 },
- "neg", "neg", SYN (0), FMT (0), 0x30,
- { 0, 0, { 0 } }
+ M32R_INSN_SNC, "snc", "snc",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x7501,
+ (PTR) & fmt_sc_ops[0],
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
-/* nop */
+/* end-sanitize-m32rx */
+};
+
+#undef A
+#undef MNEM
+#undef OP
+
+static const CGEN_INSN_TABLE insn_table =
+{
+ & m32r_cgen_insn_table_entries[0],
+ sizeof (CGEN_INSN),
+ MAX_INSNS,
+ NULL
+};
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_INSN macro_insn_table_entries[] =
+{
+/* bc $disp8 */
{
{ 1, 1, 1, 1 },
- "nop", "nop", SYN (25), FMT (21), 0x7000,
- { 0, 0, { 0 } }
+ -1, "bc8r", "bc",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7c00,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* not $dr,$sr */
+/* bc $disp24 */
{
{ 1, 1, 1, 1 },
- "not", "not", SYN (0), FMT (0), 0xb0,
- { 0, 0, { 0 } }
+ -1, "bc24r", "bc",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfc000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* rac */
+/* bl $disp8 */
{
{ 1, 1, 1, 1 },
- "rac", "rac", SYN (25), FMT (21), 0x5090,
- { 0, 0, { 0 } }
+ -1, "bl8r", "bl",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7e00,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* rach */
+/* bl $disp24 */
{
{ 1, 1, 1, 1 },
- "rach", "rach", SYN (25), FMT (21), 0x5080,
- { 0, 0, { 0 } }
+ -1, "bl24r", "bl",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfe000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* rte */
+/* bcl $disp8 */
{
{ 1, 1, 1, 1 },
- "rte", "rte", SYN (25), FMT (21), 0x10d6,
- { 0, 0|A(UNCOND_CTI), { 0 } }
+ -1, "bcl8r", "bcl",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7800,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
},
-/* seth $dr,$hi16 */
+/* bcl $disp24 */
{
{ 1, 1, 1, 1 },
- "seth", "seth", SYN (26), FMT (22), 0xd0c00000,
- { 0, 0, { 0 } }
+ -1, "bcl24r", "bcl",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf8000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* sll $dr,$sr */
+/* bnc $disp8 */
{
{ 1, 1, 1, 1 },
- "sll", "sll", SYN (0), FMT (0), 0x1040,
- { 0, 0, { 0 } }
+ -1, "bnc8r", "bnc",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7d00,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* sll3 $dr,$sr,$simm16 */
+/* bnc $disp24 */
{
{ 1, 1, 1, 1 },
- "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
- { 0, 0, { 0 } }
+ -1, "bnc24r", "bnc",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xfd000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* slli $dr,$uimm5 */
+/* bra $disp8 */
{
{ 1, 1, 1, 1 },
- "slli", "slli", SYN (27), FMT (23), 0x5040,
- { 0, 0, { 0 } }
+ -1, "bra8r", "bra",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7f00,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* sra $dr,$sr */
+/* bra $disp24 */
{
{ 1, 1, 1, 1 },
- "sra", "sra", SYN (0), FMT (0), 0x1020,
- { 0, 0, { 0 } }
+ -1, "bra24r", "bra",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xff000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* sra3 $dr,$sr,$simm16 */
+/* bncl $disp8 */
{
{ 1, 1, 1, 1 },
- "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
- { 0, 0, { 0 } }
+ -1, "bncl8r", "bncl",
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ { 16, 16, 0xff00 }, 0x7900,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
},
-/* srai $dr,$uimm5 */
+/* bncl $disp24 */
{
{ 1, 1, 1, 1 },
- "srai", "srai", SYN (27), FMT (23), 0x5020,
- { 0, 0, { 0 } }
+ -1, "bncl24r", "bncl",
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ { 32, 32, 0xff000000 }, 0xf9000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
},
-/* srl $dr,$sr */
+/* ld $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "srl", "srl", SYN (0), FMT (0), 0x1000,
- { 0, 0, { 0 } }
+ -1, "ld-2", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20c0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* srl3 $dr,$sr,$simm16 */
+/* ld $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
- { 0, 0, { 0 } }
+ -1, "ld-d2", "ld",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0c00000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* srli $dr,$uimm5 */
+/* ldb $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "srli", "srli", SYN (27), FMT (23), 0x5000,
- { 0, 0, { 0 } }
+ -1, "ldb-2", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2080,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* st $src1,@$src2 */
+/* ldb $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "st", "st", SYN (28), FMT (10), 0x2040,
- { 0, 0, { 0 } }
+ -1, "ldb-d2", "ldb",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0800000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* st $src1,@($src2) */
+/* ldh $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "st-2", "st", SYN (29), FMT (10), 0x2040,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "ldh-2", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20a0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* st $src1,@($slo16,$src2) */
+/* ldh $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "st-d", "st", SYN (30), FMT (24), 0xa0400000,
- { 0, 0, { 0 } }
+ -1, "ldh-d2", "ldh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0a00000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* st $src1,@($src2,$slo16) */
+/* ldub $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "st-d2", "st", SYN (31), FMT (24), 0xa0400000,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "ldub-2", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2090,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* stb $src1,@$src2 */
+/* ldub $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "stb", "stb", SYN (28), FMT (10), 0x2000,
- { 0, 0, { 0 } }
+ -1, "ldub-d2", "ldub",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0900000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* stb $src1,@($src2) */
+/* lduh $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "stb-2", "stb", SYN (29), FMT (10), 0x2000,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "lduh-2", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x20b0,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* stb $src1,@($slo16,$src2) */
+/* lduh $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "stb-d", "stb", SYN (30), FMT (24), 0xa0000000,
- { 0, 0, { 0 } }
+ -1, "lduh-d2", "lduh",
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0b00000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* stb $src1,@($src2,$slo16) */
+/* pop $dr */
{
{ 1, 1, 1, 1 },
- "stb-d2", "stb", SYN (31), FMT (24), 0xa0000000,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "pop", "pop",
+ { { MNEM, ' ', OP (DR), 0 } },
+ { 16, 16, 0xf0ff }, 0x20ef,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* sth $src1,@$src2 */
+/* ldi $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "sth", "sth", SYN (28), FMT (10), 0x2020,
- { 0, 0, { 0 } }
+ -1, "ldi8a", "ldi",
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ { 16, 16, 0xf000 }, 0x6000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
},
-/* sth $src1,@($src2) */
+/* ldi $dr,$hash$slo16 */
{
{ 1, 1, 1, 1 },
- "sth-2", "sth", SYN (29), FMT (10), 0x2020,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "ldi16a", "ldi",
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
+ { 32, 32, 0xf0ff0000 }, 0x90f00000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* sth $src1,@($slo16,$src2) */
+/* rac $accd */
{
{ 1, 1, 1, 1 },
- "sth-d", "sth", SYN (30), FMT (24), 0xa0200000,
- { 0, 0, { 0 } }
+ -1, "rac-d", "rac",
+ { { MNEM, ' ', OP (ACCD), 0 } },
+ { 16, 16, 0xf3ff }, 0x5090,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* sth $src1,@($src2,$slo16) */
+/* rac $accd,$accs */
{
{ 1, 1, 1, 1 },
- "sth-d2", "sth", SYN (31), FMT (24), 0xa0200000,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "rac-ds", "rac",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf3f3 }, 0x5090,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* st $src1,@+$src2 */
+/* rach $accd */
{
{ 1, 1, 1, 1 },
- "st-plus", "st", SYN (32), FMT (10), 0x2060,
- { 0, 0, { 0 } }
+ -1, "rach-d", "rach",
+ { { MNEM, ' ', OP (ACCD), 0 } },
+ { 16, 16, 0xf3ff }, 0x5080,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* st $src1,@-$src2 */
+/* rach $accd,$accs */
{
{ 1, 1, 1, 1 },
- "st-minus", "st", SYN (33), FMT (10), 0x2070,
- { 0, 0, { 0 } }
+ -1, "rach-ds", "rach",
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+ { 16, 16, 0xf3f3 }, 0x5080,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
-/* sub $dr,$sr */
+/* st $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "sub", "sub", SYN (0), FMT (0), 0x20,
- { 0, 0, { 0 } }
+ -1, "st-2", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2040,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* subv $dr,$sr */
+/* st $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "subv", "subv", SYN (0), FMT (0), 0x0,
- { 0, 0, { 0 } }
+ -1, "st-d2", "st",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0400000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* subx $dr,$sr */
+/* stb $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "subx", "subx", SYN (0), FMT (0), 0x10,
- { 0, 0, { 0 } }
+ -1, "stb-2", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* trap $uimm4 */
+/* stb $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "trap", "trap", SYN (34), FMT (25), 0x10f0,
- { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
+ -1, "stb-d2", "stb",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0000000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* unlock $src1,@$src2 */
+/* sth $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "unlock", "unlock", SYN (28), FMT (10), 0x2050,
- { 0, 0, { 0 } }
+ -1, "sth-2", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ { 16, 16, 0xf0f0 }, 0x2020,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
-/* push $src1 */
+/* sth $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "push", "push", SYN (23), FMT (19), 0x207f,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "sth-d2", "sth",
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ { 32, 32, 0xf0f00000 }, 0xa0200000,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
-/* pop $dr */
+/* push $src1 */
{
{ 1, 1, 1, 1 },
- "pop", "pop", SYN (21), FMT (17), 0x20ef,
- { 0, 0|A(ALIAS), { 0 } }
+ -1, "push", "push",
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ { 16, 16, 0xf0ff }, 0x207f,
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
};
#undef A
-#undef SYN
-#undef FMT
+#undef MNEM
+#undef OP
-CGEN_INSN_TABLE m32r_cgen_insn_table =
+static const CGEN_INSN_TABLE macro_insn_table =
{
- & m32r_cgen_insn_table_entries[0],
+ & macro_insn_table_entries[0],
sizeof (CGEN_INSN),
- CGEN_NUM_INSNS,
- NULL,
- m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
- m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
+ (sizeof (macro_insn_table_entries) /
+ sizeof (macro_insn_table_entries[0])),
+ NULL
};
-/* The hash functions are recorded here to help keep assembler code out of
- the disassembler and vice versa. */
+static void
+init_tables ()
+{
+}
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
-unsigned int
-m32r_cgen_asm_hash_insn (insn)
- const char * insn;
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN * insn;
{
- return CGEN_ASM_HASH (insn);
+ return CGEN_ASM_HASH_P (insn);
}
-unsigned int
-m32r_cgen_dis_hash_insn (buf, value)
- const char * buf;
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN * insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the insn's bytes in target order.
+ VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
+ host order. */
+
+static unsigned int
+dis_hash_insn (buf, value)
+ const char * buf;
unsigned long value;
{
return CGEN_DIS_HASH (buf, value);
}
-CGEN_OPCODE_DATA m32r_cgen_opcode_data =
-{ & m32r_cgen_hw_entries[0],
- & m32r_cgen_insn_table,
-};
+/* Initialize an opcode table and return a descriptor.
+ It's much like opening a file, and must be the first function called. */
+
+CGEN_OPCODE_DESC
+m32r_cgen_opcode_open (mach, endian)
+ int mach;
+ enum cgen_endian endian;
+{
+ CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
+ static int init_p;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (table, 0, sizeof (*table));
+
+ CGEN_OPCODE_MACH (table) = mach;
+ CGEN_OPCODE_ENDIAN (table) = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ CGEN_OPCODE_INSN_ENDIAN (table) = endian;
+
+ CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
+
+ CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
+
+ * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
+
+ * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
+
+ CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
+ CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
+ CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
+
+ CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
+ CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
+ CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
+
+ return (CGEN_OPCODE_DESC) table;
+}
+
+/* Close an opcode table. */
void
-m32r_cgen_init_tables (mach)
- int mach;
+m32r_cgen_opcode_close (desc)
+ CGEN_OPCODE_DESC desc;
{
+ free (desc);
}
-/* Main entry point for stuffing values in cgen_fields. */
+/* Getting values from cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they return.
+ TODO: floating point, inlining support, remove cases where result type
+ not appropriate. */
-CGEN_INLINE void
-m32r_cgen_set_operand (opindex, valuep, fields)
+int
+m32r_cgen_get_int_operand (opindex, fields)
int opindex;
- const long * valuep;
- CGEN_FIELDS * fields;
+ const CGEN_FIELDS * fields;
{
+ int value;
+
switch (opindex)
{
case M32R_OPERAND_SR :
- fields->f_r2 = * valuep;
+ value = fields->f_r2;
break;
case M32R_OPERAND_DR :
- fields->f_r1 = * valuep;
+ value = fields->f_r1;
break;
case M32R_OPERAND_SRC1 :
- fields->f_r1 = * valuep;
+ value = fields->f_r1;
break;
case M32R_OPERAND_SRC2 :
- fields->f_r2 = * valuep;
+ value = fields->f_r2;
break;
case M32R_OPERAND_SCR :
- fields->f_r2 = * valuep;
+ value = fields->f_r2;
break;
case M32R_OPERAND_DCR :
- fields->f_r1 = * valuep;
+ value = fields->f_r1;
break;
case M32R_OPERAND_SIMM8 :
- fields->f_simm8 = * valuep;
+ value = fields->f_simm8;
break;
case M32R_OPERAND_SIMM16 :
- fields->f_simm16 = * valuep;
+ value = fields->f_simm16;
break;
case M32R_OPERAND_UIMM4 :
- fields->f_uimm4 = * valuep;
+ value = fields->f_uimm4;
break;
case M32R_OPERAND_UIMM5 :
- fields->f_uimm5 = * valuep;
+ value = fields->f_uimm5;
break;
case M32R_OPERAND_UIMM16 :
- fields->f_uimm16 = * valuep;
+ value = fields->f_uimm16;
+ break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ value = fields->f_imm1;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ value = fields->f_accd;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ value = fields->f_accs;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ value = fields->f_acc;
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ value = fields->f_nil;
break;
case M32R_OPERAND_HI16 :
- fields->f_hi16 = * valuep;
+ value = fields->f_hi16;
break;
case M32R_OPERAND_SLO16 :
- fields->f_simm16 = * valuep;
+ value = fields->f_simm16;
break;
case M32R_OPERAND_ULO16 :
- fields->f_uimm16 = * valuep;
+ value = fields->f_uimm16;
break;
case M32R_OPERAND_UIMM24 :
- fields->f_uimm24 = * valuep;
+ value = fields->f_uimm24;
break;
case M32R_OPERAND_DISP8 :
- fields->f_disp8 = * valuep;
+ value = fields->f_disp8;
break;
case M32R_OPERAND_DISP16 :
- fields->f_disp16 = * valuep;
+ value = fields->f_disp16;
break;
case M32R_OPERAND_DISP24 :
- fields->f_disp24 = * valuep;
+ value = fields->f_disp24;
break;
default :
- fprintf (stderr, "Unrecognized field %d while setting operand.\n",
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
opindex);
abort ();
}
-}
-/* Main entry point for getting values from cgen_fields. */
+ return value;
+}
-CGEN_INLINE long
-m32r_cgen_get_operand (opindex, fields)
- int opindex;
+bfd_vma
+m32r_cgen_get_vma_operand (opindex, fields)
+ int opindex;
const CGEN_FIELDS * fields;
{
- long value;
+ bfd_vma value;
switch (opindex)
{
case M32R_OPERAND_UIMM16 :
value = fields->f_uimm16;
break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ value = fields->f_imm1;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ value = fields->f_accd;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ value = fields->f_accs;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ value = fields->f_acc;
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ value = fields->f_nil;
+ break;
case M32R_OPERAND_HI16 :
value = fields->f_hi16;
break;
break;
default :
- fprintf (stderr, "Unrecognized field %d while getting operand.\n",
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
opindex);
abort ();
}
return value;
}
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they accept.
+ TODO: floating point, inlining support, remove cases where argument type
+ not appropriate. */
+
+void
+m32r_cgen_set_int_operand (opindex, fields, value)
+ int opindex;
+ CGEN_FIELDS * fields;
+ int value;
+{
+ switch (opindex)
+ {
+ case M32R_OPERAND_SR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC1 :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC2 :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_SCR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DCR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SIMM8 :
+ fields->f_simm8 = value;
+ break;
+ case M32R_OPERAND_SIMM16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_UIMM4 :
+ fields->f_uimm4 = value;
+ break;
+ case M32R_OPERAND_UIMM5 :
+ fields->f_uimm5 = value;
+ break;
+ case M32R_OPERAND_UIMM16 :
+ fields->f_uimm16 = value;
+ break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ fields->f_imm1 = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ fields->f_accd = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ fields->f_accs = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ fields->f_acc = value;
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ fields->f_nil = value;
+ break;
+ case M32R_OPERAND_HI16 :
+ fields->f_hi16 = value;
+ break;
+ case M32R_OPERAND_SLO16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_ULO16 :
+ fields->f_uimm16 = value;
+ break;
+ case M32R_OPERAND_UIMM24 :
+ fields->f_uimm24 = value;
+ break;
+ case M32R_OPERAND_DISP8 :
+ fields->f_disp8 = value;
+ break;
+ case M32R_OPERAND_DISP16 :
+ fields->f_disp16 = value;
+ break;
+ case M32R_OPERAND_DISP24 :
+ fields->f_disp24 = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+void
+m32r_cgen_set_vma_operand (opindex, fields, value)
+ int opindex;
+ CGEN_FIELDS * fields;
+ bfd_vma value;
+{
+ switch (opindex)
+ {
+ case M32R_OPERAND_SR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC1 :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SRC2 :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_SCR :
+ fields->f_r2 = value;
+ break;
+ case M32R_OPERAND_DCR :
+ fields->f_r1 = value;
+ break;
+ case M32R_OPERAND_SIMM8 :
+ fields->f_simm8 = value;
+ break;
+ case M32R_OPERAND_SIMM16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_UIMM4 :
+ fields->f_uimm4 = value;
+ break;
+ case M32R_OPERAND_UIMM5 :
+ fields->f_uimm5 = value;
+ break;
+ case M32R_OPERAND_UIMM16 :
+ fields->f_uimm16 = value;
+ break;
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_IMM1 :
+ fields->f_imm1 = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCD :
+ fields->f_accd = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACCS :
+ fields->f_accs = value;
+ break;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ case M32R_OPERAND_ACC :
+ fields->f_acc = value;
+ break;
+/* end-sanitize-m32rx */
+ case M32R_OPERAND_HASH :
+ fields->f_nil = value;
+ break;
+ case M32R_OPERAND_HI16 :
+ fields->f_hi16 = value;
+ break;
+ case M32R_OPERAND_SLO16 :
+ fields->f_simm16 = value;
+ break;
+ case M32R_OPERAND_ULO16 :
+ fields->f_uimm16 = value;
+ break;
+ case M32R_OPERAND_UIMM24 :
+ fields->f_uimm24 = value;
+ break;
+ case M32R_OPERAND_DISP8 :
+ fields->f_disp8 = value;
+ break;
+ case M32R_OPERAND_DISP16 :
+ fields->f_disp16 = value;
+ break;
+ case M32R_OPERAND_DISP24 :
+ fields->f_disp24 = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+