Thu May 7 13:20:56 1998 Anders Blomdell <anders.blomdell@control.lth.se>

[deliverable/binutils-gdb.git] / opcodes / m32r-opc.h

diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 79b141507ac4f6620fd5a153977c3611ae2a6799..3fd2f52b9a898a08f87a095606446fdb2725fcf4 100644 (file)
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -28,7 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_ARCH m32r
 
 /* Given symbol S, return m32r_cgen_<s>.  */
-#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
+#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
 
 /* Selected cpu families.  */
 #define HAVE_CPU_M32R
@@ -75,6 +75,12 @@ typedef enum cgen_operand_type {
   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
+/* start-sanitize-m32rx */
+ , M32R_OPERAND_IMM1
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_OPERAND_ACCD
+/* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
  , M32R_OPERAND_ACCS
 /* end-sanitize-m32rx */
@@ -83,11 +89,7 @@ typedef enum cgen_operand_type {
 /* end-sanitize-m32rx */
  , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
  , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
- , M32R_OPERAND_ACCUM
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ABORT_PARALLEL_EXECUTION
-/* end-sanitize-m32rx */
- , M32R_OPERAND_MAX
+ , M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Non-boolean attributes.  */
@@ -111,9 +113,12 @@ typedef enum pipe_attr {
 /* Number of architecture variants.  */
 #define MAX_MACHS ((int) MACH_MAX)
 
-/* Number of operands.  */
+/* Number of operands types.  */
 #define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
 
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 8
+
 /* Operand and instruction attribute indices.  */
 
 /* Enum declaration for cgen_operand attrs.  */
@@ -124,7 +129,7 @@ typedef enum cgen_operand_attr {
 } CGEN_OPERAND_ATTR;
 
 /* Number of non-boolean elements in cgen_operand.  */
-#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
@@ -137,7 +142,7 @@ typedef enum cgen_insn_attr {
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn.  */
-#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 
 /* Insn types are used by the simulator.  */
 /* Enum declaration for m32r instruction types.  */
@@ -187,6 +192,9 @@ typedef enum cgen_insn_type {
  , M32R_INSN_CMPZ
 /* end-sanitize-m32rx */
  , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
+/* start-sanitize-m32rx */
+ , M32R_INSN_DIVH
+/* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
  , M32R_INSN_JC
 /* end-sanitize-m32rx */
@@ -240,11 +248,23 @@ typedef enum cgen_insn_type {
  , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
  , M32R_INSN_RAC
 /* start-sanitize-m32rx */
- , M32R_INSN_RAC_A
+ , M32R_INSN_RAC_D
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_INSN_RAC_DS
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_INSN_RAC_DSI
 /* end-sanitize-m32rx */
  , M32R_INSN_RACH
 /* start-sanitize-m32rx */
- , M32R_INSN_RACH_A
+ , M32R_INSN_RACH_D
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_INSN_RACH_DS
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_INSN_RACH_DSI
 /* end-sanitize-m32rx */
  , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
  , M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
@@ -281,7 +301,7 @@ typedef enum cgen_insn_type {
  , M32R_INSN_MULWU1
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
- , M32R_INSN_MACHL1
+ , M32R_INSN_MACLH1
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
  , M32R_INSN_SC
@@ -301,7 +321,7 @@ typedef enum cgen_insn_type {
 #include "opcode/cgen.h"
 
 /* This struct records data prior to insertion or after extraction.  */
-typedef struct cgen_fields 
+struct cgen_fields 
 {
   long f_nil;
   long f_op1;
@@ -331,14 +351,46 @@ typedef struct cgen_fields
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
   long f_accs;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+  long f_accd;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+  long f_bits67;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+  long f_bit14;
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+  long f_imm1;
 /* end-sanitize-m32rx */
   int length;
-} CGEN_FIELDS;
+};
 
 /* Attributes.  */
 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 
+/* Enum declaration for m32r hardware types.  */
+typedef enum hw_type {
+  HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
+ , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
+ , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
+/* start-sanitize-m32rx */
+ , HW_H_ACCUMS
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , HW_H_ABORT
+/* end-sanitize-m32rx */
+ , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
+ , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
+ , HW_MAX
+} HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Hardware decls.  */
+
 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 /* start-sanitize-m32rx */
@@ -368,6 +420,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 (X (buffer) | \
  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
+  : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 
 /* -- */