TX19 uses igen by default.

[deliverable/binutils-gdb.git] / opcodes / m32r-opc.h

diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 90c913c74d4e8e99510f5e81c0ed53289c930726..3fd2f52b9a898a08f87a095606446fdb2725fcf4 100644 (file)
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -28,7 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_ARCH m32r
 
 /* Given symbol S, return m32r_cgen_<s>.  */
-#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
+#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
 
 /* Selected cpu families.  */
 #define HAVE_CPU_M32R
@@ -89,11 +89,7 @@ typedef enum cgen_operand_type {
 /* end-sanitize-m32rx */
  , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
  , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
- , M32R_OPERAND_ACCUM
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ABORT_PARALLEL_EXECUTION
-/* end-sanitize-m32rx */
- , M32R_OPERAND_MAX
+ , M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Non-boolean attributes.  */
@@ -107,16 +103,6 @@ typedef enum mach_attr {
  , MACH_MAX
 } MACH_ATTR;
 
-/* Enum declaration for instructions which modify the link register as a side effect.  */
-typedef enum write_lr_attr {
-  WRITE_LR_NO, WRITE_LR_YES
-} WRITE_LR_ATTR;
-
-/* Enum declaration for instructions which modify their source register as a side effect.  */
-typedef enum write_src_attr {
-  WRITE_SRC_NO, WRITE_SRC_YES
-} WRITE_SRC_ATTR;
-
 /* start-sanitize-m32rx */
 /* Enum declaration for parallel execution pipeline selection.  */
 typedef enum pipe_attr {
@@ -143,7 +129,7 @@ typedef enum cgen_operand_attr {
 } CGEN_OPERAND_ATTR;
 
 /* Number of non-boolean elements in cgen_operand.  */
-#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
@@ -151,13 +137,12 @@ typedef enum cgen_insn_attr {
 /* start-sanitize-m32rx */
  , CGEN_INSN_PIPE
 /* end-sanitize-m32rx */
- , CGEN_INSN_WRITE_LR, CGEN_INSN_WRITE_SRC, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI
- , CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE
- , CGEN_INSN_UNCOND_CTI
+ , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
+ , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn.  */
-#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 
 /* Insn types are used by the simulator.  */
 /* Enum declaration for m32r instruction types.  */
@@ -398,7 +383,8 @@ typedef enum hw_type {
  , HW_H_ABORT
 /* end-sanitize-m32rx */
  , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
- , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_MAX
+ , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
+ , HW_MAX
 } HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)