{"jle", one(0067400), one(0177400), "Bg", m68000up | mcf5200 },
{"bchg", one(0000500), one(0170700), "Dd$s", m68000up | mcf5200 },
-{"bchg", one(0004100), one(0177700), "#b$s", m68000up | mcf5200 },
+{"bchg", one(0004100), one(0177700), "#b$s", m68000up },
+{"bchg", one(0004100), one(0177700), "#bqs", mcf5200 },
-{"bclr", one(0000600), one(0170700), "Dd$s", m68000up | mcf5200 },
-{"bclr", one(0004200), one(0177700), "#b$s", m68000up | mcf5200 },
+{"bclr", one(0000600), one(0170700), "Dd$s", m68000up },
+{"bclr", one(0000600), one(0170700), "Ddvs", mcf5200 },
+{"bclr", one(0004200), one(0177700), "#b$s", m68000up },
+{"bclr", one(0004200), one(0177700), "#bqs", mcf5200 },
{"bfchg", two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
{"bfclr", two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 },
{"bras", one(0060000), one(0177400), "BB", m68000up | mcf5200 },
-{"bset", one(0000700), one(0170700), "Dd$s", m68000up | mcf5200 },
-{"bset", one(0004300), one(0177700), "#b$s", m68000up | mcf5200 },
+{"bset", one(0000700), one(0170700), "Dd$s", m68000up },
+{"bset", one(0000700), one(0170700), "Ddvs", mcf5200 },
+{"bset", one(0004300), one(0177700), "#b$s", m68000up },
+{"bset", one(0004300), one(0177700), "#bqs", mcf5200 },
{"bsrw", one(0060400), one(0177777), "BW", m68000up | mcf5200 },
{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 },
{"bsrs", one(0060400), one(0177400), "BB", m68000up | mcf5200 },
{"btst", one(0000400), one(0170700), "Dd@s", m68000up | mcf5200 },
-{"btst", one(0004000), one(0177700), "#b@s", m68000up | mcf5200 },
+{"btst", one(0004000), one(0177700), "#b@s", m68000up },
+{"btst", one(0004000), one(0177700), "#bqs", mcf5200 },
{"callm", one(0003300), one(0177700), "#b!s", m68020 },
{"dbvs", one(0054710), one(0177770), "DsBw", m68000up },
{"divsw", one(0100700), one(0170700), ";wDd", m68000up },
+/* start-sanitize-coldfire */
+{"divsw", one(0100700), one(0170700), ";wDd", m68000up|mcfdiv },
+/* end-sanitize-coldfire */
{"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
{"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
+/* start-sanitize-coldfire */
+{"divsl", two(0046100,0004000),two(0177700,0107770),"DsDD", mcfdiv },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"asDD", mcfdiv },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"+sDD", mcfdiv },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"-sDD", mcfdiv },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"dsDD", mcfdiv },
+/* end-sanitize-coldfire */
{"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
{"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
{"divuw", one(0100300), one(0170700), ";wDd", m68000up },
+/* start-sanitize-coldfire */
+{"divuw", one(0100300), one(0170700), ";wDd", m68000up|mcfdiv },
+/* end-sanitize-coldfire */
{"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
{"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
+/* start-sanitize-coldfire */
+{"divul", two(0046100,0000000),two(0177700,0107770),"DsDD", mcfdiv },
+{"divul", two(0046100,0000000),two(0177700,0107770),"asDD", mcfdiv },
+{"divul", two(0046100,0000000),two(0177700,0107770),"+sDD", mcfdiv },
+{"divul", two(0046100,0000000),two(0177700,0107770),"-sDD", mcfdiv },
+{"divul", two(0046100,0000000),two(0177700,0107770),"dsDD", mcfdiv },
+/* end-sanitize-coldfire */
{"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
{"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
{"lea", one(0040700), one(0170700), "!sAd", m68000up | mcf5200 },
-{"lpstop", two(0174000,0000700), two(0177777,0177777), "", cpu32|m68060 },
+{"lpstop", two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 },
{"linkw", one(0047120), one(0177770), "As#w", m68000up | mcf5200 },
{"linkl", one(0044010), one(0177770), "As#l", m68020up | cpu32 },
{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf5200 },
{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf5200 },
+/* NOTE: The mcf5200 family programmer's reference manual does not
+ indicate the byte form of the movea instruction is invalid (as it
+ is on 68000 family cpus). However, experiments on the 5202 yeild
+ unexpected results. The value is copied, but it is not sign extended
+ (as is done with movea.w) and the top three bytes in the address
+ register are not disturbed. I don't know if this is the intended
+ behavior --- it could be a hole in instruction decoding (Motorola
+ decided not to trap all invalid instructions for performance reasons)
+ --- but I suspect that it is not.
+
+ I reported this to Motorola ISD Technical Communications Support,
+ which replied that other coldfire assemblers reject movea.b. For
+ this reason I've decided to not allow moveab.
+
+ jtc@cygnus.com - 97/01/24
+ */
+
{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf5200 },
{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf5200 },
{"moveml", one(0046300), one(0177700), "<sLw", m68000up },
{"moveml", one(0046300), one(0177700), "<s#w", m68000up },
/* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns */
-{"moveml", one(0044320), one(0177700), "Lwas", mcf5200 },
-{"moveml", one(0044320), one(0177700), "#was", mcf5200 },
-{"moveml", one(0044350), one(0177700), "Lwds", mcf5200 },
-{"moveml", one(0044350), one(0177700), "#wds", mcf5200 },
-{"moveml", one(0046320), one(0177700), "asLw", mcf5200 },
-{"moveml", one(0046320), one(0177700), "as#w", mcf5200 },
-{"moveml", one(0046350), one(0177700), "dsLw", mcf5200 },
+{"moveml", one(0044320), one(0177770), "Lwas", mcf5200 },
+{"moveml", one(0044320), one(0177770), "#was", mcf5200 },
+{"moveml", one(0044350), one(0177770), "Lwds", mcf5200 },
+{"moveml", one(0044350), one(0177770), "#wds", mcf5200 },
+{"moveml", one(0046320), one(0177770), "asLw", mcf5200 },
+{"moveml", one(0046320), one(0177770), "as#w", mcf5200 },
+{"moveml", one(0046350), one(0177770), "dsLw", mcf5200 },
{"moveml", one(0046350), one(0177770), "ds#w", mcf5200 },
{"movepw", one(0000410), one(0170770), "dsDd", m68000up },
{"movew", one(0041300), one(0177770), "CsDs", mcf5200 },
{"movew", one(0042300), one(0177700), ";wCd", m68000up },
{"movew", one(0042300), one(0177700), "DsCd", mcf5200 },
-{"movew", one(0042300), one(0177700), "#wCd", mcf5200 },
+{"movew", one(0042374), one(0177700), "#wCd", mcf5200 },
{"movew", one(0043300), one(0177700), ";wSd", m68000up },
{"movew", one(0043300), one(0177700), "DsSd", mcf5200 },
-{"movew", one(0043300), one(0177700), "#wSd", mcf5200 },
+{"movew", one(0043374), one(0177700), "#wSd", mcf5200 },
{"movel", one(0070000), one(0170400), "MsDd", m68000up | mcf5200 },
{"movel", one(0020000), one(0170000), "*l%d", m68000up },
{"move16", one(0xf618), one(0xfff8), "_Las", m68040up },
{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf5200 },
-{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 },
+{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
+{"mulsl", two(0046000,004000), two(0177700,0107770), "DsD1", mcf5200 },
+{"mulsl", two(0046000,004000), two(0177700,0107770), "asD1", mcf5200 },
+{"mulsl", two(0046000,004000), two(0177700,0107770), "+sD1", mcf5200 },
+{"mulsl", two(0046000,004000), two(0177700,0107770), "-sD1", mcf5200 },
+{"mulsl", two(0046000,004000), two(0177700,0107770), "dsD1", mcf5200 },
{"mulsl", two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
{"muluw", one(0140300), one(0170700), ";wDd", m68000up|mcf5200 },
-{"mulul", two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 },
+{"mulul", two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
+{"mulul", two(0046000,000000), two(0177700,0107770), "DsD1", mcf5200 },
+{"mulul", two(0046000,000000), two(0177700,0107770), "asD1", mcf5200 },
+{"mulul", two(0046000,000000), two(0177700,0107770), "+sD1", mcf5200 },
+{"mulul", two(0046000,000000), two(0177700,0107770), "-sD1", mcf5200 },
+{"mulul", two(0046000,000000), two(0177700,0107770), "dsD1", mcf5200 },
{"mulul", two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
{"nbcd", one(0044000), one(0177700), "$s", m68000up },
{"pvalid", two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 },
{"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 },
+/* start-sanitize-coldfire */
+{"remsl", two(0046100,0006000),two(0177700,0107770),"DsD3D1", mcfdiv },
+{"remsl", two(0046100,0006000),two(0177700,0107770),"asD3D1", mcfdiv },
+{"remsl", two(0046100,0006000),two(0177700,0107770),"+sD3D1", mcfdiv },
+{"remsl", two(0046100,0006000),two(0177700,0107770),"-sD3D1", mcfdiv },
+{"remsl", two(0046100,0006000),two(0177700,0107770),"dsD3D1", mcfdiv },
+
+{"remul", two(0046100,0002000),two(0177700,0107770),"DsD3D1", mcfdiv },
+{"remul", two(0046100,0002000),two(0177700,0107770),"asD3D1", mcfdiv },
+{"remul", two(0046100,0002000),two(0177700,0107770),"+sD3D1", mcfdiv },
+{"remul", two(0046100,0002000),two(0177700,0107770),"-sD3D1", mcfdiv },
+{"remul", two(0046100,0002000),two(0177700,0107770),"dsD3D1", mcfdiv },
+/* end-sanitize-coldfire */
+
{"reset", one(0047160), one(0177777), "", m68000up },
{"rolb", one(0160430), one(0170770), "QdDs", m68000up },
{"swap", one(0044100), one(0177770), "Ds", m68000up | mcf5200 },
+/* swbeg and swbegl are magic constants used on sysV68. The compiler
+ generates them before a switch table. They tell the debugger and
+ disassembler that a switch table follows. The parameter is the
+ number of elements in the table. swbeg means that the entries in
+ the table are word (2 byte) sized, and swbegl means that the
+ entries in the table are longword (4 byte) sized. */
+{"swbeg", one(0045374), one(0177777), "#w", m68000up | mcf5200 },
+{"swbegl", one(0045375), one(0177777), "#l", m68000up | mcf5200 },
+
{"tas", one(0045300), one(0177700), "$s", m68000up },
#define TBL1(name,signed,round,size) \
{name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \
- two(0177700,0107777), "`sD1", cpu32 }, \
+ two(0177700,0107777), "!sD1", cpu32 }, \
{name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \
two(0177770,0107770), "DsD3D1", cpu32 }
#define TBL(name1, name2, name3, s, r) \
{"trapv", one(0047166), one(0177777), "", m68000up },
-{"tstb", one(0045000), one(0177700), ";b", m68000up | mcf5200 },
-{"tstw", one(0045100), one(0177700), "*w", m68000up | mcf5200 },
-{"tstl", one(0045200), one(0177700), "*l", m68000up | mcf5200 },
+{"tstb", one(0045000), one(0177700), ";b", m68020up|cpu32|mcf5200 },
+{"tstb", one(0045000), one(0177700), "@b", m68000up },
+{"tstw", one(0045100), one(0177700), "*w", m68020up|cpu32|mcf5200 },
+{"tstw", one(0045100), one(0177700), "@w", m68000up },
+{"tstl", one(0045200), one(0177700), "*l", m68020up|cpu32|mcf5200 },
+{"tstl", one(0045200), one(0177700), "@l", m68000up },
{"unlk", one(0047130), one(0177770), "As", m68000up | mcf5200 },
{ "bhsb", "bccs" },
{ "bhsw", "bccw" },
{ "bhsl", "bccl" },
+ { "blo", "bcsw" },
+ { "blos", "bcss" },
+ { "blob", "bcss" },
+ { "blow", "bcsw" },
+ { "blol", "bcsl" },
{ "br", "braw", },
{ "brs", "bras", },
{ "brb", "bras", },
projects / deliverable / binutils-gdb.git / blobdiff