/* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
- Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001,
- 2002, 2005, 2007 Free Software Foundation, Inc.
+ Copyright (C) 1986-2017 Free Software Foundation, Inc.
Contributed by Data General Corporation, November 1989.
Partially derived from an earlier printcmd.c.
MA 02110-1301, USA. */
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "opcode/m88k.h"
#include "opintl.h"
#include "libiberty.h"
{0x8400bc20,"fcmpu.sxs ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
{0x8400bd20,"fcmpu.sxx ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84000820,"fcvt.sd ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84000880,"fcvt.ds ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84000820,"fcvt.ds ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84000880,"fcvt.sd ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84008880,"fcvt.ds ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x840088c0,"fcvt.dx ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84008820,"fcvt.sd ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84008840,"fcvt.sx ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84008920,"fcvt.xd ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
- {0x84008900,"fcvt.xs ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84008880,"fcvt.sd ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x840088c0,"fcvt.xd ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84008820,"fcvt.ds ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84008840,"fcvt.xs ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84008920,"fcvt.dx ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
+ {0x84008900,"fcvt.sx ",{21,5,XREG} ,{0,5,XREG} ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
{0x8400f2a0,"fdiv.ddd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
{0x8400f280,"fdiv.dds ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
\f
/* Initialize the disassembler instruction table.
-
+
Initialize the hash table and instruction table for the
disassembler. This should be called once before the first call to
disasm(). */
hashtable[hashvalue] = &hashentries[i];
}
}
-
+
/* Decode an Operand of an instruction.
-
+
This function formats and writes an operand of an instruction to
info based on the operand specification. When the `first' flag is
set this is the first operand of an instruction. Undefined operand
types cause a <dis error> message.
-
+
Parameters:
disassemble_info where the operand may be printed
OPSPEC *opptr pointer to an operand specification
UINT pc pc of instruction; used for pc-relative disp.
int first flag which if nonzero indicates the first
operand of an instruction
-
+
The operand specified is extracted from the instruction and is
written to buf in the format specified. The operand is preceded by
a comma if it is not the first operand of an instruction and it is
else
(*info->fprintf_func) (info->stream, "%x", extracted_field);
break;
-
+
case PCREL:
(*info->print_address_func)
(pc + (4 * (SEXT (inst, opptr->offset, opptr->width))),
`pc' should be the address of this instruction, it will be used to
print the target address if this is a relative jump or call the
disassembled instruction is written to `info'.
-
+
The function returns the length of this instruction in bytes. */
static int
unsigned int opcode;
const HASHTAB *entry_ptr;
int opmask;
- unsigned int class;
+ unsigned int in_class;
if (! ihashtab_initialized)
{
/* Create the appropriate mask to isolate the opcode. */
opmask = DEFMASK;
- class = instruction & DEFMASK;
- if ((class >= SFU0) && (class <= SFU7))
+ in_class = instruction & DEFMASK;
+ if ((in_class >= SFU0) && (in_class <= SFU7))
{
if (instruction < SFU1)
opmask = CTRLMASK;
else
opmask = SFUMASK;
}
- else if (class == RRR)
+ else if (in_class == RRR)
opmask = RRRMASK;
- else if (class == RRI10)
+ else if (in_class == RRI10)
opmask = RRI10MASK;
/* Isolate the opcode. */