2000-02-16 Fernando Nasser <fnasser@totem.to.cygnus.com>

[deliverable/binutils-gdb.git] / opcodes / mcore-dis.c

diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index 2c9f041d773c332cd87fcecef3d0a28088f0ad91..096cec9aec06a90e80a00c5f5c7dd382f83db3e6 100644 (file)
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -1,5 +1,5 @@
-/* Disassemble Motorolla M*Core instructions.
-   Copyright (C) 1993, 1999 Free Software Foundation, Inc.
+/* Disassemble Motorola M*Core instructions.
+   Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -57,50 +57,7 @@ static const unsigned short imsk[] =
     /* OMc */ 0xFF00,
     /* SIa */ 0xFE00,
 
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include <stdio.h>
-#define STATIC_TABLE
-#define DEFINE_TABLE
-
-#include "mcore-opc.h"
-#include "dis-asm.h"
-
-/* Mask for each mcore_opclass: */
-static const unsigned short imsk[] =
-{
-    /* O0  */ 0xFFFF,
-    /* OT  */ 0xFFFC,
-    /* O1  */ 0xFFF0,
-    /* OC  */ 0xFFE0,
-    /* O2  */ 0xFF00,
-    /* X1  */ 0xFFF0,
-    /* OI  */ 0xFE00,
-    /* OB  */ 0xFE00,
-             
-    /* OMa */ 0xFFF0,
-    /* SI  */ 0xFE00,
-    /* I7  */ 0xF800,
-    /* LS  */ 0xF000,
-    /* BR  */ 0xF800,
-    /* BL  */ 0xFF00,
-    /* LR  */ 0xF000,
-    /* LJ  */ 0xFF00,
-             
-    /* RM  */ 0xFFF0,
-    /* RQ  */ 0xFFF0,
-    /* JSR */ 0xFFF0,
-    /* JMP */ 0xFFF0,
-    /* OBRa*/ 0xFFF0,
-    /* OBRb*/ 0xFF80,
-    /* OBRc*/ 0xFF00,
-    /* OBR2*/ 0xFE00,
-             
-    /* O1R1*/ 0xFFF0,
-    /* OMb */ 0xFF80,
-    /* OMc */ 0xFF00,
-    /* SIa */ 0xFE00,
-
+  /* MULSH */ 0xFF00,    
   /* OPSR  */ 0xFFF8,   /* psrset/psrclr */
                 
     /* JC  */ 0,               /* JC,JU,JL don't appear in object */
@@ -151,7 +108,12 @@ print_insn_mcore (memaddr, info)
       return -1;
     }
 
+  if (info->endian == BFD_ENDIAN_BIG)
     inst = (ibytes[0] << 8) | ibytes[1];
+  else if (info->endian == BFD_ENDIAN_LITTLE)
+    inst = (ibytes[1] << 8) | ibytes[0];
+  else
+    abort ();
 
   /* Just a linear search of the table.  */
   for (op = mcore_table; op->name != 0; op ++)
@@ -175,6 +137,7 @@ print_insn_mcore (memaddr, info)
        case JSR: fprintf (stream, "\t%s", name); break;
        case OC:  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
        case O1R1: fprintf (stream, "\t%s, r1", name); break;
+       case MULSH:
        case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
        case X1: fprintf (stream, "\tr1, %s", name); break;
        case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
@@ -239,6 +202,10 @@ print_insn_mcore (memaddr, info)
                break;
              }
            
+           if (info->endian == BFD_ENDIAN_LITTLE)
+             val = (ibytes[3] << 24) | (ibytes[2] << 16)
+               | (ibytes[1] << 8) | (ibytes[0]);
+           else
              val = (ibytes[0] << 24) | (ibytes[1] << 16)
                | (ibytes[2] << 8) | (ibytes[3]);
            
@@ -264,6 +231,10 @@ print_insn_mcore (memaddr, info)
                break;
              }
 
+           if (info->endian == BFD_ENDIAN_LITTLE)
+             val = (ibytes[3] << 24) | (ibytes[2] << 16)
+               | (ibytes[1] << 8) | (ibytes[0]);
+           else
              val = (ibytes[0] << 24) | (ibytes[1] << 16)
                | (ibytes[2] << 8) | (ibytes[3]);
            
@@ -294,7 +265,7 @@ print_insn_mcore (memaddr, info)
            fprintf (stream, "\t%s", fields[inst & 0x7]);
          }
          break;
-
+         
        default:
          /* if the disassembler lags the instruction set */
          fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);