RISC-V: Add compressed instruction hints, and a few misc cleanups.

[deliverable/binutils-gdb.git] / opcodes / mep-asm.c

diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 89116ee8e8e004f5234205dbf6e74ab3c6e653d0..9af326bab8b084c99e4f7c213ff5b3f85938e9c4 100644 (file)
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -1,10 +1,11 @@
+/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
 /* Assembler interface for targets using CGEN. -*- C -*-
    CGEN: Cpu tools GENerator
 
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-asm.in isn't
 
-   Copyright (C) 1996-2016 Free Software Foundation, Inc.
+   Copyright (C) 1996-2017 Free Software Foundation, Inc.
 
    This file is part of libopcodes.