+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
- 2008 Free Software Foundation, Inc.
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
This file is part of libopcodes.
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
}
static void
-print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
+print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
if (corelength > 0)
{
int my_status = 0;
-
+
for (i = 0; i < corelength; i++ )
insnbuf[i] = buf[i];
cd->isas = & MEP_CORE_ISA;
-
+
my_status = print_insn (cd, pc, info, insnbuf, corelength);
if (my_status != corelength)
{
/* Print the + to indicate that the following copro insn is */
/* part of a vliw group. */
if (copro1length > 0)
- (*info->fprintf_func) (info->stream, " + ");
+ (*info->fprintf_func) (info->stream, " + ");
}
/* Now all that is left to be processed is the coprocessor insns
if (copro1length > 0)
{
int my_status = 0;
-
+
for (i = corelength; i < corelength + copro1length; i++ )
insnbuf[i - corelength] = buf[i];
break;
case 8:
cd->isas = & MEP_COP64_ISA;
- break;
+ break;
default:
/* Shouldn't be anything but 16,32,48,64. */
break;
for (i = corelength + copro1length; i < 64; i++)
insnbuf[i - (corelength + copro1length)] = buf[i];
-
+
switch (copro2length)
{
case 2:
cd->isas = 1 << ISA_EXT_COP1_48;
break;
case 8:
- cd->isas = 1 << ISA_EXT_COP1_64;
+ cd->isas = 1 << ISA_EXT_COP1_64;
break;
default:
/* Shouldn't be anything but 16,32,48,64. */
return status;
}
-/* The two functions mep_examine_vliw[32,64]_insns are used find out
- which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
- with 32 bit copro, etc.) is present. Later on, when internally
- parallel coprocessors are handled, only these functions should
- need to be changed.
+/* The two functions mep_examine_vliw[32,64]_insns are used find out
+ which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
+ with 32 bit copro, etc.) is present. Later on, when internally
+ parallel coprocessors are handled, only these functions should
+ need to be changed.
+
+ At this time only the following combinations are supported:
- At this time only the following combinations are supported:
-
VLIW32 Mode:
16 bit core insn (core) and 16 bit coprocessor insn (cop1)
32 bit core insn (core)
32 bit coprocessor insn (cop1)
Note: As of this time, I do not believe we have enough information
to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
- no 16 bit coprocessor insns have been specified.
+ no 16 bit coprocessor insns have been specified.
VLIW64 Mode:
16 bit core insn (core) and 48 bit coprocessor insn (cop1)
32 bit core insn (core) and 32 bit coprocessor insn (cop1)
64 bit coprocessor insn (cop1)
-
+
The framework for an internally parallel coprocessor is also
- present (2nd coprocessor insn is cop2), but at this time it
+ present (2nd coprocessor insn is cop2), but at this time it
is not used. This only appears to be valid in VLIW64 mode. */
static int
int corebuflength;
int cop1buflength;
int cop2buflength;
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
char indicator16[1];
- char indicatorcop32[2];
+ char indicatorcop32[2];
/* At this time we're not supporting internally parallel coprocessors,
so cop2buflength will always be 0. */
{
int status;
int buflength;
- int cop2buflength;
bfd_byte buf[8];
bfd_byte insn[8];
int e;
- /* At this time we're not supporting internally parallel
- coprocessors, so cop2buflength will always be 0. */
- cop2buflength = 0;
-
/* Read in 64 bits. */
buflength = 8; /* VLIW insn spans 8 bytes. */
status = (*info->read_memory_func) (pc, buf, buflength, info);
else
e = 0;
- if ((buf[0^e] & 0xf0) != 0xf0)
+ if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)
{
/* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
/* V1 [-----core-----][--------p0s-------][------------p1------------] */
case MEP_OPERAND_IVC_X_6_3 :
print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
case MEP_OPERAND_IVC2CCRN :
- print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_IVC2CRN :
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
case MEP_OPERAND_SIMM8P0 :
print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
+ case MEP_OPERAND_SIMM8P20 :
+ print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
case MEP_OPERAND_SIMM8P4 :
print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
}
}
-cgen_print_fn * const mep_cgen_print_handlers[] =
+cgen_print_fn * const mep_cgen_print_handlers[] =
{
print_insn_normal,
};
{
disassemble_info *info = (disassemble_info *) dis_info;
-#ifdef CGEN_PRINT_NORMAL
- CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
-#endif
-
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
{
disassemble_info *info = (disassemble_info *) dis_info;
-#ifdef CGEN_PRINT_ADDRESS
- CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
-#endif
-
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* Nothing to do. */
int length;
unsigned long insn_value_cropped;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! mep_cgen_insn_supported (cd, insn))
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
-
+
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)