Remove unnecessary @w{} in gdb.texinfo

[deliverable/binutils-gdb.git] / opcodes / micromips-opc.c

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 33dd57e545e6d9c525c042941670eb6b453cff5f..c5733d43acffc2669b86c39694e0d38ef398840f 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -309,9 +309,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"addu",               "md,me,ml",         0x0400,     0xfc01, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"addu",               "d,v,t",        0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"addu",               "t,r,I",        0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1,             0,      0 },
-/* We have no flag to mark the read from "y", so we use NODS to disable
-   delay slot scheduling of ALNV.PS altogether.  */
-{"alnv.ps",            "D,V,T,y",      0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|NODS|FP_D, 0,            I1,             0,      0 },
+{"alnv.ps",            "D,V,T,y",      0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I1,             0,      0 },
 {"and",                        "mf,mt,mg",         0x4480,     0xffc0, MOD_1|RD_3,             0,              I1,             0,      0 },
 {"and",                        "mf,mg,mx",         0x4480,     0xffc0, MOD_1|RD_2,             0,              I1,             0,      0 },
 {"and",                        "d,v,t",        0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
@@ -544,8 +542,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"dclo",               "t,s",          0x58004b3c, 0xfc00ffff, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dclz",               "t,s",          0x58005b3c, 0xfc00ffff, WR_1|RD_2,              0,              I3,             0,      0 },
 {"deret",              "",             0x0000e37c, 0xffffffff, NODS,                   0,              I1,             0,      0 },
-{"dext",               "t,r,I,+I",     0,    (int) M_DEXT,     INSN_MACRO,             0,              I3,             0,      0 },
-{"dext",               "t,r,+A,+C",    0x5800002c, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
+{"dext",               "t,r,+A,+H",    0x5800002c, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
+{"dext",               "t,r,+A,+G",    0x58000024, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dextm */
+{"dext",               "t,r,+E,+H",    0x58000014, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dextu */
 {"dextm",              "t,r,+A,+G",    0x58000024, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dextu",              "t,r,+E,+H",    0x58000014, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
 /* For ddiv, see the comments about div.  */
@@ -560,8 +559,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"ddivu",              "d,v,I",        0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3,             0,      0 },
 {"di",                 "",             0x0000477c, 0xffffffff, RD_C0,                  0,              I1,             0,      0 },
 {"di",                 "s",            0x0000477c, 0xffe0ffff, WR_1|RD_C0,             0,              I1,             0,      0 },
-{"dins",               "t,r,I,+I",     0,    (int) M_DINS,     INSN_MACRO,             0,              I3,             0,      0 },
 {"dins",               "t,r,+A,+B",    0x5800000c, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
+{"dins",               "t,r,+A,+F",    0x58000004, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dinsm */
+{"dins",               "t,r,+E,+F",    0x58000034, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dinsu */
 {"dinsm",              "t,r,+A,+F",    0x58000004, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dinsu",              "t,r,+E,+F",    0x58000034, 0xfc00003f, WR_1|RD_2,              0,              I3,             0,      0 },
 /* The MIPS assembler treats the div opcode with two operands as
@@ -586,12 +586,12 @@ const struct mips_opcode micromips_opcodes[] =
 {"dli",                        "t,I",          0,    (int) M_DLI,      INSN_MACRO,             0,              I3,             0,      0 },
 {"dmfc0",              "t,G",          0x580000fc, 0xfc00ffff, WR_1|RD_C0,             0,              I3,             0,      0 },
 {"dmfc0",              "t,G,H",        0x580000fc, 0xfc00c7ff, WR_1|RD_C0,             0,              I3,             0,      0 },
-{"dmfgc0",             "t,G",          0x580000e7, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
-{"dmfgc0",             "t,G,H",        0x580000e7, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
+{"dmfgc0",             "t,G",          0x580004fc, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
+{"dmfgc0",             "t,G,H",        0x580004fc, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
 {"dmtc0",              "t,G",          0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              I3,             0,      0 },
 {"dmtc0",              "t,G,H",        0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              I3,             0,      0 },
-{"dmtgc0",             "t,G",          0x580002e7, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
-{"dmtgc0",             "t,G,H",        0x580002e7, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
+{"dmtgc0",             "t,G",          0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
+{"dmtgc0",             "t,G,H",        0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
 {"dmfc1",              "t,S",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I3,             0,      0 },
 {"dmfc1",              "t,G",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I3,             0,      0 },
 {"dmtc1",              "t,G",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S,         0,              I3,             0,      0 },