gas: run the hwcaps-bump tests with 64-bit sparc objects only.

[deliverable/binutils-gdb.git] / opcodes / micromips-opc.c

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index e182f470d087cb276e38ce0702a822652a1af31b..dbbb792ba2cbfd16a26c3d58426598fe02d940a7 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -305,9 +305,11 @@ const struct mips_opcode micromips_opcodes[] =
 {"b",                  "mD",               0xcc00,     0xfc00, UBD,                    0,              I1,             0,      0 },
 {"b",                  "p",            0x94000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 }, /* beq 0, 0 */
 {"b",                  "p",            0x40400000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 }, /* bgez 0 */
+/* BC is next to B so that we easily find it when converting a normal
+   branch to a compact one.  */
+{"bc",                 "p",            0x40e00000, 0xffff0000, NODS,                   INSN2_ALIAS|UBR,  I1,           0,      0 }, /* beqzc 0 */
 {"bal",                        "p",            0x40600000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS|BD32, I1,           0,      0 }, /* bgezal 0 */
 {"bals",               "p",            0x42600000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS|BD16, I1,           0,      0 }, /* bgezals 0 */
-{"bc",                 "p",            0x40e00000, 0xffff0000, NODS,                   INSN2_ALIAS|UBR,  I1,           0,      0 }, /* beqzc 0 */
 {"abs",                        "d,v",          0,    (int) M_ABS,      INSN_MACRO,             0,              I1,             0,      0 },
 {"abs.d",              "T,V",          0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D,         0,              I1,             0,      0 },
 {"abs.s",              "T,V",          0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
@@ -366,12 +368,14 @@ const struct mips_opcode micromips_opcodes[] =
 {"bc2tl",              "N,p",          0,    (int) M_BC2TL,    INSN_MACRO,             0,              I1,             0,      0 },
 {"beqz",               "md,mE",            0x8c00,     0xfc00, RD_1|CBD,               0,              I1,             0,      0 },
 {"beqz",               "s,p",          0x94000000, 0xffe00000, RD_1|CBD,               0,              I1,             0,      0 },
-{"beqzc",              "s,p",          0x40e00000, 0xffe00000, RD_1|NODS,              CBR,            I1,             0,      0 },
 {"beqzl",              "s,p",          0,    (int) M_BEQL,     INSN_MACRO,             0,              I1,             0,      0 },
 {"beq",                        "md,mz,mE",         0x8c00,     0xfc00, RD_1|CBD,               0,              I1,             0,      0 }, /* beqz */
 {"beq",                        "mz,md,mE",         0x8c00,     0xfc00, RD_2|CBD,               0,              I1,             0,      0 }, /* beqz */
 {"beq",                        "s,t,p",        0x94000000, 0xfc000000, RD_1|RD_2|CBD,          0,              I1,             0,      0 },
 {"beq",                        "s,I,p",        0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1,             0,      0 },
+/* BEQZC is next to BEQ so that we easily find it when converting a normal
+   branch to a compact one.  */
+{"beqzc",              "s,p",          0x40e00000, 0xffe00000, RD_1|NODS,              CBR,            I1,             0,      0 },
 {"beql",               "s,t,p",        0,    (int) M_BEQL,     INSN_MACRO,             0,              I1,             0,      0 },
 {"beql",               "s,I,p",        0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"bge",                        "s,t,p",        0,    (int) M_BGE,      INSN_MACRO,             0,              I1,             0,      0 },
@@ -422,12 +426,14 @@ const struct mips_opcode micromips_opcodes[] =
 {"bltzall",            "s,p",          0,    (int) M_BLTZALL,  INSN_MACRO,             0,              I1,             0,      0 },
 {"bnez",               "md,mE",            0xac00,     0xfc00, RD_1|CBD,               0,              I1,             0,      0 },
 {"bnez",               "s,p",          0xb4000000, 0xffe00000, RD_1|CBD,               0,              I1,             0,      0 },
-{"bnezc",              "s,p",          0x40a00000, 0xffe00000, RD_1|NODS,              CBR,            I1,             0,      0 },
 {"bnezl",              "s,p",          0,    (int) M_BNEL,     INSN_MACRO,             0,              I1,             0,      0 },
 {"bne",                        "md,mz,mE",         0xac00,     0xfc00, RD_1|CBD,               0,              I1,             0,      0 }, /* bnez */
 {"bne",                        "mz,md,mE",         0xac00,     0xfc00, RD_2|CBD,               0,              I1,             0,      0 }, /* bnez */
 {"bne",                        "s,t,p",        0xb4000000, 0xfc000000, RD_1|RD_2|CBD,          0,              I1,             0,      0 },
 {"bne",                        "s,I,p",        0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1,             0,      0 },
+/* BNEZC is next to BNE so that we easily find it when converting a normal
+   branch to a compact one.  */
+{"bnezc",              "s,p",          0x40a00000, 0xffe00000, RD_1|NODS,              CBR,            I1,             0,      0 },
 {"bnel",               "s,t,p",        0,    (int) M_BNEL,     INSN_MACRO,             0,              I1,             0,      0 },
 {"bnel",               "s,I,p",        0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"break",              "",                 0x4680,     0xffff, TRAP,                   0,              I1,             0,      0 },
@@ -697,10 +703,6 @@ const struct mips_opcode micromips_opcodes[] =
 /* This macro is after the real instruction so that it only matches with
    -minsn32.  */
 {"jraddiusp",          "mP",           0,   (int) M_JRADDIUSP, INSN_MACRO,             0,              I1,             0,      0 },
-{"jrc",                        "mj",               0x45a0,     0xffe0, RD_1|NODS,              UBR,            I1,             0,      0 },
-/* This macro is after the real instruction so that it only matches with
-   -minsn32.  */
-{"jrc",                        "s",            0,    (int) M_JRC,      INSN_MACRO,             0,              I1,             0,      0 },
 {"jr.hb",              "s",            0x00001f3c, 0xffe0ffff, RD_1|UBD,               BD32,           I1,             0,      0 }, /* jalr.hb */
 {"jrs.hb",             "s",            0x00005f3c, 0xffe0ffff, RD_1|UBD,               BD16,           I1,             0,      0 }, /* jalrs.hb */
 {"j",                  "mj",               0x4580,     0xffe0, RD_1|UBD,               0,              I1,             0,      0 }, /* jr */
@@ -712,6 +714,12 @@ const struct mips_opcode micromips_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"j",                  "a",            0xd4000000, 0xfc000000, UBD,                    0,              I1,             0,      0 },
+/* JRC is close to JR and J so that we easily find it when converting
+   a normal jump to a compact one.  */
+{"jrc",                        "mj",               0x45a0,     0xffe0, RD_1|NODS,              UBR,            I1,             0,      0 },
+/* This macro is after the real instruction so that it only matches with
+   -minsn32.  */
+{"jrc",                        "s",            0,    (int) M_JRC,      INSN_MACRO,             0,              I1,             0,      0 },
 {"jalr",               "mj",               0x45c0,     0xffe0, RD_1|WR_31|UBD,         BD32,           I1,             0,      0 },
 {"jalr",               "my,mj",            0x45c0,     0xffe0, RD_2|WR_31|UBD,         BD32,           I1,             0,      0 },
 {"jalr",               "s",            0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD,         BD32,           I1,             0,      0 },