Replace some $ARCH_{get,set}_pc with linux_{get,set}_pc_32bit

[deliverable/binutils-gdb.git] / opcodes / micromips-opc.c

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 66c5418a3cf2139f9b7e9e8e8321087cd204a336..e182f470d087cb276e38ce0702a822652a1af31b 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -1,5 +1,5 @@
 /* micromips-opc.c.  microMIPS opcode table.
-   Copyright (C) 2008-2015 Free Software Foundation, Inc.
+   Copyright (C) 2008-2016 Free Software Foundation, Inc.
    Contributed by Chao-ying Fu, MIPS Technologies, Inc.
 
    This file is part of the GNU opcodes library.
@@ -299,16 +299,15 @@ const struct mips_opcode micromips_opcodes[] =
 {"li",                 "t,I",          0,    (int) M_LI,       INSN_MACRO,             0,              I1,             0,      0 },
 {"move",               "d,s",          0,    (int) M_MOVE,     INSN_MACRO,             0,              I1,             0,      0 },
 {"move",               "mp,mj",            0x0c00,     0xfc00, WR_1|RD_2,              0,              I1,             0,      0 },
+{"move",               "d,s",          0x00000290, 0xffe007ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 }, /* or */
 {"move",               "d,s",          0x58000150, 0xffe007ff, WR_1|RD_2,              INSN2_ALIAS,    I3,             0,      0 }, /* daddu */
 {"move",               "d,s",          0x00000150, 0xffe007ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 }, /* addu */
-{"move",               "d,s",          0x00000290, 0xffe007ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 }, /* or */
 {"b",                  "mD",               0xcc00,     0xfc00, UBD,                    0,              I1,             0,      0 },
 {"b",                  "p",            0x94000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 }, /* beq 0, 0 */
 {"b",                  "p",            0x40400000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 }, /* bgez 0 */
 {"bal",                        "p",            0x40600000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS|BD32, I1,           0,      0 }, /* bgezal 0 */
 {"bals",               "p",            0x42600000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS|BD16, I1,           0,      0 }, /* bgezals 0 */
 {"bc",                 "p",            0x40e00000, 0xffff0000, NODS,                   INSN2_ALIAS|UBR,  I1,           0,      0 }, /* beqzc 0 */
-
 {"abs",                        "d,v",          0,    (int) M_ABS,      INSN_MACRO,             0,              I1,             0,      0 },
 {"abs.d",              "T,V",          0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D,         0,              I1,             0,      0 },
 {"abs.s",              "T,V",          0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },