reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
break;
+ case 'U':
+ {
+ /* First check for both rd and rt being equal. */
+ int reg = (l >> OP_SH_RD) & OP_MASK_RD;
+ if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[reg]);
+ else
+ {
+ /* If one is zero use the other. */
+ if (reg == 0)
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[reg]);
+ else /* Bogus, result depends on processor. */
+ (*info->fprintf_func) (info->stream, "$%s or $%s",
+ reg_names[reg],
+ reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ }
+ }
+ break;
+
case 'z':
(*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
break;
(l >> OP_SH_CODE) & OP_MASK_CODE);
break;
-
case 'q':
(*info->fprintf_func) (info->stream, "0x%x",
(l >> OP_SH_CODE2) & OP_MASK_CODE2);
case 'B':
(*info->fprintf_func) (info->stream, "0x%x",
- (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
+ (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ break;
+
+ case 'J':
+ (*info->fprintf_func) (info->stream, "0x%x",
+ (l >> OP_SH_CODE19) & OP_MASK_CODE19);
break;
case 'S':
(l >> OP_SH_FS) & OP_MASK_FS);
break;
-
case 'T':
case 'W':
(*info->fprintf_func) (info->stream, "$f%d",
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
break;
+ case 'H':
+ (*info->fprintf_func) (info->stream, "%d",
+ (l >> OP_SH_SEL) & OP_MASK_SEL);
+ break;
default:
/* xgettext:c-format */
int *isa;
int *cputype;
{
- int target_processor = 0;
- int mips_isa = 0;
+ int target_processor = CPU_UNKNOWN;
+ int mips_isa = ISA_UNKNOWN;
/* Use standard MIPS register names by default. */
reg_names = std_reg_names;
switch (mach)
{
- case bfd_mach_mips3000:
- target_processor = 3000;
- mips_isa = 1;
- break;
- case bfd_mach_mips3900:
- target_processor = 3900;
- mips_isa = 1;
- break;
- case bfd_mach_mips4000:
- target_processor = 4000;
- mips_isa = 3;
- break;
- case bfd_mach_mips4010:
- target_processor = 4010;
- mips_isa = 2;
- break;
- case bfd_mach_mips4100:
- target_processor = 4100;
- mips_isa = 3;
- break;
- case bfd_mach_mips4111:
- target_processor = 4100;
- mips_isa = 3;
- break;
- case bfd_mach_mips4300:
- target_processor = 4300;
- mips_isa = 3;
- break;
- case bfd_mach_mips4400:
- target_processor = 4400;
- mips_isa = 3;
- break;
- case bfd_mach_mips4600:
- target_processor = 4600;
- mips_isa = 3;
- break;
- case bfd_mach_mips4650:
- target_processor = 4650;
- mips_isa = 3;
- break;
- case bfd_mach_mips5000:
- target_processor = 5000;
- mips_isa = 4;
- break;
- case bfd_mach_mips6000:
- target_processor = 6000;
- mips_isa = 2;
- break;
- case bfd_mach_mips8000:
- target_processor = 8000;
- mips_isa = 4;
- break;
- case bfd_mach_mips10000:
- target_processor = 10000;
- mips_isa = 4;
- break;
- case bfd_mach_mips16:
- target_processor = 16;
- mips_isa = 3;
- break;
- default:
- target_processor = 3000;
- mips_isa = 3;
- break;
-
+ case bfd_mach_mips3000:
+ target_processor = CPU_R3000;
+ mips_isa = ISA_MIPS1;
+ break;
+ case bfd_mach_mips3900:
+ target_processor = CPU_R3900;
+ mips_isa = ISA_MIPS1;
+ break;
+ case bfd_mach_mips4000:
+ target_processor = CPU_R4000;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips4010:
+ target_processor = CPU_R4010;
+ mips_isa = ISA_MIPS2;
+ break;
+ case bfd_mach_mips4100:
+ target_processor = CPU_VR4100;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips4111:
+ target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips4300:
+ target_processor = CPU_R4300;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips4400:
+ target_processor = CPU_R4400;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips4600:
+ target_processor = CPU_R4600;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips4650:
+ target_processor = CPU_R4650;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips5000:
+ target_processor = CPU_R5000;
+ mips_isa = ISA_MIPS4;
+ break;
+ case bfd_mach_mips6000:
+ target_processor = CPU_R6000;
+ mips_isa = ISA_MIPS2;
+ break;
+ case bfd_mach_mips8000:
+ target_processor = CPU_R8000;
+ mips_isa = ISA_MIPS4;
+ break;
+ case bfd_mach_mips10000:
+ target_processor = CPU_R10000;
+ mips_isa = ISA_MIPS4;
+ break;
+ case bfd_mach_mips16:
+ target_processor = CPU_MIPS16;
+ mips_isa = ISA_MIPS3;
+ break;
+ case bfd_mach_mips32:
+ target_processor = CPU_MIPS32;
+ mips_isa = ISA_MIPS32;
+ break;
+ case bfd_mach_mips32_4k:
+ target_processor = CPU_MIPS32_4K;
+ mips_isa = ISA_MIPS32;
+ break;
+ case bfd_mach_mips5:
+ target_processor = CPU_MIPS5;
+ mips_isa = ISA_MIPS5;
+ break;
+ case bfd_mach_mips64:
+ target_processor = CPU_MIPS64;
+ mips_isa = ISA_MIPS64;
+ break;
+ default:
+ target_processor = CPU_R3000;
+ mips_isa = ISA_MIPS3;
+ break;
}
*isa = mips_isa;