/* Print mips instructions for GDB, the GNU debugger, or for objdump.
- Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012
- Free Software Foundation, Inc.
+ Copyright (C) 1989-2018 Free Software Foundation, Inc.
Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
This file is part of the GNU opcodes library.
MA 02110-1301, USA. */
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "libiberty.h"
#include "opcode/mips.h"
#include "opintl.h"
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
+static const char * const mips_cp1_names_numeric[32] =
+{
+ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
+ "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
+ "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
+ "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
+};
+
static const char * const mips_cp0_names_r3000[32] =
{
"c0_index", "c0_random", "c0_entrylo", "$3",
"c0_taglo", "c0_taghi", "c0_errorepc", "$31"
};
-static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
-{
- { 24, 2, "c0_iab" },
- { 24, 3, "c0_iabm" },
- { 24, 4, "c0_dab" },
- { 24, 5, "c0_dabm" },
- { 24, 6, "c0_dvb" },
- { 24, 7, "c0_dvbm" },
- { 25, 1, "c0_perfcnt,1" },
- { 25, 2, "c0_perfcnt,2" }
-};
-
static const char * const mips_cp0_names_mips3264[32] =
{
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
+static const char * const mips_cp1_names_mips3264[32] =
+{
+ "c1_fir", "c1_ufr", "$2", "$3",
+ "c1_unfr", "$5", "$6", "$7",
+ "$8", "$9", "$10", "$11",
+ "$12", "$13", "$14", "$15",
+ "$16", "$17", "$18", "$19",
+ "$20", "$21", "$22", "$23",
+ "$24", "c1_fccr", "c1_fexr", "$27",
+ "c1_fenr", "$29", "$30", "c1_fcsr"
+};
+
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
{
{ 16, 1, "c0_config1" },
const char * const *cp0_names;
const struct mips_cp0sel_name *cp0sel_names;
unsigned int cp0sel_names_len;
+ const char * const *cp1_names;
const char * const *hwr_names;
};
const struct mips_arch_choice mips_arch_choices[] =
{
{ "numeric", 0, 0, 0, 0, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
- mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
- mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
- mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
- mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
ISA_MIPS32, ASE_SMARTMIPS,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
- mips_hwr_names_numeric },
+ mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
ISA_MIPS32R2,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
- | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3,
+ ISA_MIPS32R3,
+ (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
- mips_hwr_names_mips3264r2 },
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5,
+ ISA_MIPS32R5,
+ (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
+ ISA_MIPS32R6,
+ (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
+ | ASE_DSPR2 | ASE_DSPR3),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
- mips_hwr_names_numeric },
+ mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
ISA_MIPS64R2,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
- | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3,
+ ISA_MIPS64R3,
+ (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
- mips_hwr_names_mips3264r2 },
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5,
+ ISA_MIPS64R5,
+ (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
+ ISA_MIPS64R6,
+ (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
+ | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "interaptiv-mr2", 1, bfd_mach_mips_interaptiv_mr2, CPU_INTERAPTIV_MR2,
+ ISA_MIPS32R3,
+ ASE_MT | ASE_EVA | ASE_DSP | ASE_DSPR2 | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
{ "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
mips_cp0_names_sb1,
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
- mips_hwr_names_numeric },
+ mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
- NULL, 0, mips_hwr_names_numeric },
+ NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
{ "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
- NULL, 0, mips_hwr_names_numeric },
+ NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
- ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
- NULL, 0, mips_hwr_names_numeric },
+ ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
+ NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
- mips_hwr_names_numeric },
+ mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
- NULL, 0, mips_hwr_names_numeric },
+ NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
- NULL, 0, mips_hwr_names_numeric },
+ NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
+ { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
+ ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
+ mips_cp0_names_numeric,
+ NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR, 0,
mips_cp0_names_xlr,
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
- mips_hwr_names_numeric },
+ mips_cp1_names_mips3264, mips_hwr_names_numeric },
/* XLP is mostly like XLR, with the prominent exception it is being
MIPS64R2. */
ISA_MIPS64R2 | INSN_XLR, 0,
mips_cp0_names_xlr,
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
- mips_hwr_names_numeric },
+ mips_cp1_names_mips3264, mips_hwr_names_numeric },
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
- { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64,
+ ASE_MIPS16E2 | ASE_MIPS16E2_MT,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_hwr_names_numeric },
};
/* ISA and processor type to disassemble for, and register names to use.
static const char * const *mips_cp0_names;
static const struct mips_cp0sel_name *mips_cp0sel_names;
static int mips_cp0sel_names_len;
+static const char * const *mips_cp1_names;
static const char * const *mips_hwr_names;
/* Other options */
return 0;
}
+/* Convert ASE flags from .MIPS.abiflags to internal values. */
+
+static unsigned long
+mips_convert_abiflags_ases (unsigned long afl_ases)
+{
+ unsigned long opcode_ases = 0;
+
+ if (afl_ases & AFL_ASE_DSP)
+ opcode_ases |= ASE_DSP;
+ if (afl_ases & AFL_ASE_DSPR2)
+ opcode_ases |= ASE_DSPR2;
+ if (afl_ases & AFL_ASE_EVA)
+ opcode_ases |= ASE_EVA;
+ if (afl_ases & AFL_ASE_MCU)
+ opcode_ases |= ASE_MCU;
+ if (afl_ases & AFL_ASE_MDMX)
+ opcode_ases |= ASE_MDMX;
+ if (afl_ases & AFL_ASE_MIPS3D)
+ opcode_ases |= ASE_MIPS3D;
+ if (afl_ases & AFL_ASE_MT)
+ opcode_ases |= ASE_MT;
+ if (afl_ases & AFL_ASE_SMARTMIPS)
+ opcode_ases |= ASE_SMARTMIPS;
+ if (afl_ases & AFL_ASE_VIRT)
+ opcode_ases |= ASE_VIRT;
+ if (afl_ases & AFL_ASE_MSA)
+ opcode_ases |= ASE_MSA;
+ if (afl_ases & AFL_ASE_XPA)
+ opcode_ases |= ASE_XPA;
+ if (afl_ases & AFL_ASE_DSPR3)
+ opcode_ases |= ASE_DSPR3;
+ if (afl_ases & AFL_ASE_MIPS16E2)
+ opcode_ases |= ASE_MIPS16E2;
+ return opcode_ases;
+}
+
+/* Calculate combination ASE flags from regular ASE flags. */
+
+static unsigned long
+mips_calculate_combination_ases (unsigned long opcode_ases)
+{
+ unsigned long combination_ases = 0;
+
+ if ((opcode_ases & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
+ combination_ases |= ASE_XPA_VIRT;
+ if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
+ combination_ases |= ASE_MIPS16E2_MT;
+ return combination_ases;
+}
+
static void
set_default_mips_dis_options (struct disassemble_info *info)
{
mips_cp0_names = mips_cp0_names_numeric;
mips_cp0sel_names = NULL;
mips_cp0sel_names_len = 0;
+ mips_cp1_names = mips_cp1_names_numeric;
mips_hwr_names = mips_hwr_names_numeric;
no_aliases = 0;
- /* Update settings according to the ELF file header flags. */
- if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
- {
- Elf_Internal_Ehdr *header;
-
- header = elf_elfheader (info->section->owner);
- /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
- if (is_newabi (header))
- mips_gpr_names = mips_gpr_names_newabi;
- /* If a microMIPS binary, then don't use MIPS16 bindings. */
- micromips_ase = is_micromips (header);
- }
-
/* Set ISA, architecture, and cp0 register names as best we can. */
#if ! SYMTAB_AVAILABLE
/* This is running out on a target machine, not in a host tool.
mips_cp0_names = chosen_arch->cp0_names;
mips_cp0sel_names = chosen_arch->cp0sel_names;
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+ mips_cp1_names = chosen_arch->cp1_names;
mips_hwr_names = chosen_arch->hwr_names;
}
+
+ /* Update settings according to the ELF file header flags. */
+ if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
+ {
+ struct bfd *abfd = info->section->owner;
+ Elf_Internal_Ehdr *header = elf_elfheader (abfd);
+ Elf_Internal_ABIFlags_v0 *abiflags = NULL;
+
+ /* We won't ever get here if !HAVE_BFD_MIPS_ELF_GET_ABIFLAGS,
+ because we won't then have a MIPS/ELF BFD, however we need
+ to guard against a link error in a `--enable-targets=...'
+ configuration with a 32-bit host where the MIPS target is
+ a secondary, or with MIPS/ECOFF configurations. */
+#ifdef HAVE_BFD_MIPS_ELF_GET_ABIFLAGS
+ abiflags = bfd_mips_elf_get_abiflags (abfd);
#endif
+ /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
+ if (is_newabi (header))
+ mips_gpr_names = mips_gpr_names_newabi;
+ /* If a microMIPS binary, then don't use MIPS16 bindings. */
+ micromips_ase = is_micromips (header);
+ /* OR in any extra ASE flags set in ELF file structures. */
+ if (abiflags)
+ mips_ase |= mips_convert_abiflags_ases (abiflags->ases);
+ else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX)
+ mips_ase |= ASE_MDMX;
+ }
+#endif
+ mips_ase |= mips_calculate_combination_ases (mips_ase);
+}
+
+/* Parse an ASE disassembler option and set the corresponding global
+ ASE flag(s). Return TRUE if successful, FALSE otherwise. */
+
+static bfd_boolean
+parse_mips_ase_option (const char *option)
+{
+ if (CONST_STRNEQ (option, "msa"))
+ {
+ mips_ase |= ASE_MSA;
+ if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)
+ mips_ase |= ASE_MSA64;
+ return TRUE;
+ }
+
+ if (CONST_STRNEQ (option, "virt"))
+ {
+ mips_ase |= ASE_VIRT;
+ if (mips_isa & ISA_MIPS64R2
+ || mips_isa & ISA_MIPS64R3
+ || mips_isa & ISA_MIPS64R5
+ || mips_isa & ISA_MIPS64R6)
+ mips_ase |= ASE_VIRT64;
+ return TRUE;
+ }
+
+ if (CONST_STRNEQ (option, "xpa"))
+ {
+ mips_ase |= ASE_XPA;
+ return TRUE;
+ }
+
+ return FALSE;
}
static void
return;
}
- if (CONST_STRNEQ (option, "msa"))
+ if (parse_mips_ase_option (option))
{
- mips_ase |= ASE_MSA;
- if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2)
- mips_ase |= ASE_MSA64;
+ mips_ase |= mips_calculate_combination_ases (mips_ase);
return;
}
- if (CONST_STRNEQ (option, "virt"))
- {
- mips_ase |= ASE_VIRT;
- if (mips_isa & ISA_MIPS64R2)
- mips_ase |= ASE_VIRT64;
- return;
- }
-
/* Look for the = that delimits the end of the option name. */
for (i = 0; i < len; i++)
if (option[i] == '=')
return;
}
+ if (strncmp ("cp1-names", option, optionlen) == 0
+ && strlen ("cp1-names") == optionlen)
+ {
+ chosen_arch = choose_arch_by_name (val, vallen);
+ if (chosen_arch != NULL)
+ mips_cp1_names = chosen_arch->cp1_names;
+ return;
+ }
+
if (strncmp ("hwr-names", option, optionlen) == 0
&& strlen ("hwr-names") == optionlen)
{
mips_cp0_names = chosen_arch->cp0_names;
mips_cp0sel_names = chosen_arch->cp0sel_names;
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+ mips_cp1_names = chosen_arch->cp1_names;
mips_hwr_names = chosen_arch->hwr_names;
}
return;
case OP_REG_COPRO:
if (opcode->name[strlen (opcode->name) - 1] == '0')
info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
+ else if (opcode->name[strlen (opcode->name) - 1] == '1')
+ info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]);
else
info->fprintf_func (info->stream, "$%d", regno);
break;
OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */
enum mips_reg_operand_type last_reg_type;
unsigned int last_regno;
+ unsigned int dest_regno;
+ unsigned int seen_dest;
};
/* Initialize STATE for the start of an instruction. */
abort ();
}
+/* Record information about a register operand. */
+
+static void
+mips_seen_register (struct mips_print_arg_state *state,
+ unsigned int regno,
+ enum mips_reg_operand_type reg_type)
+{
+ state->last_reg_type = reg_type;
+ state->last_regno = regno;
+
+ if (!state->seen_dest)
+ {
+ state->seen_dest = 1;
+ state->dest_regno = regno;
+ }
+}
+
+/* Print SAVE/RESTORE instruction operands according to the argument
+ register mask AMASK, the number of static registers saved NSREG,
+ the $ra, $s0 and $s1 register specifiers RA, S0 and S1 respectively,
+ and the frame size FRAME_SIZE. */
+
+static void
+mips_print_save_restore (struct disassemble_info *info, unsigned int amask,
+ unsigned int nsreg, unsigned int ra,
+ unsigned int s0, unsigned int s1,
+ unsigned int frame_size)
+{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ unsigned int nargs, nstatics, smask, i, j;
+ void *is = info->stream;
+ const char *sep;
+
+ if (amask == MIPS_SVRS_ALL_ARGS)
+ {
+ nargs = 4;
+ nstatics = 0;
+ }
+ else if (amask == MIPS_SVRS_ALL_STATICS)
+ {
+ nargs = 0;
+ nstatics = 4;
+ }
+ else
+ {
+ nargs = amask >> 2;
+ nstatics = amask & 3;
+ }
+
+ sep = "";
+ if (nargs > 0)
+ {
+ infprintf (is, "%s", mips_gpr_names[4]);
+ if (nargs > 1)
+ infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
+ sep = ",";
+ }
+
+ infprintf (is, "%s%d", sep, frame_size);
+
+ if (ra) /* $ra */
+ infprintf (is, ",%s", mips_gpr_names[31]);
+
+ smask = 0;
+ if (s0) /* $s0 */
+ smask |= 1 << 0;
+ if (s1) /* $s1 */
+ smask |= 1 << 1;
+ if (nsreg > 0) /* $s2-$s8 */
+ smask |= ((1 << nsreg) - 1) << 2;
+
+ for (i = 0; i < 9; i++)
+ if (smask & (1 << i))
+ {
+ infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
+ /* Skip over string of set bits. */
+ for (j = i; smask & (2 << j); j++)
+ continue;
+ if (j > i)
+ infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
+ i = j + 1;
+ }
+ /* Statics $ax - $a3. */
+ if (nstatics == 1)
+ infprintf (is, ",%s", mips_gpr_names[7]);
+ else if (nstatics > 0)
+ infprintf (is, ",%s-%s",
+ mips_gpr_names[7 - nstatics + 1],
+ mips_gpr_names[7]);
+}
+
+
/* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
the base address for OP_PCREL operands. */
uval = mips_decode_reg_operand (reg_op, uval);
print_reg (info, opcode, reg_op->reg_type, uval);
- state->last_reg_type = reg_op->reg_type;
- state->last_regno = uval;
+ mips_seen_register (state, uval, reg_op->reg_type);
}
break;
pcrel_op = (const struct mips_pcrel_operand *) operand;
info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval);
- /* Preserve the ISA bit for the GDB disassembler,
- otherwise clear it. */
- if (info->flavour != bfd_target_unknown_flavour)
+ /* For jumps and branches clear the ISA bit except for
+ the GDB disassembler. */
+ if (pcrel_op->include_isa_bit
+ && info->flavour != bfd_target_unknown_flavour)
info->target &= -2;
(*info->print_address_func) (info->target, info);
}
break;
+ case OP_SAME_RS_RT:
+ case OP_CHECK_PREV:
+ case OP_NON_ZERO_REG:
+ {
+ print_reg (info, opcode, OP_REG_GP, uval & 31);
+ mips_seen_register (state, uval, OP_REG_GP);
+ }
+ break;
+
case OP_LWM_SWM_LIST:
if (operand->size == 2)
{
break;
case OP_SAVE_RESTORE_LIST:
- /* Should be handled by the caller due to extend behavior. */
+ /* Should be handled by the caller due to complex behavior. */
abort ();
case OP_MDMX_IMM_REG:
break;
case OP_REPEAT_DEST_REG:
- /* Should always match OP_REPEAT_PREV_REG first. */
- abort ();
+ print_reg (info, opcode, state->last_reg_type, state->dest_regno);
+ break;
case OP_PC:
infprintf (is, "$pc");
break;
+ case OP_REG28:
+ print_reg (info, opcode, OP_REG_GP, 28);
+ break;
+
case OP_VU0_SUFFIX:
case OP_VU0_MATCH_SUFFIX:
print_vu0_channel (info, operand, uval);
}
}
+/* Validate the arguments for INSN, which is described by OPCODE.
+ Use DECODE_OPERAND to get the encoding of each operand. */
+
+static bfd_boolean
+validate_insn_args (const struct mips_opcode *opcode,
+ const struct mips_operand *(*decode_operand) (const char *),
+ unsigned int insn)
+{
+ struct mips_print_arg_state state;
+ const struct mips_operand *operand;
+ const char *s;
+ unsigned int uval;
+
+ init_print_arg_state (&state);
+ for (s = opcode->args; *s; ++s)
+ {
+ switch (*s)
+ {
+ case ',':
+ case '(':
+ case ')':
+ break;
+
+ case '#':
+ ++s;
+ break;
+
+ default:
+ operand = decode_operand (s);
+
+ if (operand)
+ {
+ uval = mips_extract_operand (operand, insn);
+ switch (operand->type)
+ {
+ case OP_REG:
+ case OP_OPTIONAL_REG:
+ {
+ const struct mips_reg_operand *reg_op;
+
+ reg_op = (const struct mips_reg_operand *) operand;
+ uval = mips_decode_reg_operand (reg_op, uval);
+ mips_seen_register (&state, uval, reg_op->reg_type);
+ }
+ break;
+
+ case OP_SAME_RS_RT:
+ {
+ unsigned int reg1, reg2;
+
+ reg1 = uval & 31;
+ reg2 = uval >> 5;
+
+ if (reg1 != reg2 || reg1 == 0)
+ return FALSE;
+ }
+ break;
+
+ case OP_CHECK_PREV:
+ {
+ const struct mips_check_prev_operand *prev_op;
+
+ prev_op = (const struct mips_check_prev_operand *) operand;
+
+ if (!prev_op->zero_ok && uval == 0)
+ return FALSE;
+
+ if (((prev_op->less_than_ok && uval < state.last_regno)
+ || (prev_op->greater_than_ok && uval > state.last_regno)
+ || (prev_op->equal_ok && uval == state.last_regno)))
+ break;
+
+ return FALSE;
+ }
+
+ case OP_NON_ZERO_REG:
+ {
+ if (uval == 0)
+ return FALSE;
+ }
+ break;
+
+ case OP_INT:
+ case OP_MAPPED_INT:
+ case OP_MSB:
+ case OP_REG_PAIR:
+ case OP_PCREL:
+ case OP_PERF_REG:
+ case OP_ADDIUSP_INT:
+ case OP_CLO_CLZ_DEST:
+ case OP_LWM_SWM_LIST:
+ case OP_ENTRY_EXIT_LIST:
+ case OP_MDMX_IMM_REG:
+ case OP_REPEAT_PREV_REG:
+ case OP_REPEAT_DEST_REG:
+ case OP_PC:
+ case OP_REG28:
+ case OP_VU0_SUFFIX:
+ case OP_VU0_MATCH_SUFFIX:
+ case OP_IMM_INDEX:
+ case OP_REG_INDEX:
+ case OP_SAVE_RESTORE_LIST:
+ break;
+ }
+ }
+ if (*s == 'm' || *s == '+' || *s == '-')
+ ++s;
+ }
+ }
+ return TRUE;
+}
+
/* Print the arguments for INSN, which is described by OPCODE.
Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC
- as the base of OP_PCREL operands. */
+ as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL
+ operand is for a branch or jump. */
static void
print_insn_args (struct disassemble_info *info,
const struct mips_opcode *opcode,
const struct mips_operand *(*decode_operand) (const char *),
- unsigned int insn, bfd_vma base_pc)
+ unsigned int insn, bfd_vma insn_pc, unsigned int length)
{
const fprintf_ftype infprintf = info->fprintf_func;
void *is = info->stream;
opcode->name, opcode->args);
return;
}
- if (operand->type == OP_REG
- && s[1] == ','
- && s[2] == 'H'
- && opcode->name[strlen (opcode->name) - 1] == '0')
+
+ if (operand->type == OP_SAVE_RESTORE_LIST)
+ {
+ /* Handle this case here because of the complex behavior. */
+ unsigned int amask = (insn >> 15) & 0xf;
+ unsigned int nsreg = (insn >> 23) & 0x7;
+ unsigned int ra = insn & 0x1000; /* $ra */
+ unsigned int s0 = insn & 0x800; /* $s0 */
+ unsigned int s1 = insn & 0x400; /* $s1 */
+ unsigned int frame_size = (((insn >> 15) & 0xf0)
+ | ((insn >> 6) & 0x0f)) * 8;
+ mips_print_save_restore (info, amask, nsreg, ra, s0, s1,
+ frame_size);
+ }
+ else if (operand->type == OP_REG
+ && s[1] == ','
+ && s[2] == 'H'
+ && opcode->name[strlen (opcode->name) - 1] == '0')
{
- /* Coprocessor register 0 with sel field (MT ASE). */
+ /* Coprocessor register 0 with sel field. */
const struct mips_cp0sel_name *n;
unsigned int reg, sel;
infprintf (is, "$%d,%d", reg, sel);
}
else
- print_insn_arg (info, &state, opcode, operand, base_pc,
- mips_extract_operand (operand, insn));
- if (*s == 'm' || *s == '+')
+ {
+ bfd_vma base_pc = insn_pc;
+
+ /* Adjust the PC relative base so that branch/jump insns use
+ the following PC as the base but genuinely PC relative
+ operands use the current PC. */
+ if (operand->type == OP_PCREL)
+ {
+ const struct mips_pcrel_operand *pcrel_op;
+
+ pcrel_op = (const struct mips_pcrel_operand *) operand;
+ /* The include_isa_bit flag is sufficient to distinguish
+ branch/jump from other PC relative operands. */
+ if (pcrel_op->include_isa_bit)
+ base_pc += length;
+ }
+
+ print_insn_arg (info, &state, opcode, operand, base_pc,
+ mips_extract_operand (operand, insn));
+ }
+ if (*s == 'm' || *s == '+' || *s == '-')
++s;
break;
}
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
{
- if (op->pinfo != INSN_MACRO
+ if (op->pinfo != INSN_MACRO
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
&& (word & op->mask) == op->match)
{
- /* We always allow to disassemble the jalx instruction. */
+ /* We always disassemble the jalx instruction, except for MIPS r6. */
if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
- && strcmp (op->name, "jalx"))
+ && (strcmp (op->name, "jalx")
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6))
continue;
/* Figure out instruction type and branch delay information. */
| INSN_LOAD_MEMORY)) != 0)
info->insn_type = dis_dref;
+ if (!validate_insn_args (op, decode_mips_operand, word))
+ continue;
+
infprintf (is, "%s", op->name);
if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
{
{
infprintf (is, "\t");
print_insn_args (info, op, decode_mips_operand, word,
- memaddr + 4);
+ memaddr, 4);
}
return INSNLEN;
const fprintf_ftype infprintf = info->fprintf_func;
void *is = info->stream;
const struct mips_operand *operand, *ext_operand;
+ unsigned short ext_size;
unsigned int uval;
bfd_vma baseaddr;
if (operand->type == OP_SAVE_RESTORE_LIST)
{
- /* Handle this case here because of the complex interation
+ /* Handle this case here because of the complex interaction
with the EXTEND opcode. */
- unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j;
- const char *sep;
-
- amask = extend & 0xf;
- if (amask == MIPS16_ALL_ARGS)
- {
- nargs = 4;
- nstatics = 0;
- }
- else if (amask == MIPS16_ALL_STATICS)
- {
- nargs = 0;
- nstatics = 4;
- }
- else
- {
- nargs = amask >> 2;
- nstatics = amask & 3;
- }
-
- sep = "";
- if (nargs > 0)
- {
- infprintf (is, "%s", mips_gpr_names[4]);
- if (nargs > 1)
- infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
- sep = ",";
- }
-
- frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
+ unsigned int amask = extend & 0xf;
+ unsigned int nsreg = (extend >> 8) & 0x7;
+ unsigned int ra = insn & 0x40; /* $ra */
+ unsigned int s0 = insn & 0x20; /* $s0 */
+ unsigned int s1 = insn & 0x10; /* $s1 */
+ unsigned int frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
if (frame_size == 0 && !use_extend)
frame_size = 128;
- infprintf (is, "%s%d", sep, frame_size);
-
- if (insn & 0x40) /* $ra */
- infprintf (is, ",%s", mips_gpr_names[31]);
-
- nsreg = (extend >> 8) & 0x7;
- smask = 0;
- if (insn & 0x20) /* $s0 */
- smask |= 1 << 0;
- if (insn & 0x10) /* $s1 */
- smask |= 1 << 1;
- if (nsreg > 0) /* $s2-$s8 */
- smask |= ((1 << nsreg) - 1) << 2;
-
- for (i = 0; i < 9; i++)
- if (smask & (1 << i))
- {
- infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
- /* Skip over string of set bits. */
- for (j = i; smask & (2 << j); j++)
- continue;
- if (j > i)
- infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
- i = j + 1;
- }
- /* Statics $ax - $a3. */
- if (nstatics == 1)
- infprintf (is, ",%s", mips_gpr_names[7]);
- else if (nstatics > 0)
- infprintf (is, ",%s-%s",
- mips_gpr_names[7 - nstatics + 1],
- mips_gpr_names[7]);
+ mips_print_save_restore (info, amask, nsreg, ra, s0, s1, frame_size);
break;
}
info->data_size = 1 << int_op->shift;
}
- if (operand->size == 26)
- /* In this case INSN is the first two bytes of the instruction
- and EXTEND is the second two bytes. */
- uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend;
- else
+ ext_size = 0;
+ if (use_extend)
{
- /* Calculate the full field value. */
- uval = mips_extract_operand (operand, insn);
- if (use_extend)
+ ext_operand = decode_mips16_operand (type, TRUE);
+ if (ext_operand != operand
+ || (operand->type == OP_INT && operand->lsb == 0
+ && mips_opcode_32bit_p (opcode)))
{
- ext_operand = decode_mips16_operand (type, TRUE);
- if (ext_operand != operand)
- {
- operand = ext_operand;
- if (operand->size == 16)
- uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
- else if (operand->size == 15)
- uval |= ((extend & 0xf) << 11) | (extend & 0x7f0);
- else
- uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
- }
+ ext_size = ext_operand->size;
+ operand = ext_operand;
}
}
+ if (operand->size == 26)
+ uval = ((extend & 0x1f) << 21) | ((extend & 0x3e0) << 11) | insn;
+ else if (ext_size == 16 || ext_size == 9)
+ uval = ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
+ else if (ext_size == 15)
+ uval = ((extend & 0xf) << 11) | (extend & 0x7f0) | (insn & 0xf);
+ else if (ext_size == 6)
+ uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
+ else
+ uval = mips_extract_operand (operand, (extend << 16) | insn);
+ if (ext_size == 9)
+ uval &= (1U << ext_size) - 1;
baseaddr = memaddr + 2;
if (operand->type == OP_PCREL)
if (!pcrel_op->include_isa_bit && use_extend)
baseaddr = memaddr - 2;
else if (!pcrel_op->include_isa_bit)
- {
- bfd_byte buffer[2];
-
- /* If this instruction is in the delay slot of a JR
- instruction, the base address is the address of the
- JR instruction. If it is in the delay slot of a JALR
- instruction, the base address is the address of the
- JALR instruction. This test is unreliable: we have
- no way of knowing whether the previous word is
- instruction or data. */
- if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
- && (((info->endian == BFD_ENDIAN_BIG
- ? bfd_getb16 (buffer)
- : bfd_getl16 (buffer))
- & 0xf800) == 0x1800))
- baseaddr = memaddr - 4;
- else if (info->read_memory_func (memaddr - 2, buffer, 2,
- info) == 0
- && (((info->endian == BFD_ENDIAN_BIG
- ? bfd_getb16 (buffer)
- : bfd_getl16 (buffer))
- & 0xf81f) == 0xe800))
- baseaddr = memaddr - 2;
- else
- baseaddr = memaddr;
- }
+ {
+ bfd_byte buffer[2];
+
+ /* If this instruction is in the delay slot of a JAL/JALX
+ instruction, the base address is the address of the
+ JAL/JALX instruction. If it is in the delay slot of
+ a JR/JALR instruction, the base address is the address
+ of the JR/JALR instruction. This test is unreliable:
+ we have no way of knowing whether the previous word is
+ instruction or data. */
+ if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
+ && (((info->endian == BFD_ENDIAN_BIG
+ ? bfd_getb16 (buffer)
+ : bfd_getl16 (buffer))
+ & 0xf800) == 0x1800))
+ baseaddr = memaddr - 4;
+ else if (info->read_memory_func (memaddr - 2, buffer, 2,
+ info) == 0
+ && (((info->endian == BFD_ENDIAN_BIG
+ ? bfd_getb16 (buffer)
+ : bfd_getl16 (buffer))
+ & 0xf89f) == 0xe800)
+ && (((info->endian == BFD_ENDIAN_BIG
+ ? bfd_getb16 (buffer)
+ : bfd_getl16 (buffer))
+ & 0x0060) != 0x0060))
+ baseaddr = memaddr - 2;
+ else
+ baseaddr = memaddr;
+ }
}
print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval);
return FALSE;
}
+/* Whether none, a 32-bit or a 16-bit instruction match has been done. */
+
+enum match_kind
+{
+ MATCH_NONE,
+ MATCH_FULL,
+ MATCH_SHORT
+};
+
/* Disassemble mips16 instructions. */
static int
const fprintf_ftype infprintf = info->fprintf_func;
int status;
bfd_byte buffer[4];
- int length;
- int insn;
- bfd_boolean use_extend;
- int extend = 0;
const struct mips_opcode *op, *opend;
struct mips_print_arg_state state;
void *is = info->stream;
+ bfd_boolean have_second;
+ bfd_boolean extend_only;
+ unsigned int second;
+ unsigned int first;
+ unsigned int full;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
return -1;
}
- length = 2;
+ extend_only = FALSE;
if (info->endian == BFD_ENDIAN_BIG)
- insn = bfd_getb16 (buffer);
+ first = bfd_getb16 (buffer);
else
- insn = bfd_getl16 (buffer);
+ first = bfd_getl16 (buffer);
- /* Handle the extend opcode specially. */
- use_extend = FALSE;
- if ((insn & 0xf800) == 0xf000)
+ status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
+ if (status == 0)
{
- use_extend = TRUE;
- extend = insn & 0x7ff;
-
- memaddr += 2;
-
- status = (*info->read_memory_func) (memaddr, buffer, 2, info);
- if (status != 0)
- {
- infprintf (is, "extend 0x%x", (unsigned int) extend);
- (*info->memory_error_func) (status, memaddr, info);
- return -1;
- }
-
+ have_second = TRUE;
if (info->endian == BFD_ENDIAN_BIG)
- insn = bfd_getb16 (buffer);
+ second = bfd_getb16 (buffer);
else
- insn = bfd_getl16 (buffer);
-
- /* Check for an extend opcode followed by an extend opcode. */
- if ((insn & 0xf800) == 0xf000)
- {
- infprintf (is, "extend 0x%x", (unsigned int) extend);
- info->insn_type = dis_noninsn;
- return length;
- }
-
- length += 2;
+ second = bfd_getl16 (buffer);
+ full = (first << 16) | second;
+ }
+ else
+ {
+ have_second = FALSE;
+ second = 0;
+ full = first;
}
/* FIXME: Should probably use a hash table on the major opcode here. */
opend = mips16_opcodes + bfd_mips16_num_opcodes;
for (op = mips16_opcodes; op < opend; op++)
{
- if (op->pinfo != INSN_MACRO
- && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
- && (insn & op->mask) == op->match)
- {
- const char *s;
-
- if (op->args[0] == 'a' || op->args[0] == 'i')
- {
- if (use_extend)
- {
- infprintf (is, "extend 0x%x", (unsigned int) extend);
- info->insn_type = dis_noninsn;
- return length - 2;
- }
-
- use_extend = FALSE;
+ enum match_kind match;
- memaddr += 2;
+ if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor))
+ continue;
- status = (*info->read_memory_func) (memaddr, buffer, 2,
- info);
- if (status == 0)
- {
- use_extend = TRUE;
- if (info->endian == BFD_ENDIAN_BIG)
- extend = bfd_getb16 (buffer);
- else
- extend = bfd_getl16 (buffer);
- length += 2;
- }
+ if (op->pinfo == INSN_MACRO
+ || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
+ match = MATCH_NONE;
+ else if (mips_opcode_32bit_p (op))
+ {
+ if (have_second
+ && (full & op->mask) == op->match)
+ match = MATCH_FULL;
+ else
+ match = MATCH_NONE;
+ }
+ else if ((first & op->mask) == op->match)
+ {
+ match = MATCH_SHORT;
+ second = 0;
+ full = first;
+ }
+ else if ((first & 0xf800) == 0xf000
+ && have_second
+ && !extend_only
+ && (second & op->mask) == op->match)
+ {
+ if (op->pinfo2 & INSN2_SHORT_ONLY)
+ {
+ match = MATCH_NONE;
+ extend_only = TRUE;
}
+ else
+ match = MATCH_FULL;
+ }
+ else
+ match = MATCH_NONE;
+
+ if (match != MATCH_NONE)
+ {
+ const char *s;
infprintf (is, "%s", op->name);
if (op->args[0] != '\0')
{
if (*s == ','
&& s[1] == 'w'
- && GET_OP (insn, RX) == GET_OP (insn, RY))
+ && GET_OP (full, RX) == GET_OP (full, RY))
{
/* Skip the register and the comma. */
++s;
}
if (*s == ','
&& s[1] == 'v'
- && GET_OP (insn, RZ) == GET_OP (insn, RX))
+ && GET_OP (full, RZ) == GET_OP (full, RX))
{
/* Skip the register and the comma. */
++s;
continue;
}
- print_mips16_insn_arg (info, &state, op, *s, memaddr, insn,
- use_extend, extend, s[1] == '(');
+ if (s[0] == 'N'
+ && s[1] == ','
+ && s[2] == 'O'
+ && op->name[strlen (op->name) - 1] == '0')
+ {
+ /* Coprocessor register 0 with sel field. */
+ const struct mips_cp0sel_name *n;
+ const struct mips_operand *operand;
+ unsigned int reg, sel;
+
+ operand = decode_mips16_operand (*s, TRUE);
+ reg = mips_extract_operand (operand, (first << 16) | second);
+ s += 2;
+ operand = decode_mips16_operand (*s, TRUE);
+ sel = mips_extract_operand (operand, (first << 16) | second);
+
+ /* CP0 register including 'sel' code for mftc0, to be
+ printed textually if known. If not known, print both
+ CP0 register name and sel numerically since CP0 register
+ with sel 0 may have a name unrelated to register being
+ printed. */
+ n = lookup_mips_cp0sel_name (mips_cp0sel_names,
+ mips_cp0sel_names_len,
+ reg, sel);
+ if (n != NULL)
+ infprintf (is, "%s", n->name);
+ else
+ infprintf (is, "$%d,%d", reg, sel);
+ }
+ else
+ switch (match)
+ {
+ case MATCH_FULL:
+ print_mips16_insn_arg (info, &state, op, *s, memaddr + 2,
+ second, TRUE, first, s[1] == '(');
+ break;
+ case MATCH_SHORT:
+ print_mips16_insn_arg (info, &state, op, *s, memaddr,
+ first, FALSE, 0, s[1] == '(');
+ break;
+ case MATCH_NONE: /* Stop the compiler complaining. */
+ break;
+ }
}
/* Figure out branch instruction type and delay slot information. */
else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
info->insn_type = dis_condbranch;
- return length;
+ return match == MATCH_FULL ? 4 : 2;
}
}
#undef GET_OP
- if (use_extend)
- infprintf (is, "0x%x", extend | 0xf000);
- infprintf (is, "0x%x", insn);
+ infprintf (is, "0x%x", first);
info->insn_type = dis_noninsn;
- return length;
+ return 2;
}
/* Disassemble microMIPS instructions. */
else
insn = bfd_getl16 (buffer);
- if ((insn & 0xfc00) == 0x7c00)
- {
- /* This is a 48-bit microMIPS instruction. */
- higher = insn;
-
- status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
- if (status != 0)
- {
- infprintf (is, "micromips 0x%x", higher);
- (*info->memory_error_func) (status, memaddr + 2, info);
- return -1;
- }
- if (info->endian == BFD_ENDIAN_BIG)
- insn = bfd_getb16 (buffer);
- else
- insn = bfd_getl16 (buffer);
- higher = (higher << 16) | insn;
-
- status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
- if (status != 0)
- {
- infprintf (is, "micromips 0x%x", higher);
- (*info->memory_error_func) (status, memaddr + 4, info);
- return -1;
- }
- if (info->endian == BFD_ENDIAN_BIG)
- insn = bfd_getb16 (buffer);
- else
- insn = bfd_getl16 (buffer);
- infprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
-
- info->insn_type = dis_noninsn;
- return 6;
- }
- else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
+ if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
{
/* This is a 32-bit microMIPS instruction. */
higher = insn;
&& ((length == 2 && (op->mask & 0xffff0000) == 0)
|| (length == 4 && (op->mask & 0xffff0000) != 0)))
{
+ if (!validate_insn_args (op, decode_micromips_operand, insn))
+ continue;
+
infprintf (is, "%s", op->name);
if (op->args[0])
{
infprintf (is, "\t");
print_insn_args (info, op, decode_micromips_operand, insn,
- memaddr + length + 1);
+ memaddr + 1, length);
}
/* Figure out instruction type and branch delay information. */
}
/* Return 1 if a symbol associated with the location being disassembled
- indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
- all the symbols at the address being considered assuming if at least
- one of them indicates code compression, then such code has been
- genuinely produced here (other symbols could have been derived from
- function symbols defined elsewhere or could define data). Otherwise,
- return 0. */
+ indicates a compressed mode, either MIPS16 or microMIPS, according to
+ MICROMIPS_P. We iterate over all the symbols at the address being
+ considered assuming if at least one of them indicates code compression,
+ then such code has been genuinely produced here (other symbols could
+ have been derived from function symbols defined elsewhere or could
+ define data). Otherwise, return 0. */
static bfd_boolean
-is_compressed_mode_p (struct disassemble_info *info)
+is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p)
{
int i;
int l;
for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++)
if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0
- && ((!micromips_ase
+ && ((!micromips_p
&& ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i))
- || (micromips_ase
+ || (micromips_p
&& ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i))))
return 1;
else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour
&& info->symtab[i]->section == info->section)
{
elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i];
- if ((!micromips_ase
+ if ((!micromips_p
&& ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
- || (micromips_ase
+ || (micromips_p
&& ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
return 1;
}
struct disassemble_info *info,
enum bfd_endian endianness)
{
- int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
bfd_byte buffer[INSNLEN];
int status;
if (info->mach == bfd_mach_mips_micromips)
return print_insn_micromips (memaddr, info);
- print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
-
#if 1
/* FIXME: If odd address, this is CLEARLY a compressed instruction. */
/* Only a few tools will work this way. */
if (memaddr & 0x01)
- return print_insn_compr (memaddr, info);
+ {
+ if (micromips_ase)
+ return print_insn_micromips (memaddr, info);
+ else
+ return print_insn_mips16 (memaddr, info);
+ }
#endif
#if SYMTAB_AVAILABLE
- if (is_compressed_mode_p (info))
- return print_insn_compr (memaddr, info);
+ if (is_compressed_mode_p (info, TRUE))
+ return print_insn_micromips (memaddr, info);
+ if (is_compressed_mode_p (info, FALSE))
+ return print_insn_mips16 (memaddr, info);
#endif
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
- msa Recognize MSA instructions.\n"));
+ no-aliases Use canonical instruction forms.\n"));
+
+ fprintf (stream, _("\n\
+ msa Recognize MSA instructions.\n"));
+
+ fprintf (stream, _("\n\
+ virt Recognize the virtualization ASE instructions.\n"));
fprintf (stream, _("\n\
- virt Recognize the virtualization ASE instructions.\n"));
+ xpa Recognize the eXtended Physical Address (XPA)\n\
+ ASE instructions.\n"));
fprintf (stream, _("\n\
- gpr-names=ABI Print GPR names according to specified ABI.\n\
+ gpr-names=ABI Print GPR names according to specified ABI.\n\
Default: based on binary being disassembled.\n"));
fprintf (stream, _("\n\
fprintf (stream, _("\n\
hwr-names=ARCH Print HWR names according to specified \n\
- architecture.\n\
+ architecture.\n\
Default: based on binary being disassembled.\n"));
fprintf (stream, _("\n\