/* Print mips instructions for GDB, the GNU debugger, or for objdump.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001
+ 2000, 2001, 2002
Free Software Foundation, Inc.
Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
static int is_newabi
PARAMS ((Elf_Internal_Ehdr *));
static void print_mips16_insn_arg
- PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma,
+ PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
struct disassemble_info *));
\f
/* FIXME: These should be shared with gdb somehow. */
case ',':
case '(':
case ')':
+ case '[':
+ case ']':
(*info->fprintf_func) (info->stream, "%c", *d);
break;
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
break;
+ case 'e':
+ (*info->fprintf_func) (info->stream, "%d",
+ (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
+ break;
+
+ case '%':
+ (*info->fprintf_func) (info->stream, "%d",
+ (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
+ break;
+
case 'H':
(*info->fprintf_func) (info->stream, "%d",
(l >> OP_SH_SEL) & OP_MASK_SEL);
break;
+ case 'O':
+ (*info->fprintf_func) (info->stream, "%d",
+ (l >> OP_SH_ALN) & OP_MASK_ALN);
+ break;
+
+ case 'Q':
+ {
+ unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
+ if ((vsel & 0x10) == 0)
+ {
+ int fmt;
+ vsel &= 0x0f;
+ for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
+ if ((vsel & 1) == 0)
+ break;
+ (*info->fprintf_func) (info->stream, "$v%d[%d]",
+ (l >> OP_SH_FT) & OP_MASK_FT,
+ vsel >> 1);
+ }
+ else if ((vsel & 0x08) == 0)
+ {
+ (*info->fprintf_func) (info->stream, "$v%d",
+ (l >> OP_SH_FT) & OP_MASK_FT);
+ }
+ else
+ {
+ (*info->fprintf_func) (info->stream, "0x%x",
+ (l >> OP_SH_FT) & OP_MASK_FT);
+ }
+ }
+ break;
+
+ case 'X':
+ (*info->fprintf_func) (info->stream, "$v%d",
+ (l >> OP_SH_FD) & OP_MASK_FD);
+ break;
+
+ case 'Y':
+ (*info->fprintf_func) (info->stream, "$v%d",
+ (l >> OP_SH_FS) & OP_MASK_FS);
+ break;
+
+ case 'Z':
+ (*info->fprintf_func) (info->stream, "$v%d",
+ (l >> OP_SH_FT) & OP_MASK_FT);
+ break;
+
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
*cputype = CPU_R4111;
*isa = ISA_MIPS3;
break;
+ case bfd_mach_mips4120:
+ *cputype = CPU_VR4120;
+ *isa = ISA_MIPS3;
+ break;
case bfd_mach_mips4300:
*cputype = CPU_R4300;
*isa = ISA_MIPS3;
*cputype = CPU_R5000;
*isa = ISA_MIPS4;
break;
+ case bfd_mach_mips5400:
+ *cputype = CPU_VR5400;
+ *isa = ISA_MIPS4;
+ break;
+ case bfd_mach_mips5500:
+ *cputype = CPU_VR5500;
+ *isa = ISA_MIPS4;
+ break;
case bfd_mach_mips6000:
*cputype = CPU_R6000;
*isa = ISA_MIPS2;
break;
case bfd_mach_mips16:
*cputype = CPU_MIPS16;
- *isa = ISA_MIPS3;
+ *isa = ISA_MIPS3 | INSN_MIPS16;
break;
case bfd_mach_mips5:
*cputype = CPU_MIPS5;
case bfd_mach_mipsisa32:
*cputype = CPU_MIPS32;
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
- Note that MIPS-3D is not applicable to MIPS32. (See _MIPS32
- Architecture For Programmers Volume I: Introduction to the
+ Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
+ _MIPS32 Architecture For Programmers Volume I: Introduction to the
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
- *isa = ISA_MIPS32;
+ *isa = ISA_MIPS32 | INSN_MIPS16;
break;
case bfd_mach_mipsisa64:
*cputype = CPU_MIPS64;
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
- *isa = ISA_MIPS64 | INSN_MIPS3D;
+ *isa = ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX;
break;
default:
if (header->e_ident[EI_CLASS] == ELFCLASS64)
return 1;
- /* If a 32-bit ELF file, N32, EABI32, and EABI64 are new-style ABIs. */
- if ((header->e_flags & EF_MIPS_ABI2) != 0
- || (header->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32
- || (header->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI64)
+ /* If a 32-bit ELF file, n32 is a new-style ABI. */
+ if ((header->e_flags & EF_MIPS_ABI2) != 0)
return 1;
return 0;
{
register const struct mips_opcode *op;
int target_processor, mips_isa;
- static boolean init = 0;
+ static bfd_boolean init = 0;
static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
/* Build a hash table to shorten the search time. */
{
register const char *d;
- if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor))
+ /* We always allow to disassemble the jalx instruction. */
+ if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor)
+ && strcmp (op->name, "jalx"))
continue;
/* Figure out instruction type and branch delay information. */
#endif
#if SYMTAB_AVAILABLE
- if (info->mach == 16
+ if (info->mach == bfd_mach_mips16
|| (info->flavour == bfd_target_elf_flavour
&& info->symbols != NULL
&& ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
bfd_byte buffer[2];
int length;
int insn;
- boolean use_extend;
+ bfd_boolean use_extend;
int extend = 0;
const struct mips_opcode *op, *opend;
insn = bfd_getl16 (buffer);
/* Handle the extend opcode specially. */
- use_extend = false;
+ use_extend = FALSE;
if ((insn & 0xf800) == 0xf000)
{
- use_extend = true;
+ use_extend = TRUE;
extend = insn & 0x7ff;
memaddr += 2;
return length - 2;
}
- use_extend = false;
+ use_extend = FALSE;
memaddr += 2;
info);
if (status == 0)
{
- use_extend = true;
+ use_extend = TRUE;
if (info->endian == BFD_ENDIAN_BIG)
extend = bfd_getb16 (buffer);
else
char type;
const struct mips_opcode *op;
int l;
- boolean use_extend;
+ bfd_boolean use_extend;
int extend;
bfd_vma memaddr;
struct disassemble_info *info;
projects / deliverable / binutils-gdb.git / blobdiff