* arm-dis.c (print_insn_arm): Constify "insn". Formatting.

[deliverable/binutils-gdb.git] / opcodes / mips-dis.c

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 9b35a472712b59002ecd337b2309bcea83064a9d..d8862f78de504bb3876ef2936335787029acfe88 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -52,7 +52,7 @@ static int print_insn_mips16
 static int is_newabi
   PARAMS ((Elf_Internal_Ehdr *));
 static void print_mips16_insn_arg
-  PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma,
+  PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
           struct disassemble_info *));
 \f
 /* FIXME: These should be shared with gdb somehow.  */
@@ -110,6 +110,8 @@ print_insn_arg (d, l, pc, info)
     case ',':
     case '(':
     case ')':
+    case '[':
+    case ']':
       (*info->fprintf_func) (info->stream, "%c", *d);
       break;
 
@@ -279,6 +281,16 @@ print_insn_arg (d, l, pc, info)
                             (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
       break;
 
+    case 'e':
+      (*info->fprintf_func) (info->stream, "%d",
+                            (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
+      break;
+
+    case '%':
+      (*info->fprintf_func) (info->stream, "%d",
+                            (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
+      break;
+
     case 'H':
       (*info->fprintf_func) (info->stream, "%d",
                             (l >> OP_SH_SEL) & OP_MASK_SEL);
@@ -300,7 +312,7 @@ print_insn_arg (d, l, pc, info)
              if ((vsel & 1) == 0)
                break;
            (*info->fprintf_func) (info->stream, "$v%d[%d]",
-                                  (l >> OP_SH_FT) & OP_MASK_FT, 
+                                  (l >> OP_SH_FT) & OP_MASK_FT,
                                   vsel >> 1);
          }
        else if ((vsel & 0x08) == 0)
@@ -374,6 +386,10 @@ mips_isa_type (mach, isa, cputype)
       *cputype = CPU_R4111;
       *isa = ISA_MIPS3;
       break;
+    case bfd_mach_mips4120:
+      *cputype = CPU_VR4120;
+      *isa = ISA_MIPS3;
+      break;
     case bfd_mach_mips4300:
       *cputype = CPU_R4300;
       *isa = ISA_MIPS3;
@@ -394,6 +410,14 @@ mips_isa_type (mach, isa, cputype)
       *cputype = CPU_R5000;
       *isa = ISA_MIPS4;
       break;
+    case bfd_mach_mips5400:
+      *cputype = CPU_VR5400;
+      *isa = ISA_MIPS4;
+      break;
+    case bfd_mach_mips5500:
+      *cputype = CPU_VR5500;
+      *isa = ISA_MIPS4;
+      break;
     case bfd_mach_mips6000:
       *cputype = CPU_R6000;
       *isa = ISA_MIPS2;
@@ -474,7 +498,7 @@ print_insn_mips (memaddr, word, info)
 {
   register const struct mips_opcode *op;
   int target_processor, mips_isa;
-  static boolean init = 0;
+  static bfd_boolean init = 0;
   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
 
   /* Build a hash table to shorten the search time.  */
@@ -526,7 +550,9 @@ print_insn_mips (memaddr, word, info)
            {
              register const char *d;
 
-             if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor))
+             /* We always allow to disassemble the jalx instruction.  */
+             if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor)
+                 && strcmp (op->name, "jalx"))
                continue;
 
              /* Figure out instruction type and branch delay information.  */
@@ -595,7 +621,7 @@ _print_insn_mips (memaddr, info, endianness)
 #endif
 
 #if SYMTAB_AVAILABLE
-  if (info->mach == 16
+  if (info->mach == bfd_mach_mips16
       || (info->flavour == bfd_target_elf_flavour
          && info->symbols != NULL
          && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
@@ -661,7 +687,7 @@ print_insn_mips16 (memaddr, info)
   bfd_byte buffer[2];
   int length;
   int insn;
-  boolean use_extend;
+  bfd_boolean use_extend;
   int extend = 0;
   const struct mips_opcode *op, *opend;
 
@@ -689,10 +715,10 @@ print_insn_mips16 (memaddr, info)
     insn = bfd_getl16 (buffer);
 
   /* Handle the extend opcode specially.  */
-  use_extend = false;
+  use_extend = FALSE;
   if ((insn & 0xf800) == 0xf000)
     {
-      use_extend = true;
+      use_extend = TRUE;
       extend = insn & 0x7ff;
 
       memaddr += 2;
@@ -742,7 +768,7 @@ print_insn_mips16 (memaddr, info)
                  return length - 2;
                }
 
-             use_extend = false;
+             use_extend = FALSE;
 
              memaddr += 2;
 
@@ -750,7 +776,7 @@ print_insn_mips16 (memaddr, info)
                                                  info);
              if (status == 0)
                {
-                 use_extend = true;
+                 use_extend = TRUE;
                  if (info->endian == BFD_ENDIAN_BIG)
                    extend = bfd_getb16 (buffer);
                  else
@@ -813,7 +839,7 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
      char type;
      const struct mips_opcode *op;
      int l;
-     boolean use_extend;
+     bfd_boolean use_extend;
      int extend;
      bfd_vma memaddr;
      struct disassemble_info *info;