MIPS: Add Global INValidate ASE support

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index d17280109b4aab8661aa1bf1954ca3120262f03f..1cbcbc6abccd09e49fb175767e6a31324598e891 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -139,6 +139,7 @@ decode_mips_operand (const char *p)
        case '\'': BRANCH (26, 0, 2);
        case '"': BRANCH (21, 0, 2);
        case ';': SPECIAL (10, 16, SAME_RS_RT);
+       case '\\': BIT (2, 8, 0);               /* (0 .. 3) */
        }
       break;
 
@@ -408,6 +409,9 @@ decode_mips_operand (const char *p)
 #define CRC    ASE_CRC
 #define CRC64  ASE_CRC64
 
+/* Global INValidate (GINV) support.  */
+#define GINV   ASE_GINV
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -3361,6 +3365,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"crc32cw",            "t,s,-d",       0x7c00018f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
 {"crc32cd",            "t,s,-d",       0x7c0001cf, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC64,  0 },
 
+/* MIPS Global INValidate (GINV) ASE.  */
+{"ginvi",              "s",            0x7c00003d, 0xfc1fffff, RD_1,                   0,              0,              GINV,   0 },
+{"ginvt",              "s,+\\",        0x7c0000bd, 0xfc1ffcff, RD_1,                   0,              0,              GINV,   0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the