minimal setf support

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 1f2ab7559a41102fcc37a059541bdfdd99523ff5..2719bb054183d9c0aedfed2cdc4ef1736d39f25a 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -63,6 +63,7 @@ Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 
 #define I2     INSN_ISA2
 #define I3     INSN_ISA3
+#define P3     INSN_4650
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -391,6 +392,8 @@ const struct mips_opcode mips_opcodes[] = {
 {"flush",   "t,A(b)",  2,    (int) M_LWR_AB,   INSN_MACRO      }, /* as lwr */
 {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
 {"lwu",     "t,A(b)",  3,    (int) M_LWU_AB,   INSN_MACRO      },
+{"mad",            "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
+{"madu",    "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0  },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
@@ -410,6 +413,7 @@ const struct mips_opcode mips_opcodes[] = {
 {"mtlo",    "s",       0x00000013, 0xfc1fffff, RD_s|WR_LO      },
 {"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T  },
 {"mul.s",   "D,V,T",   0x46000002, 0xffe0003f, WR_D|RD_S|RD_T  },
+{"mul",     "d,v,t",   0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO|P3},
 {"mul",     "d,v,t",   0,    (int) M_MUL,      INSN_MACRO      },
 {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO      },
 {"mulo",    "d,v,t",   0,    (int) M_MULO,     INSN_MACRO      },
@@ -570,12 +574,16 @@ const struct mips_opcode mips_opcodes[] = {
 {"trunc.w.s", "D,S",   0x4600000d, 0xffff003f, WR_D|RD_S|I2    },
 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|I2    },
 {"trunc.w.s", "D,S,t", 0,    (int) M_TRUNCWS,  INSN_MACRO      },
+{"uld",     "t,o(b)",  3,    (int) M_ULD,      INSN_MACRO      },
+{"uld",     "t,A",     3,    (int) M_ULD_A,    INSN_MACRO      },
 {"ulh",     "t,o(b)",  0,    (int) M_ULH,      INSN_MACRO      },
 {"ulh",     "t,A",     0,    (int) M_ULH_A,    INSN_MACRO      },
 {"ulhu",    "t,o(b)",  0,    (int) M_ULHU,     INSN_MACRO      },
 {"ulhu",    "t,A",     0,    (int) M_ULHU_A,   INSN_MACRO      },
 {"ulw",     "t,o(b)",  0,    (int) M_ULW,      INSN_MACRO      },
 {"ulw",     "t,A",     0,    (int) M_ULW_A,    INSN_MACRO      },
+{"usd",     "t,o(b)",  3,    (int) M_USD,      INSN_MACRO      },
+{"usd",     "t,A",     3,    (int) M_USD_A,    INSN_MACRO      },
 {"ush",     "t,o(b)",  0,    (int) M_USH,      INSN_MACRO      },
 {"ush",     "t,A",     0,    (int) M_USH_A,    INSN_MACRO      },
 {"usw",     "t,o(b)",  0,    (int) M_USW,      INSN_MACRO      },