2003-10-03 Andrew Cagney <cagney@redhat.com>

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 436420ef7fb07aa7804f98511c363f004cf6d72a..340a08468a17c480d093507e8b38a6e8fcef4154 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -87,6 +87,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I32    INSN_ISA32
 #define I64     INSN_ISA64
 #define I33    INSN_ISA32R2
+#define I65    INSN_ISA64R2
 
 /* MIPS64 MIPS-3D ASE support.  */
 #define I16     INSN_MIPS16
@@ -481,8 +482,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,                   I3      },
 {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,                   I3      },
 {"deret",   "",         0x4200001f, 0xffffffff, 0,                     I32|G2  },
-{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             I33     },
-{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             I33     },
+{"dext",    "t,r,I,+I",        0,    (int) M_DEXT,     INSN_MACRO,             I65     },
+{"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,                    I65     },
+{"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,                    I65     },
+{"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,                    I65     },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
 {"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,             I3      },
@@ -491,6 +494,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
 {"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             I3      },
 {"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             I3      },
+{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             I33     },
+{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             I33     },
+{"dins",    "t,r,I,+I",        0,    (int) M_DINS,     INSN_MACRO,             I65     },
+{"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                    I65     },
+{"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                    I65     },
+{"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,                    I65     },
 /* The MIPS assembler treats the div opcode with two operands as
    though the first operand appeared twice (the first operand is both
    a source and a destination).  To get the div machine instruction,
@@ -559,9 +568,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"drol",    "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             I3      },
 {"dror",    "d,v,t",   0,    (int) M_DROR,     INSN_MACRO,             I3      },
 {"dror",    "d,v,I",   0,    (int) M_DROR_I,   INSN_MACRO,             I3      },
-{"dror",    "d,w,<",   0x0020003a, 0xffe0003f, WR_d|RD_t,              N5      },
-{"drorv",   "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      },
-{"dror32",  "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              N5      },
+{"dror",    "d,w,<",   0x0020003a, 0xffe0003f, WR_d|RD_t,              N5|I65  },
+{"drorv",   "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         N5|I65  },
+{"dror32",  "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              N5|I65  },
+{"drotl",   "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             I65     },
+{"drotl",   "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             I65     },
+{"drotr",   "d,v,t",   0,    (int) M_DROR,     INSN_MACRO,             I65     },
+{"drotr",   "d,v,I",   0,    (int) M_DROR_I,   INSN_MACRO,             I65     },
+{"drotrv",  "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         I65     },
+{"drotr32", "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              I65     },
+{"dsbh",    "d,w",     0x7c0000a4, 0xffe007ff, WR_d|RD_t,              I65     },
+{"dshd",    "d,w",     0x7c000164, 0xffe007ff, WR_d|RD_t,              I65     },
 {"dsllv",   "d,t,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
 {"dsll32",  "d,w,<",   0x0000003c, 0xffe0003f, WR_d|RD_t,              I3      },
 {"dsll",    "d,w,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsllv */
@@ -979,8 +996,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdr",     "t,o(b)",  0xb4000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
 {"sdr",     "t,A(b)",  0,    (int) M_SDR_AB,   INSN_MACRO,             I3      },
 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     I4      },
-{"seb",     "d,w",     0x7C000420, 0xffe007ff, WR_d|RD_t,              I33     },
-{"seh",     "d,w",     0x7C000620, 0xffe007ff, WR_d|RD_t,              I33     },
+{"seb",     "d,w",     0x7c000420, 0xffe007ff, WR_d|RD_t,              I33     },
+{"seh",     "d,w",     0x7c000620, 0xffe007ff, WR_d|RD_t,              I33     },
 {"selsl",   "d,v,t",   0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         L1      },
 {"selsr",   "d,v,t",   0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         L1      },
 {"seq",     "d,v,t",   0,    (int) M_SEQ,      INSN_MACRO,             I1      },
@@ -1158,7 +1175,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,                   L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                L1      },
 {"wrpgpr",  "d,w",     0x41c00000, 0xffe007ff, RD_t,                   I33     },
-{"wsbh",    "d,w",     0x7C0000a0, 0xffe007ff, WR_d|RD_t,              I33     },
+{"wsbh",    "d,w",     0x7c0000a0, 0xffe007ff, WR_d|RD_t,              I33     },
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             I1      },
 {"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },