[AArch64][SVE 21/32] Add Zn and Pn registers

[deliverable/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index b29a8ed4d0518947a5b88ef5406c6255d6d4f34a..3dcec768481c1c36a2a1f9421217f94a59bbc7dc 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2015 Free Software Foundation, Inc.
+   Copyright (C) 1993-2016 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -374,6 +374,7 @@ decode_mips_operand (const char *p)
 #define DSP_VOLA INSN_NO_DELAY_SLOT
 #define D32    ASE_DSP
 #define D33    ASE_DSPR2
+#define D34    ASE_DSPR3
 #define D64    ASE_DSP64
 
 /* MIPS MT ASE support.  */
@@ -430,7 +431,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"move",               "d,s",          0x00000021, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* addu */
 {"b",                  "p",            0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* beq 0,0 */
 {"b",                  "p",            0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* bgez 0 */
-{"nal",                        "",             0x04100000, 0xffffffff, WR_31|CBD,              INSN2_ALIAS,    I1,             0,      0 },/* bltzal 0 */
 {"bal",                        "p",            0x04110000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS,    I1,             0,      0 },/* bgezal 0*/
 {"bc",                 "+'",           0xc8000000, 0xfc000000, NODS,                   0,              I37,            0,      0 },
 {"balc",               "+'",           0xe8000000, 0xfc000000, WR_31|NODS,             0,              I37,            0,      0 },
@@ -749,6 +749,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bltz",               "s,p",          0x04000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
 {"bltzl",              "s,p",          0x04020000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
 {"bltzal",             "s,p",          0x04100000, 0xfc1f0000, RD_1|WR_31|CBD,         0,              I1,             0,      I37 },
+{"nal",                        "",             0x04100000, 0xffffffff, WR_31|CBD,              0,              I1,             0,      0 }, /* bltzal 0,.+4 */
 {"bltzall",            "s,p",          0x04120000, 0xfc1f0000, RD_1|WR_31|CBL,         0,              I2|T3,          0,      I37 },
 {"bnez",               "s,p",          0x14000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
 {"bnezl",              "s,p",          0x54000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
@@ -2149,6 +2150,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addwc",              "d,s,t",        0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              D32,    0 },
 {"bitrev",             "d,t",          0x7c0006d2, 0xffe007ff, WR_1|RD_2,              0,              0,              D32,    0 },
 {"bposge32",           "p",            0x041c0000, 0xffff0000, CBD,                    0,              0,              D32,    0 },
+{"bposge32c",          "p",            0x04180000, 0xffff0000, NODS,                   FS,             0,              D34,    0 },
 {"bposge64",           "p",            0x041d0000, 0xffff0000, CBD,                    0,              0,              D64,    0 },
 {"cmp.eq.ph",          "s,t",          0x7c000211, 0xfc00ffff, RD_1|RD_2,              0,              0,              D32,    0 },
 {"cmp.eq.pw",          "s,t",          0x7c000415, 0xfc00ffff, RD_1|RD_2,              0,              0,              D64,    0 },
@@ -3010,8 +3012,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"copy_s.d",           "+k,+e+w",      0x78b80019, 0xfffe003f, WR_1|RD_2,              0,              0,              MSA64,  0 },
 {"copy_u.b",           "+k,+e+o",      0x78c00019, 0xfff0003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"copy_u.h",           "+k,+e+u",      0x78e00019, 0xfff8003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"copy_u.w",           "+k,+e+v",      0x78f00019, 0xfffc003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"copy_u.d",           "+k,+e+w",      0x78f80019, 0xfffe003f, WR_1|RD_2,              0,              0,              MSA64,  0 },
+{"copy_u.w",           "+k,+e+v",      0x78f00019, 0xfffc003f, WR_1|RD_2,              0,              0,              MSA64,  0 },
 {"insert.b",           "+d+o,d",       0x79000019, 0xfff0003f, MOD_1|RD_3,             0,              0,              MSA,    0 },
 {"insert.h",           "+d+u,d",       0x79200019, 0xfff8003f, MOD_1|RD_3,             0,              0,              MSA,    0 },
 {"insert.w",           "+d+v,d",       0x79300019, 0xfffc003f, MOD_1|RD_3,             0,              0,              MSA,    0 },